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From: Ritesh Harjani <riteshh@codeaurora.org>
To: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org,
	adrian.hunter@intel.com, sboyd@codeaurora.org,
	andy.gross@linaro.org
Cc: shawn.lin@rock-chips.com, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, david.brown@linaro.org,
	linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org,
	alex.lemberg@sandisk.com, mateusz.nowak@intel.com,
	Yuliy.Izrailov@sandisk.com, asutoshd@codeaurora.org,
	david.griego@linaro.org, stummala@codeaurora.org,
	venkatg@codeaurora.org, rnayak@codeaurora.org,
	pramod.gurav@linaro.org, jeremymc@redhat.com,
	Ritesh Harjani <riteshh@codeaurora.org>
Subject: [PATCH v9 14/16] mmc: sdhci-msm: Save the calculated tuning phase
Date: Mon, 21 Nov 2016 12:07:24 +0530	[thread overview]
Message-ID: <1479710246-26676-15-git-send-email-riteshh@codeaurora.org> (raw)
In-Reply-To: <1479710246-26676-1-git-send-email-riteshh@codeaurora.org>

Save the tuning phase once the tuning is performed.
This phase value will be used while calibrating DLL
for HS400 mode.

Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
 drivers/mmc/host/sdhci-msm.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index b1888c3..f4f277b 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -75,6 +75,7 @@
 
 #define CORE_VENDOR_SPEC_CAPABILITIES0	0x11c
 
+#define INVALID_TUNING_PHASE	-1
 #define SDHCI_MSM_MIN_CLOCK	400000
 #define CORE_FREQ_100MHZ	(100 * 1000 * 1000)
 
@@ -97,6 +98,7 @@ struct sdhci_msm_host {
 	bool use_14lpp_dll_reset;
 	bool tuning_done;
 	bool calibration_done;
+	u8 saved_tuning_phase;
 };
 
 /* Platform specific tuning */
@@ -136,6 +138,9 @@ static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
 	u32 config;
 	struct mmc_host *mmc = host->mmc;
 
+	if (phase > 0xf)
+		return -EINVAL;
+
 	spin_lock_irqsave(&host->lock, flags);
 
 	config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
@@ -429,6 +434,8 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
 	int rc;
 	struct mmc_host *mmc = host->mmc;
 	struct mmc_ios ios = host->mmc->ios;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 
 	/*
 	 * Tuning is required for SDR104, HS200 and HS400 cards and
@@ -453,6 +460,7 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
 		if (rc)
 			return rc;
 
+		msm_host->saved_tuning_phase = phase;
 		rc = mmc_send_tuning(mmc, opcode, NULL);
 		if (!rc) {
 			/* Tuning is successful at this tuning point */
@@ -799,6 +807,8 @@ static int sdhci_msm_probe(struct platform_device *pdev)
 
 	sdhci_get_of_property(pdev);
 
+	msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
+
 	/* Setup SDCC bus voter clock. */
 	msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
 	if (!IS_ERR(msm_host->bus_clk)) {
-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
a Linux Foundation Collaborative Project.


  parent reply	other threads:[~2016-11-21  6:37 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-21  6:37 [PATCH v9 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support Ritesh Harjani
2016-11-21  6:37 ` [PATCH v9 01/16] clk: qcom: Add rcg ops to return floor value closest to the requested rate Ritesh Harjani
     [not found]   ` <1479710246-26676-2-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-23 19:00     ` Stephen Boyd
2016-11-21  6:37 ` [PATCH v9 02/16] clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops Ritesh Harjani
2016-11-23 19:00   ` Stephen Boyd
2016-11-21  6:37 ` [PATCH v9 03/16] mmc: sdhci-msm: Change poor style writel/readl of registers Ritesh Harjani
2016-11-21  6:37 ` [PATCH v9 04/16] ARM: dts: Add xo to sdhc clock node on qcom platforms Ritesh Harjani
2016-11-21  6:37 ` [PATCH v9 05/16] dt-bindings: sdhci-msm: Add xo value Ritesh Harjani
2016-11-21  6:37 ` [PATCH v9 06/16] mmc: sdhci-msm: Update DLL reset sequence Ritesh Harjani
2016-11-21  6:37 ` [PATCH v9 07/16] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback Ritesh Harjani
2017-04-26 21:44   ` Andy Gross
2017-04-27  7:58     ` Georgi Djakov
2016-11-21  6:37 ` [PATCH v9 08/16] mmc: sdhci-msm: Enable few quirks Ritesh Harjani
2016-11-21  6:37 ` [PATCH v9 09/16] mmc: sdhci: Factor out sdhci_enable_clk Ritesh Harjani
     [not found]   ` <1479710246-26676-10-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-21  7:45     ` Adrian Hunter
2016-11-21  6:37 ` [PATCH v9 11/16] mmc: sdhci-msm: Add clock changes for DDR mode Ritesh Harjani
2016-11-21  6:37 ` [PATCH v9 12/16] arm64: dts: qcom: msm8916: Add ddr support to sdhc1 Ritesh Harjani
     [not found] ` <1479710246-26676-1-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-21  6:37   ` [PATCH v9 10/16] mmc: sdhci-msm: Implement set_clock callback for sdhci-msm Ritesh Harjani
2016-11-21  6:37   ` [PATCH v9 13/16] mmc: sdhci-msm: Add HS400 platform support Ritesh Harjani
2016-11-21  6:37   ` [PATCH v9 16/16] sdhci: sdhci-msm: update dll configuration Ritesh Harjani
2016-11-21 10:06   ` [PATCH v9 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support Ulf Hansson
2016-11-21 11:42     ` Ritesh Harjani
     [not found]       ` <d4d05fb9-8a9e-6cf2-dc63-0edbd27a9e55-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-21 23:11         ` Stephen Boyd
2016-11-23  0:05           ` Ritesh Harjani
     [not found]             ` <6dd874b4-8f60-471b-d1e7-089b4b035ad2-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-23 12:49               ` Ulf Hansson
2016-11-23  5:00     ` Andy Gross
2016-11-23  8:32       ` Ulf Hansson
2016-11-21  6:37 ` Ritesh Harjani [this message]
2016-11-21  6:37 ` [PATCH v9 15/16] mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit Ritesh Harjani

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