* [PATCH 0/5] Enable onboard SDHCI for Nexus 5X (msm8992)
@ 2016-11-23 1:09 Jeremy McNicoll
2016-11-23 1:09 ` [PATCH 1/5] clk: gcc: Updates for SDHCI enablement Jeremy McNicoll
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Jeremy McNicoll @ 2016-11-23 1:09 UTC (permalink / raw)
To: linux-arm-msm, linux-soc, devicetree, linux-mmc
Cc: andy.gross, sboyd, robh, arnd, bjorn.andersson, riteshh, jeremymc
Now that the basic board support is available:
http://www.spinics.net/lists/linux-arm-msm/msg24533.html
and the associated clock changes have been picked up for next,
http://www.spinics.net/lists/linux-arm-msm/msg24499.html
Using V8 from Ritesh Harjani, with the additional changes provided to him for gcc-msm8994.c
[ http://www.spinics.net/lists/linux-arm-msm/msg24652.html ]
Additionally V9 of the RPM clock support [http://www.spinics.net/lists/linux-arm-msm/msg24211.html]
is needed.
At this point, "qcom,rpmcc-msm8916" was used successfully for testing of
the rpm clock controller. It has been marked as a TODO item in the DTS
and once the rpmcc clocks are added for 8992/8994 the needed change will
be made. i.e.) expect a follow up patch for rpmcc
Currently, the minimal regulators to verify / enable SDHCI functionality
have been added. While looking at the downstream code, I saw a few more
obvious entries so they have been included (completely untested). Hopefully
someone with the hardware docs can provide feedback and/or an individual
with better eye site than I who can ferret out more of the entries from
downstream.
The nonremovable "keyword/flag" was used to assess the reliability of the
initial mmc detection. When the flag is present in the DTS only 1 check
for SDHCI was made, without non removable it checks over and over again.
Without the workaround (patch 5/5) mmc/sdhci didn't get detected 8/20
times. When including the afore mentioned workaround MMC detection is
100% (35 boots) .
While at it, I took the liberty of re-tabifying include/dt-bindings/
clock/qcom,gcc-msm8994.h to make it look nice according to VIM using (:set list ).
Sorry emacs users, you are on your own.
Question:
In what DT-bindings txt file should the following, compatible = "qcom,rpm-msm8994";
be placed? (arch/arm64/boot/dts/qcom/msm8992.dtsi, rpm_requests node)
Obviously, this is a work in progress, and its progressing :-)
Jeremy McNicoll (5):
clk: gcc: Updates for SDHCI enablement
smd: Make packet size a constant
arm64: dts: Enable SDHCI for Nexus 5X (msm8992)
sdhci: dump vendor state and regs
sdhci: Add quirk for delayed IRQ ACK
.../bindings/regulator/qcom,smd-rpm-regulator.txt | 40 ++++
.../boot/dts/qcom/msm8992-bullhead-rev-101.dts | 262 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 82 +++++++
arch/arm64/boot/dts/qcom/msm8992.dtsi | 153 ++++++++++++
drivers/clk/qcom/gcc-msm8994.c | 108 +++++++--
drivers/mmc/host/sdhci-msm.c | 86 +++++++
drivers/mmc/host/sdhci.c | 37 ++-
drivers/mmc/host/sdhci.h | 3 +
drivers/regulator/qcom_smd-regulator.c | 49 ++++
drivers/soc/qcom/smd-rpm.c | 2 +-
include/dt-bindings/clock/qcom,gcc-msm8994.h | 32 ++-
include/linux/soc/qcom/smd.h | 7 +
12 files changed, 824 insertions(+), 37 deletions(-)
--
2.6.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 1/5] clk: gcc: Updates for SDHCI enablement 2016-11-23 1:09 [PATCH 0/5] Enable onboard SDHCI for Nexus 5X (msm8992) Jeremy McNicoll @ 2016-11-23 1:09 ` Jeremy McNicoll 2016-11-23 1:09 ` [PATCH 2/5] smd: Make packet size a constant Jeremy McNicoll ` (3 subsequent siblings) 4 siblings, 0 replies; 13+ messages in thread From: Jeremy McNicoll @ 2016-11-23 1:09 UTC (permalink / raw) To: linux-arm-msm, linux-soc, devicetree, linux-mmc Cc: andy.gross, sboyd, robh, arnd, bjorn.andersson, riteshh, jeremymc Global clock updates to enable onboard SDHCI / MMC. Re-tabify dt-bindings to align correctly in vim. Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> --- drivers/clk/qcom/gcc-msm8994.c | 108 +++++++++++++++++++++------ include/dt-bindings/clock/qcom,gcc-msm8994.h | 32 ++++---- 2 files changed, 106 insertions(+), 34 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index e3d15e4..5a8ff2a 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -24,6 +24,7 @@ #include "common.h" #include "clk-regmap.h" +#include "clk-pll.h" #include "clk-alpha-pll.h" #include "clk-rcg.h" #include "clk-branch.h" @@ -54,7 +55,7 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { static const char * const gcc_xo_gpll0_gpll4[] = { "xo", "gpll0", - "gpll4", + "gpll4_vote", }; #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } @@ -97,29 +98,65 @@ static struct clk_alpha_pll_postdiv gpll0 = { }, }; -static struct clk_alpha_pll gpll4_early = { - .offset = 0x1dc0, - .clkr = { - .enable_reg = 0x1480, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data) - { - .name = "gpll4_early", - .parent_names = (const char *[]) { "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, + +static struct clk_rcg2 config_noc_clk_src = { + .cmd_rcgr = 0x0150, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "config_noc_clk_src", + .parent_names = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 periph_noc_clk_src = { + .cmd_rcgr = 0x0190, + .hid_width = 5, + .mnd_width = 8, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "periph_noc_clk_src", + .parent_names = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 system_noc_clk_src = { + .cmd_rcgr = 0x0120, //TODO + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data) { + .name = "system_noc_clk_src", + .parent_names = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, }, }; -static struct clk_alpha_pll_postdiv gpll4 = { - .offset = 0x1dc0, +static struct clk_pll gpll4 = { + .status_reg = 0x1dc0, + .status_bit = 30, .clkr.hw.init = &(struct clk_init_data) { .name = "gpll4", - .parent_names = (const char *[]) { "gpll4_early" }, + .parent_names = (const char *[]) { "xo" }, .num_parents = 1, - .ops = &clk_alpha_pll_postdiv_ops, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll4_vote = { + .enable_reg = 0x1480, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data) + { + .name = "gpll4_vote", + .parent_names = (const char *[]) { "gpll4" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, }, }; @@ -896,8 +933,8 @@ static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { F(25000000, P_GPLL0, 12, 1, 2), F(50000000, P_GPLL0, 12, 0, 0), F(100000000, P_GPLL0, 6, 0, 0), - F(192000000, P_GPLL4, 2, 0, 0), - F(384000000, P_GPLL4, 1, 0, 0), + F(172000000, P_GPLL4, 2, 0, 0), + F(344000000, P_GPLL4, 1, 0, 0), { } }; @@ -1057,6 +1094,10 @@ static struct clk_branch gcc_blsp1_ahb_clk = { .hw.init = &(struct clk_init_data) { .name = "gcc_blsp1_ahb_clk", + .parent_names = (const char *[]){ + "periph_noc_clk_src", + }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1872,6 +1913,7 @@ static struct clk_branch gcc_pdm2_clk = { static struct clk_branch gcc_sdcc1_apps_clk = { .halt_reg = 0x04c4, + .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x04c4, .enable_mask = BIT(0), @@ -1888,6 +1930,26 @@ static struct clk_branch gcc_sdcc1_apps_clk = { }, }; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0x04c8, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x04c8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_sdcc1_ahb_clk", + .parent_names = (const char *[]){ + "periph_noc_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + + static struct clk_branch gcc_sdcc2_apps_clk = { .halt_reg = 0x0504, .clkr = { @@ -2123,10 +2185,13 @@ static struct clk_branch gcc_usb_hs_system_clk = { }; static struct clk_regmap *gcc_msm8994_clocks[] = { - [GPLL0_EARLY] = &gpll0_early.clkr, + [GPLL0_VOTE] = &gpll0_early.clkr, [GPLL0] = &gpll0.clkr, - [GPLL4_EARLY] = &gpll4_early.clkr, + [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, + [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, + [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, [GPLL4] = &gpll4.clkr, + [GPLL4_VOTE] = &gpll4_vote, [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, @@ -2231,6 +2296,7 @@ static struct clk_regmap *gcc_msm8994_clocks[] = { [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h index 0ae494b..76ef541 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8994.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h @@ -15,10 +15,10 @@ #ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H #define _DT_BINDINGS_CLK_MSM_GCC_8994_H -#define GPLL0_EARLY 0 #define GPLL0 1 -#define GPLL4_EARLY 2 -#define GPLL4 3 +#define GPLL0_VOTE 0 +#define GPLL4 2 +#define GPLL4_VOTE 3 #define UFS_AXI_CLK_SRC 4 #define USB30_MASTER_CLK_SRC 5 #define BLSP1_QUP1_I2C_APPS_CLK_SRC 6 @@ -123,16 +123,22 @@ #define GCC_SDCC2_APPS_CLK 105 #define GCC_SDCC3_APPS_CLK 106 #define GCC_SDCC4_APPS_CLK 107 -#define GCC_SYS_NOC_UFS_AXI_CLK 108 -#define GCC_SYS_NOC_USB3_AXI_CLK 109 -#define GCC_TSIF_REF_CLK 110 -#define GCC_UFS_AXI_CLK 111 -#define GCC_UFS_RX_CFG_CLK 112 -#define GCC_UFS_TX_CFG_CLK 113 -#define GCC_USB30_MASTER_CLK 114 -#define GCC_USB30_MOCK_UTMI_CLK 115 -#define GCC_USB3_PHY_AUX_CLK 116 -#define GCC_USB_HS_SYSTEM_CLK 117 +#define GCC_SDCC1_AHB_CLK 108 +#define GCC_SDCC2_AHB_CLK 109 + +#define GCC_SYS_NOC_UFS_AXI_CLK 110 +#define GCC_SYS_NOC_USB3_AXI_CLK 111 +#define GCC_TSIF_REF_CLK 112 +#define GCC_UFS_AXI_CLK 113 +#define GCC_UFS_RX_CFG_CLK 114 +#define GCC_UFS_TX_CFG_CLK 115 +#define GCC_USB30_MASTER_CLK 116 +#define GCC_USB30_MOCK_UTMI_CLK 117 +#define GCC_USB3_PHY_AUX_CLK 118 +#define GCC_USB_HS_SYSTEM_CLK 119 +#define SYSTEM_NOC_CLK_SRC 120 +#define PERIPH_NOC_CLK_SRC 121 +#define CONFIG_NOC_CLK_SRC 122 /* Indexes for GDSCs */ #define BIMC_GDSC 0 -- 2.6.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/5] smd: Make packet size a constant 2016-11-23 1:09 [PATCH 0/5] Enable onboard SDHCI for Nexus 5X (msm8992) Jeremy McNicoll 2016-11-23 1:09 ` [PATCH 1/5] clk: gcc: Updates for SDHCI enablement Jeremy McNicoll @ 2016-11-23 1:09 ` Jeremy McNicoll 2016-11-24 6:14 ` Bjorn Andersson 2016-11-23 1:09 ` [PATCH 3/5] arm64: dts: Enable SDHCI for Nexus 5X (msm8992) Jeremy McNicoll ` (2 subsequent siblings) 4 siblings, 1 reply; 13+ messages in thread From: Jeremy McNicoll @ 2016-11-23 1:09 UTC (permalink / raw) To: linux-arm-msm, linux-soc, devicetree, linux-mmc Cc: andy.gross, sboyd, robh, arnd, bjorn.andersson, riteshh, jeremymc Use a macro to define the maximum size of a RPM message. Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> --- drivers/soc/qcom/smd-rpm.c | 2 +- include/linux/soc/qcom/smd.h | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index 6609d7e..b5a2836 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -114,7 +114,7 @@ int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, size_t size = sizeof(*pkt) + count; /* SMD packets to the RPM may not exceed 256 bytes */ - if (WARN_ON(size >= 256)) + if (WARN_ON(size >= SMD_RPM_MAX_SIZE)) return -EINVAL; pkt = kmalloc(size, GFP_KERNEL); diff --git a/include/linux/soc/qcom/smd.h b/include/linux/soc/qcom/smd.h index f148e0f..8039015 100644 --- a/include/linux/soc/qcom/smd.h +++ b/include/linux/soc/qcom/smd.h @@ -4,6 +4,13 @@ #include <linux/device.h> #include <linux/mod_devicetable.h> + +/* + * SMD packets to the RPM may not exceed 256 bytes + */ +#define SMD_RPM_MAX_SIZE 256 + + struct qcom_smd; struct qcom_smd_channel; struct qcom_smd_lookup; -- 2.6.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 2/5] smd: Make packet size a constant 2016-11-23 1:09 ` [PATCH 2/5] smd: Make packet size a constant Jeremy McNicoll @ 2016-11-24 6:14 ` Bjorn Andersson 2016-11-28 21:20 ` Jeremy McNicoll 0 siblings, 1 reply; 13+ messages in thread From: Bjorn Andersson @ 2016-11-24 6:14 UTC (permalink / raw) To: Jeremy McNicoll Cc: linux-arm-msm, linux-soc, devicetree, linux-mmc, andy.gross, sboyd, robh, arnd, riteshh On Tue 22 Nov 17:09 PST 2016, Jeremy McNicoll wrote: > Use a macro to define the maximum size of a RPM message. > No thanks. > Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> > --- > drivers/soc/qcom/smd-rpm.c | 2 +- > include/linux/soc/qcom/smd.h | 7 +++++++ > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c > index 6609d7e..b5a2836 100644 > --- a/drivers/soc/qcom/smd-rpm.c > +++ b/drivers/soc/qcom/smd-rpm.c > @@ -114,7 +114,7 @@ int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, > size_t size = sizeof(*pkt) + count; > > /* SMD packets to the RPM may not exceed 256 bytes */ > - if (WARN_ON(size >= 256)) > + if (WARN_ON(size >= SMD_RPM_MAX_SIZE)) > return -EINVAL; The only thing you do is to change "oh, the max packet size is 256 bytes" to "hmm, i wonder what SMD_RPM_MAX_SIZE is and if the comment is still valid". > > pkt = kmalloc(size, GFP_KERNEL); > diff --git a/include/linux/soc/qcom/smd.h b/include/linux/soc/qcom/smd.h > index f148e0f..8039015 100644 > --- a/include/linux/soc/qcom/smd.h > +++ b/include/linux/soc/qcom/smd.h > @@ -4,6 +4,13 @@ > #include <linux/device.h> > #include <linux/mod_devicetable.h> > > + > +/* > + * SMD packets to the RPM may not exceed 256 bytes > + */ > +#define SMD_RPM_MAX_SIZE 256 > + And this has nothing to do with SMD, it's a limitation of RPM. Regards, Bjorn ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/5] smd: Make packet size a constant 2016-11-24 6:14 ` Bjorn Andersson @ 2016-11-28 21:20 ` Jeremy McNicoll 0 siblings, 0 replies; 13+ messages in thread From: Jeremy McNicoll @ 2016-11-28 21:20 UTC (permalink / raw) To: Bjorn Andersson Cc: Jeremy McNicoll, linux-arm-msm, linux-soc, devicetree, linux-mmc, andy.gross, sboyd, robh, arnd, riteshh On Wed, Nov 23, 2016 at 10:14:50PM -0800, Bjorn Andersson wrote: > On Tue 22 Nov 17:09 PST 2016, Jeremy McNicoll wrote: > > > Use a macro to define the maximum size of a RPM message. > > > > No thanks. > Sure, will drop this change with V2 in a few days so that people have a chance to provide feedback. -jeremy ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/5] arm64: dts: Enable SDHCI for Nexus 5X (msm8992) 2016-11-23 1:09 [PATCH 0/5] Enable onboard SDHCI for Nexus 5X (msm8992) Jeremy McNicoll 2016-11-23 1:09 ` [PATCH 1/5] clk: gcc: Updates for SDHCI enablement Jeremy McNicoll 2016-11-23 1:09 ` [PATCH 2/5] smd: Make packet size a constant Jeremy McNicoll @ 2016-11-23 1:09 ` Jeremy McNicoll [not found] ` <1479863388-23678-4-git-send-email-jeremymc-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> 2016-11-23 1:09 ` [PATCH 4/5] sdhci: dump vendor state and regs Jeremy McNicoll 2016-11-23 1:09 ` [PATCH 5/5] sdhci: Add quirk for delayed IRQ ACK Jeremy McNicoll 4 siblings, 1 reply; 13+ messages in thread From: Jeremy McNicoll @ 2016-11-23 1:09 UTC (permalink / raw) To: linux-arm-msm, linux-soc, devicetree, linux-mmc Cc: andy.gross, sboyd, robh, arnd, bjorn.andersson, riteshh, jeremymc Add Nexus 5X (msm8992) SDHCI support, including initial regulator entries to support enabling the main SDHCI/MMC. The msm8994 RPM regulator talks over SMD to the APPS processor. Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> --- .../bindings/regulator/qcom,smd-rpm-regulator.txt | 40 ++++ .../boot/dts/qcom/msm8992-bullhead-rev-101.dts | 262 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 82 +++++++ arch/arm64/boot/dts/qcom/msm8992.dtsi | 153 ++++++++++++ drivers/regulator/qcom_smd-regulator.c | 49 ++++ 5 files changed, 586 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt index 1f8d6f8..126989b 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt @@ -23,6 +23,7 @@ Regulator nodes are identified by their compatible: "qcom,rpm-pm8916-regulators" "qcom,rpm-pm8941-regulators" "qcom,rpm-pma8084-regulators" + "qcom,rpm-pm8994-regulators" - vdd_s1-supply: - vdd_s2-supply: @@ -97,6 +98,40 @@ Regulator nodes are identified by their compatible: Definition: reference to regulator supplying the input pin, as described in the data sheet +- vdd_s1-supply: +- vdd_s2-supply: +- vdd_s3-supply: +- vdd_s4-supply: +- vdd_s5-supply: +- vdd_s6-supply: +- vdd_s7-supply: +- vdd_l1_l11-supply: +- vdd_l2_l3_l4_l27-supply: +- vdd_l5_l7-supply: +- vdd_l6_l12_l14_l15_l26-supply: +- vdd_l8-supply: +- vdd_l9_l10_l13_l20_l23_l24-supply: +- vdd_l1_l11-supply: +- vdd_l6_l12_l14_l15_l26-supply: +- vdd_l16_l25-supply: +- vdd_l17-supply: +- vdd_l18-supply: +- vdd_l19-supply: +- vdd_l21-supply: +- vdd_l22-supply: +- vdd_l16_l25-supply: +- vdd_l27-supply: +- vdd_l28-supply: +- vdd_l29-supply: +- vdd_l30-supply: +- vdd_l31-supply: +- vdd_l32-supply: + Usage: optional (pm8994 only) + Value type: <phandle> + Definition: reference to regulator supplying the input pin, as + described in the data sheet. + + The regulator node houses sub-nodes for each regulator within the device. Each sub-node is identified using the node's name, with valid values listed for each of the pmics below. @@ -118,6 +153,11 @@ pma8084: l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1 +pm8994: + s1, s2, s3, s4, s5, s6, s7, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, + l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, + l27, l28, l29, l30, l31, l32, lvs1, lvs2 + The content of each sub-node is defined by the standard binding for regulators - see regulator.txt. diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts index 4542133..2ce8798 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts @@ -39,3 +39,265 @@ }; }; }; + +&smd_rpm { + rpm { + rpm_requests { + pm8994-regulators { + + vdd_l1-supply = <&pm8994_s1>; + vdd_l2_26_28-supply = <&pm8994_s3>; + vdd_l3_11-supply = <&pm8994_s3>; + vdd_l4_27_31-supply = <&pm8994_s3>; + vdd_l5_7-supply = <&pm8994_s3>; + vdd_l6_12_32-supply = <&pm8994_s5>; + vdd_l8_16_30-supply = <&vreg_vph_pwr>; + vdd_l9_10_18_22-supply = <&vreg_vph_pwr>; + vdd_l13_19_23_24-supply = <&vreg_vph_pwr>; + vdd_l14_15-supply = <&pm8994_s5>; + vdd_l17_29-supply = <&vreg_vph_pwr>; + vdd_l20_21-supply = <&vreg_vph_pwr>; + vdd_l25-supply = <&pm8994_s5>; + /*vin_lvs1_2 = <&pm8994_s4>; */ + + s1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + s2 { + }; + + s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-system-load = <325000>; + }; + + s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + s7 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + l2 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + }; + + l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l5 { + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + }; + + l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + }; + + l11 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + proxy-supply = <&pm8994_l12>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <10000>; + status = "okay"; + }; + + l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <2950000>; + status = "okay"; + }; + + l14 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + proxy-supply = <&pm8994_l14>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <10000>; + status = "okay"; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + qcom,init-voltage = <2700000>; + status = "okay"; + }; + + l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + qcom,init-voltage = <2700000>; + status = "okay"; + }; + + l18 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + qcom,init-voltage = <3000000>; + qcom,init-ldo-mode = <1>; + }; + + l19 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-system-load = <570000>; + }; + + l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + qcom,init-voltage = <1800000>; + }; + + l22 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + qcom,init-voltage = <3100000>; + }; + + l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + }; + + l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3150000>; + qcom,init-voltage = <3075000>; + }; + + l25 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + }; + + l26 { + /* TODO: value from downstream + regulator-min-microvolt = <987500>; + fails to apply */ + }; + + l27 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <1050000>; + }; + + l28 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <1000000>; + proxy-supply = <&pm8994_l28>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <10000>; + }; + + l29 { + /* TODO: Unsupported voltage range.. + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + */ + }; + + l30 { + /* TODO: get this verified + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + */ + }; + + l31 { + regulator-min-microvolt = <1262500>; + regulator-max-microvolt = <1262500>; + qcom,init-voltage = <1262500>; + }; + + l32 { + /* TODO: get this verified + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + */ + }; + + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi index d2a26f0..15202c8 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi @@ -35,4 +35,86 @@ bias-pull-down; }; }; + + /* 0-3 for sdc1 4-6 for sdc2 */ + /* Order of pins */ + /* SDC1: CLK -> 0, CMD -> 1, DATA -> 2, RCLK -> 3 */ + /* SDC2: CLK -> 4, CMD -> 5, DATA -> 6 */ + pmx_sdc1_clk { + sdc1_clk_on: clk_on { + pinmux { + pins = "sdc1_clk"; + }; + pinconf { + pins = "sdc1_clk"; + bias-disable = <0>; /* No pull */ + drive-strength = <16>; /* 16mA */ + }; + }; + sdc1_clk_off: clk_off { + pinmux { + pins = "sdc1_clk"; + }; + pinconf { + pins = "sdc1_clk"; + bias-disable = <0>; /* No pull */ + drive-strength = <2>; /* 2mA */ + }; + }; + }; + + pmx_sdc1_cmd { + sdc1_cmd_on: cmd_on { + pinmux { + pins = "sdc1_cmd"; + }; + pinconf { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <8>; + }; + }; + sdc1_cmd_off: cmd_off { + pinmux { + pins = "sdc1_cmd"; + }; + pinconf { + pins = "sdc1_cmd"; + bias-pull-up = <0x3>; /* same as 3.10 ?? */ + drive-strength = <2>; /* 2mA */ + }; + }; + }; + + pmx_sdc1_data { + sdc1_data_on: data_on { + pinmux { + pins = "sdc1_data"; + }; + pinconf { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <8>; /* 8mA */ + }; + }; + sdc1_data_off: data_off { + pinmux { + pins = "sdc1_data"; + }; + pinconf { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + }; + + pmx_sdc1_rclk { + sdc1_rclk_on: rclk_on { + bias-pull-down; /* pull down */ + }; + sdc1_rclk_off: rclk_off { + bias-pull-down; /* pull down */ + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 44b2d37..d104770 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -82,6 +82,12 @@ <0xf9002000 0x1000>; }; + apcs: syscon@0xf900d000 { + compatible = "syscon"; + reg = <0xf900d000 0x2000>; + }; + + timer@f9020000 { #address-cells = <1>; #size-cells = <1>; @@ -172,12 +178,159 @@ #power-domain-cells = <1>; reg = <0xfc400000 0x2000>; }; + + sdhci1: qcom,sdhci@f9824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>, + <GIC_SPI 138 IRQ_TYPE_NONE>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&clock_gcc GCC_SDCC1_APPS_CLK>, + <&clock_gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on + &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off + &sdc1_rclk_off>; + + vdd-supply = <&pm8994_l20>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <200 570000>; + + vdd-io-supply = <&pm8994_s4>; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 325000>; + + regulator-always-on; + bus-width = <8>; + mmc-hs400-1_8v; + status = "okay"; + }; + + vreg_vph_pwr: vreg-vph-pwr { + compatible = "regulator-fixed"; + status = "okay"; + regulator-name = "vph-pwr"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + regulator-always-on; + }; + + rpm_msg_ram: memory@fc428000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0xfc428000 0x4000>; + }; + + sfpb_mutex_regs: syscon@fd484000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "syscon"; + reg = <0xfd484000 0x400>; + }; + + sfpb_mutex: hwmutex { + compatible = "qcom,sfpb-mutex"; + syscon = <&sfpb_mutex_regs 0x0 0x100>; + #hwlock-cells = <1>; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + hwlocks = <&sfpb_mutex 3>; + }; }; memory { device_type = "memory"; reg = <0 0 0 0>; // bootloader will update }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + smem_region: smem@6a00000 { + reg = <0x0 0x6a00000 0x0 0x200000>; + no-map; + }; + }; + + smd_rpm: smd { + compatible = "qcom,smd"; + + rpm { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + qcom,local-pid = <0>; + qcom,remote-pid = <6>; + + rpm_requests { + compatible = "qcom,rpm-msm8994"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: qcom,rpmcc { + /* TODO: update when rpmcc-msm8994 support added */ + compatible = "qcom,rpmcc-msm8916", + "qcom,rpmcc"; + #clock-cells = <1>; + }; + + smd_rpm_regulators: pm8994-regulators { + compatible = "qcom,rpm-pm8994-regulators"; + + pm8994_s1: s1 {}; + pm8994_s2: s2 {}; + pm8994_s3: s3 {}; + pm8994_s4: s4 {}; + pm8994_s5: s5 {}; + pm8994_s6: s6 {}; + pm8994_s7: s7 {}; + + pm8994_l1: l1 {}; + pm8994_l2: l2 {}; + pm8994_l3: l3 {}; + pm8994_l4: l4 {}; + pm8994_l6: l6 {}; + pm8994_l8: l8 {}; + pm8994_l9: l9 {}; + pm8994_l10: l10 {}; + pm8994_l11: l11 {}; + pm8994_l12: l12 {}; + pm8994_l13: l13 {}; + pm8994_l14: l14 {}; + pm8994_l15: l15 {}; + pm8994_l16: l16 {}; + pm8994_l17: l17 {}; + pm8994_l18: l18 {}; + pm8994_l19: l19 {}; + pm8994_l20: l20 {}; + pm8994_l21: l21 {}; + pm8994_l22: l22 {}; + pm8994_l23: l23 {}; + pm8994_l24: l24 {}; + pm8994_l25: l25 {}; + pm8994_l26: l26 {}; + pm8994_l27: l27 {}; + pm8994_l28: l28 {}; + pm8994_l29: l29 {}; + pm8994_l30: l30 {}; + pm8994_l31: l31 {}; + pm8994_l32: l32 {}; + }; + }; + }; + }; }; diff --git a/drivers/regulator/qcom_smd-regulator.c b/drivers/regulator/qcom_smd-regulator.c index 8ed46a9..a7e8ce7 100644 --- a/drivers/regulator/qcom_smd-regulator.c +++ b/drivers/regulator/qcom_smd-regulator.c @@ -443,11 +443,60 @@ static const struct rpm_regulator_data rpm_pma8084_regulators[] = { {} }; +static const struct rpm_regulator_data rpm_pm8994_regulators[] = { + { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" }, + { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" }, + { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" }, + { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" }, + { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" }, + { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" }, + { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" }, + + { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" }, + { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, + { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, + { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, + { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" }, + { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, + { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" }, + { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" }, + { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, + { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, + { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" }, + { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, + { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, + { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, + { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, + { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" }, + { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" }, + { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" }, + { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" }, + { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, + { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" }, + { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" }, + { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, + { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, + { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" }, + { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, + { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l27" }, + { "l28", QCOM_SMD_RPM_LDOA, 28, &pma8084_nldo, "vdd_l28" }, + { "l29", QCOM_SMD_RPM_LDOA, 29, &pma8084_nldo, "vdd_l29" }, + { "l30", QCOM_SMD_RPM_LDOA, 30, &pma8084_nldo, "vdd_l30" }, + { "l31", QCOM_SMD_RPM_LDOA, 31, &pma8084_nldo, "vdd_l31" }, + { "l32", QCOM_SMD_RPM_LDOA, 32, &pma8084_nldo, "vdd_l32" }, + + { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch }, + { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch }, + + {} +}; + static const struct of_device_id rpm_of_match[] = { { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators }, { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators }, { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators }, { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators }, + { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators }, {} }; MODULE_DEVICE_TABLE(of, rpm_of_match); -- 2.6.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
[parent not found: <1479863388-23678-4-git-send-email-jeremymc-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH 3/5] arm64: dts: Enable SDHCI for Nexus 5X (msm8992) [not found] ` <1479863388-23678-4-git-send-email-jeremymc-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> @ 2016-11-28 21:53 ` Rob Herring 0 siblings, 0 replies; 13+ messages in thread From: Rob Herring @ 2016-11-28 21:53 UTC (permalink / raw) To: Jeremy McNicoll Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, linux-soc-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-mmc-u79uwXL29TY76Z2rM5mHXA, andy.gross-QSEj5FYQhm4dnm+yROfE0A, sboyd-sgV2jX0FEOL9JmXXK+q4OQ, arnd-r2nGTMty4D4, bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A, riteshh-sgV2jX0FEOL9JmXXK+q4OQ On Tue, Nov 22, 2016 at 05:09:46PM -0800, Jeremy McNicoll wrote: > Add Nexus 5X (msm8992) SDHCI support, including initial regulator > entries to support enabling the main SDHCI/MMC. > > The msm8994 RPM regulator talks over SMD to the APPS processor. > > Signed-off-by: Jeremy McNicoll <jeremymc-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> > --- > .../bindings/regulator/qcom,smd-rpm-regulator.txt | 40 ++++ > .../boot/dts/qcom/msm8992-bullhead-rev-101.dts | 262 +++++++++++++++++++++ > arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 82 +++++++ > arch/arm64/boot/dts/qcom/msm8992.dtsi | 153 ++++++++++++ > drivers/regulator/qcom_smd-regulator.c | 49 ++++ > 5 files changed, 586 insertions(+) A few nits, otherwise, Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> > > diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt > index 1f8d6f8..126989b 100644 > --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt > +++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt > @@ -23,6 +23,7 @@ Regulator nodes are identified by their compatible: > "qcom,rpm-pm8916-regulators" > "qcom,rpm-pm8941-regulators" > "qcom,rpm-pma8084-regulators" > + "qcom,rpm-pm8994-regulators" > > - vdd_s1-supply: > - vdd_s2-supply: > @@ -97,6 +98,40 @@ Regulator nodes are identified by their compatible: > Definition: reference to regulator supplying the input pin, as > described in the data sheet > > +- vdd_s1-supply: > +- vdd_s2-supply: > +- vdd_s3-supply: > +- vdd_s4-supply: > +- vdd_s5-supply: > +- vdd_s6-supply: > +- vdd_s7-supply: > +- vdd_l1_l11-supply: > +- vdd_l2_l3_l4_l27-supply: > +- vdd_l5_l7-supply: > +- vdd_l6_l12_l14_l15_l26-supply: > +- vdd_l8-supply: > +- vdd_l9_l10_l13_l20_l23_l24-supply: > +- vdd_l1_l11-supply: > +- vdd_l6_l12_l14_l15_l26-supply: > +- vdd_l16_l25-supply: > +- vdd_l17-supply: > +- vdd_l18-supply: > +- vdd_l19-supply: > +- vdd_l21-supply: > +- vdd_l22-supply: > +- vdd_l16_l25-supply: > +- vdd_l27-supply: > +- vdd_l28-supply: > +- vdd_l29-supply: > +- vdd_l30-supply: > +- vdd_l31-supply: > +- vdd_l32-supply: > + Usage: optional (pm8994 only) > + Value type: <phandle> > + Definition: reference to regulator supplying the input pin, as > + described in the data sheet. > + > + > The regulator node houses sub-nodes for each regulator within the device. Each > sub-node is identified using the node's name, with valid values listed for each > of the pmics below. > @@ -118,6 +153,11 @@ pma8084: > l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, > l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1 > > +pm8994: > + s1, s2, s3, s4, s5, s6, s7, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, > + l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, > + l27, l28, l29, l30, l31, l32, lvs1, lvs2 > + > The content of each sub-node is defined by the standard binding for regulators - > see regulator.txt. > > diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts > index 4542133..2ce8798 100644 > --- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts > +++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts > @@ -39,3 +39,265 @@ > }; > }; > }; > + > +&smd_rpm { > + rpm { > + rpm_requests { > + pm8994-regulators { > + > + vdd_l1-supply = <&pm8994_s1>; > + vdd_l2_26_28-supply = <&pm8994_s3>; > + vdd_l3_11-supply = <&pm8994_s3>; > + vdd_l4_27_31-supply = <&pm8994_s3>; > + vdd_l5_7-supply = <&pm8994_s3>; > + vdd_l6_12_32-supply = <&pm8994_s5>; > + vdd_l8_16_30-supply = <&vreg_vph_pwr>; > + vdd_l9_10_18_22-supply = <&vreg_vph_pwr>; > + vdd_l13_19_23_24-supply = <&vreg_vph_pwr>; > + vdd_l14_15-supply = <&pm8994_s5>; > + vdd_l17_29-supply = <&vreg_vph_pwr>; > + vdd_l20_21-supply = <&vreg_vph_pwr>; > + vdd_l25-supply = <&pm8994_s5>; > + /*vin_lvs1_2 = <&pm8994_s4>; */ > + > + s1 { > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <800000>; > + }; > + > + s2 { > + }; > + > + s3 { > + regulator-min-microvolt = <1300000>; > + regulator-max-microvolt = <1300000>; > + }; > + > + s4 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-allow-set-load; > + regulator-system-load = <325000>; > + }; > + > + s5 { > + regulator-min-microvolt = <2150000>; > + regulator-max-microvolt = <2150000>; > + }; > + > + s7 { > + regulator-min-microvolt = <1000000>; > + regulator-max-microvolt = <1000000>; > + }; > + > + l1 { > + regulator-min-microvolt = <1000000>; > + regulator-max-microvolt = <1000000>; > + }; > + > + l2 { > + regulator-min-microvolt = <1250000>; > + regulator-max-microvolt = <1250000>; > + }; > + > + l3 { > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + }; > + > + l4 { > + regulator-min-microvolt = <1225000>; > + regulator-max-microvolt = <1225000>; > + }; > + > + l5 { > + }; > + > + l6 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + }; > + > + l7 { > + }; > + > + l8 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + }; > + > + l9 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + }; > + > + l10 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + qcom,init-voltage = <1800000>; > + }; > + > + l11 { > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + qcom,init-voltage = <1200000>; > + }; > + > + l12 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + qcom,init-voltage = <1800000>; > + proxy-supply = <&pm8994_l12>; > + qcom,proxy-consumer-enable; > + qcom,proxy-consumer-current = <10000>; > + status = "okay"; > + }; > + > + l13 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <2950000>; > + qcom,init-voltage = <2950000>; > + status = "okay"; > + }; > + > + l14 { > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + qcom,init-voltage = <1200000>; > + proxy-supply = <&pm8994_l14>; > + qcom,proxy-consumer-enable; > + qcom,proxy-consumer-current = <10000>; > + status = "okay"; > + }; > + > + l15 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + qcom,init-voltage = <1800000>; > + status = "okay"; > + }; > + > + l16 { > + regulator-min-microvolt = <2700000>; > + regulator-max-microvolt = <2700000>; > + qcom,init-voltage = <2700000>; > + status = "okay"; > + }; > + > + l17 { > + regulator-min-microvolt = <2700000>; > + regulator-max-microvolt = <2700000>; > + qcom,init-voltage = <2700000>; > + status = "okay"; > + }; > + > + l18 { > + regulator-min-microvolt = <3000000>; > + regulator-max-microvolt = <3000000>; > + regulator-always-on; > + qcom,init-voltage = <3000000>; > + qcom,init-ldo-mode = <1>; > + }; > + > + l19 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + qcom,init-voltage = <1800000>; > + status = "okay"; > + }; > + > + l20 { > + regulator-min-microvolt = <2950000>; > + regulator-max-microvolt = <2950000>; > + regulator-always-on; > + regulator-boot-on; > + regulator-allow-set-load; > + regulator-system-load = <570000>; > + }; > + > + l21 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-always-on; > + qcom,init-voltage = <1800000>; > + }; > + > + l22 { > + regulator-min-microvolt = <3100000>; > + regulator-max-microvolt = <3100000>; > + qcom,init-voltage = <3100000>; > + }; > + > + l23 { > + regulator-min-microvolt = <2800000>; > + regulator-max-microvolt = <2800000>; > + qcom,init-voltage = <2800000>; > + }; > + > + l24 { > + regulator-min-microvolt = <3075000>; > + regulator-max-microvolt = <3150000>; > + qcom,init-voltage = <3075000>; > + }; > + > + l25 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + qcom,init-voltage = <1800000>; > + }; > + > + l26 { > + /* TODO: value from downstream > + regulator-min-microvolt = <987500>; > + fails to apply */ > + }; > + > + l27 { > + regulator-min-microvolt = <1050000>; > + regulator-max-microvolt = <1050000>; > + qcom,init-voltage = <1050000>; > + }; > + > + l28 { > + regulator-min-microvolt = <1000000>; > + regulator-max-microvolt = <1000000>; > + qcom,init-voltage = <1000000>; > + proxy-supply = <&pm8994_l28>; > + qcom,proxy-consumer-enable; > + qcom,proxy-consumer-current = <10000>; > + }; > + > + l29 { > + /* TODO: Unsupported voltage range.. > + regulator-min-microvolt = <2800000>; > + regulator-max-microvolt = <2800000>; > + qcom,init-voltage = <2800000>; > + */ > + }; > + > + l30 { > + /* TODO: get this verified > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + qcom,init-voltage = <1800000>; > + */ > + }; > + > + l31 { > + regulator-min-microvolt = <1262500>; > + regulator-max-microvolt = <1262500>; > + qcom,init-voltage = <1262500>; > + }; > + > + l32 { > + /* TODO: get this verified > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + qcom,init-voltage = <1800000>; > + */ > + }; > + > + }; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi > index d2a26f0..15202c8 100644 > --- a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi > @@ -35,4 +35,86 @@ > bias-pull-down; > }; > }; > + > + /* 0-3 for sdc1 4-6 for sdc2 */ > + /* Order of pins */ > + /* SDC1: CLK -> 0, CMD -> 1, DATA -> 2, RCLK -> 3 */ > + /* SDC2: CLK -> 4, CMD -> 5, DATA -> 6 */ > + pmx_sdc1_clk { > + sdc1_clk_on: clk_on { Use '-' rather than '_' for node names. (Labels don't matter) > + pinmux { > + pins = "sdc1_clk"; > + }; > + pinconf { > + pins = "sdc1_clk"; > + bias-disable = <0>; /* No pull */ > + drive-strength = <16>; /* 16mA */ > + }; > + }; > + sdc1_clk_off: clk_off { > + pinmux { > + pins = "sdc1_clk"; > + }; > + pinconf { > + pins = "sdc1_clk"; > + bias-disable = <0>; /* No pull */ > + drive-strength = <2>; /* 2mA */ > + }; > + }; > + }; > + > + pmx_sdc1_cmd { > + sdc1_cmd_on: cmd_on { > + pinmux { > + pins = "sdc1_cmd"; > + }; > + pinconf { > + pins = "sdc1_cmd"; > + bias-pull-up; > + drive-strength = <8>; > + }; > + }; > + sdc1_cmd_off: cmd_off { > + pinmux { > + pins = "sdc1_cmd"; > + }; > + pinconf { > + pins = "sdc1_cmd"; > + bias-pull-up = <0x3>; /* same as 3.10 ?? */ > + drive-strength = <2>; /* 2mA */ > + }; > + }; > + }; > + > + pmx_sdc1_data { > + sdc1_data_on: data_on { > + pinmux { > + pins = "sdc1_data"; > + }; > + pinconf { > + pins = "sdc1_data"; > + bias-pull-up; > + drive-strength = <8>; /* 8mA */ > + }; > + }; > + sdc1_data_off: data_off { > + pinmux { > + pins = "sdc1_data"; > + }; > + pinconf { > + pins = "sdc1_data"; > + bias-pull-up; > + drive-strength = <2>; > + }; > + }; > + }; > + > + pmx_sdc1_rclk { > + sdc1_rclk_on: rclk_on { > + bias-pull-down; /* pull down */ > + }; > + sdc1_rclk_off: rclk_off { > + bias-pull-down; /* pull down */ > + }; > + }; > }; > diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi > index 44b2d37..d104770 100644 > --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi > @@ -82,6 +82,12 @@ > <0xf9002000 0x1000>; > }; > > + apcs: syscon@0xf900d000 { Drop the '0x'. > + compatible = "syscon"; > + reg = <0xf900d000 0x2000>; > + }; > + > + > timer@f9020000 { > #address-cells = <1>; > #size-cells = <1>; > @@ -172,12 +178,159 @@ > #power-domain-cells = <1>; > reg = <0xfc400000 0x2000>; > }; > + > + sdhci1: qcom,sdhci@f9824900 { mmc@... > + compatible = "qcom,sdhci-msm-v4"; > + reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; > + reg-names = "hc_mem", "core_mem"; > + > + interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>, > + <GIC_SPI 138 IRQ_TYPE_NONE>; > + interrupt-names = "hc_irq", "pwr_irq"; > + > + clocks = <&clock_gcc GCC_SDCC1_APPS_CLK>, > + <&clock_gcc GCC_SDCC1_AHB_CLK>; > + clock-names = "core", "iface"; > + > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on > + &sdc1_rclk_on>; > + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off > + &sdc1_rclk_off>; > + > + vdd-supply = <&pm8994_l20>; > + qcom,vdd-voltage-level = <2950000 2950000>; > + qcom,vdd-current-level = <200 570000>; > + > + vdd-io-supply = <&pm8994_s4>; > + qcom,vdd-io-voltage-level = <1800000 1800000>; > + qcom,vdd-io-current-level = <200 325000>; > + > + regulator-always-on; > + bus-width = <8>; > + mmc-hs400-1_8v; > + status = "okay"; > + }; > + > + vreg_vph_pwr: vreg-vph-pwr { > + compatible = "regulator-fixed"; > + status = "okay"; > + regulator-name = "vph-pwr"; > + > + regulator-min-microvolt = <3600000>; > + regulator-max-microvolt = <3600000>; > + > + regulator-always-on; > + }; > + > + rpm_msg_ram: memory@fc428000 { > + compatible = "qcom,rpm-msg-ram"; > + reg = <0xfc428000 0x4000>; > + }; > + > + sfpb_mutex_regs: syscon@fd484000 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "syscon"; > + reg = <0xfd484000 0x400>; > + }; > + > + sfpb_mutex: hwmutex { > + compatible = "qcom,sfpb-mutex"; > + syscon = <&sfpb_mutex_regs 0x0 0x100>; > + #hwlock-cells = <1>; > + }; > + > + smem { > + compatible = "qcom,smem"; > + memory-region = <&smem_region>; > + qcom,rpm-msg-ram = <&rpm_msg_ram>; > + hwlocks = <&sfpb_mutex 3>; > + }; > }; > > memory { > device_type = "memory"; > reg = <0 0 0 0>; // bootloader will update > }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + smem_region: smem@6a00000 { > + reg = <0x0 0x6a00000 0x0 0x200000>; > + no-map; > + }; > + }; > + > + smd_rpm: smd { > + compatible = "qcom,smd"; > + > + rpm { > + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; > + qcom,ipc = <&apcs 8 0>; > + qcom,smd-edge = <15>; > + qcom,local-pid = <0>; > + qcom,remote-pid = <6>; > + > + rpm_requests { > + compatible = "qcom,rpm-msm8994"; > + qcom,smd-channels = "rpm_requests"; > + > + rpmcc: qcom,rpmcc { > + /* TODO: update when rpmcc-msm8994 support added */ > + compatible = "qcom,rpmcc-msm8916", > + "qcom,rpmcc"; > + #clock-cells = <1>; > + }; > + > + smd_rpm_regulators: pm8994-regulators { > + compatible = "qcom,rpm-pm8994-regulators"; > + > + pm8994_s1: s1 {}; > + pm8994_s2: s2 {}; > + pm8994_s3: s3 {}; > + pm8994_s4: s4 {}; > + pm8994_s5: s5 {}; > + pm8994_s6: s6 {}; > + pm8994_s7: s7 {}; > + > + pm8994_l1: l1 {}; > + pm8994_l2: l2 {}; > + pm8994_l3: l3 {}; > + pm8994_l4: l4 {}; > + pm8994_l6: l6 {}; > + pm8994_l8: l8 {}; > + pm8994_l9: l9 {}; > + pm8994_l10: l10 {}; > + pm8994_l11: l11 {}; > + pm8994_l12: l12 {}; > + pm8994_l13: l13 {}; > + pm8994_l14: l14 {}; > + pm8994_l15: l15 {}; > + pm8994_l16: l16 {}; > + pm8994_l17: l17 {}; > + pm8994_l18: l18 {}; > + pm8994_l19: l19 {}; > + pm8994_l20: l20 {}; > + pm8994_l21: l21 {}; > + pm8994_l22: l22 {}; > + pm8994_l23: l23 {}; > + pm8994_l24: l24 {}; > + pm8994_l25: l25 {}; > + pm8994_l26: l26 {}; > + pm8994_l27: l27 {}; > + pm8994_l28: l28 {}; > + pm8994_l29: l29 {}; > + pm8994_l30: l30 {}; > + pm8994_l31: l31 {}; > + pm8994_l32: l32 {}; > + }; > + }; > + }; > + }; > }; > > > diff --git a/drivers/regulator/qcom_smd-regulator.c b/drivers/regulator/qcom_smd-regulator.c > index 8ed46a9..a7e8ce7 100644 > --- a/drivers/regulator/qcom_smd-regulator.c > +++ b/drivers/regulator/qcom_smd-regulator.c > @@ -443,11 +443,60 @@ static const struct rpm_regulator_data rpm_pma8084_regulators[] = { > {} > }; > > +static const struct rpm_regulator_data rpm_pm8994_regulators[] = { > + { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" }, > + { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" }, > + { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" }, > + { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" }, > + { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" }, > + { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" }, > + { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" }, > + > + { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" }, > + { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, > + { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, > + { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" }, > + { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" }, > + { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, > + { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" }, > + { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" }, > + { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, > + { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, > + { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" }, > + { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, > + { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, > + { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, > + { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, > + { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" }, > + { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" }, > + { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" }, > + { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" }, > + { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, > + { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" }, > + { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" }, > + { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, > + { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" }, > + { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" }, > + { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" }, > + { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l27" }, > + { "l28", QCOM_SMD_RPM_LDOA, 28, &pma8084_nldo, "vdd_l28" }, > + { "l29", QCOM_SMD_RPM_LDOA, 29, &pma8084_nldo, "vdd_l29" }, > + { "l30", QCOM_SMD_RPM_LDOA, 30, &pma8084_nldo, "vdd_l30" }, > + { "l31", QCOM_SMD_RPM_LDOA, 31, &pma8084_nldo, "vdd_l31" }, > + { "l32", QCOM_SMD_RPM_LDOA, 32, &pma8084_nldo, "vdd_l32" }, > + > + { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch }, > + { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch }, > + > + {} > +}; > + > static const struct of_device_id rpm_of_match[] = { > { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators }, > { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators }, > { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators }, > { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators }, > + { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators }, > {} > }; > MODULE_DEVICE_TABLE(of, rpm_of_match); > -- > 2.6.1 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 4/5] sdhci: dump vendor state and regs 2016-11-23 1:09 [PATCH 0/5] Enable onboard SDHCI for Nexus 5X (msm8992) Jeremy McNicoll ` (2 preceding siblings ...) 2016-11-23 1:09 ` [PATCH 3/5] arm64: dts: Enable SDHCI for Nexus 5X (msm8992) Jeremy McNicoll @ 2016-11-23 1:09 ` Jeremy McNicoll 2016-11-23 1:09 ` [PATCH 5/5] sdhci: Add quirk for delayed IRQ ACK Jeremy McNicoll 4 siblings, 0 replies; 13+ messages in thread From: Jeremy McNicoll @ 2016-11-23 1:09 UTC (permalink / raw) To: linux-arm-msm, linux-soc, devicetree, linux-mmc Cc: andy.gross, sboyd, robh, arnd, bjorn.andersson, riteshh, jeremymc This has proven very useful in debugging SDHCI RPM interaction issues. Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> --- drivers/mmc/host/sdhci-msm.c | 79 ++++++++++++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci.c | 25 ++++++++++++++ drivers/mmc/host/sdhci.h | 1 + 3 files changed, 105 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index ee01d95..1fcda96 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -678,6 +678,84 @@ static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) return ret; } + + +#define MAX_TEST_BUS 20 +#define CORE_MCI_DATA_CNT 0x30 +#define CORE_MCI_FIFO_CNT 0x44 +#define CORE_MCI_STATUS 0x34 +#define CORE_VENDOR_SPEC_ADMA_ERR_ADDR0 0x114 +#define CORE_VENDOR_SPEC_ADMA_ERR_ADDR1 0x118 +#define CORE_TESTBUS_SEL2_BIT 4 +#define CORE_TESTBUS_SEL2 (1 << CORE_TESTBUS_SEL2_BIT) + +#define CORE_TESTBUS_ENA (1 << 3) + +#define CORE_TESTBUS_CONFIG 0x0CC + +#define CORE_SDCC_DEBUG_REG 0x124 + +void sdhci_msm_dump_vendor_regs(struct sdhci_host *host) +{ + + int tbsel, tbsel2; + int i, index = 0; + u32 test_bus_val = 0; + u32 debug_reg[MAX_TEST_BUS] = {0}; + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_msm_host *msm_host; + + pltfm_host = sdhci_priv(host); + msm_host = sdhci_pltfm_priv(pltfm_host); + + pr_info("----------- VENDOR REGISTER DUMP -----------\n"); + pr_info("Data cnt: 0x%08x | Fifo cnt: 0x%08x | Int sts: 0x%08x\n", + readl_relaxed(msm_host->core_mem + CORE_MCI_DATA_CNT), + readl_relaxed(msm_host->core_mem + CORE_MCI_FIFO_CNT), + readl_relaxed(msm_host->core_mem + CORE_MCI_STATUS)); + pr_info("DLL cfg: 0x%08x | DLL sts: 0x%08x | SDCC ver: 0x%08x\n", + readl_relaxed(host->ioaddr + CORE_DLL_CONFIG), + readl_relaxed(host->ioaddr + CORE_DLL_STATUS), + readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION)); + pr_info("Vndr func: 0x%08x | Vndr adma err : addr0: 0x%08x addr1: 0x%08x\n", + readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC), + readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR0), + readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR1)); + + /* + * tbsel indicates [2:0] bits and tbsel2 indicates [7:4] bits + * of CORE_TESTBUS_CONFIG register. + * + * To select test bus 0 to 7 use tbsel and to select any test bus + * above 7 use (tbsel2 | tbsel) to get the test bus number. For eg, + * to select test bus 14, write 0x1E to CORE_TESTBUS_CONFIG register + * i.e., tbsel2[7:4] = 0001, tbsel[2:0] = 110. + */ + for (tbsel2 = 0; tbsel2 < 3; tbsel2++) { + for (tbsel = 0; tbsel < 8; tbsel++) { + if (index >= MAX_TEST_BUS) + break; + test_bus_val = (tbsel2 << CORE_TESTBUS_SEL2_BIT) | + tbsel | CORE_TESTBUS_ENA; + writel_relaxed(test_bus_val, + msm_host->core_mem + CORE_TESTBUS_CONFIG); + debug_reg[index++] = readl_relaxed(msm_host->core_mem + + CORE_SDCC_DEBUG_REG); + } + } + + for (i = 0; i < MAX_TEST_BUS; i = i + 4) + pr_info(" Test bus[%d to %d]: 0x%08x 0x%08x 0x%08x 0x%08x\n", + i, i + 3, debug_reg[i], debug_reg[i+1], + debug_reg[i+2], debug_reg[i+3]); + /* Disable test bus */ + writel_relaxed(~CORE_TESTBUS_ENA, msm_host->core_mem + + CORE_TESTBUS_CONFIG); +} + + + + static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) { int tuning_seq_cnt = 3; @@ -1081,6 +1159,7 @@ static const struct sdhci_ops sdhci_msm_ops = { .set_bus_width = sdhci_set_bus_width, .set_uhs_signaling = sdhci_msm_set_uhs_signaling, .voltage_switch = sdhci_msm_voltage_switch, + .dump_vendor_regs = sdhci_msm_dump_vendor_regs, }; static const struct sdhci_pltfm_data sdhci_msm_pdata = { diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 71654b9..5911f98 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -47,6 +47,27 @@ static void sdhci_finish_data(struct sdhci_host *); static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); +static void sdhci_dump_rpm_info(struct sdhci_host *host) +{ + struct mmc_host *mmc = host->mmc; + + pr_info("%s: rpmstatus[pltfm](runtime-suspend:usage_count:disable_depth)(%d:%d:%d)\n", + mmc_hostname(mmc), mmc->parent->power.runtime_status, + atomic_read(&mmc->parent->power.usage_count), + mmc->parent->power.disable_depth); +} + + +static void sdhci_dump_state(struct sdhci_host *host) +{ + struct mmc_host *mmc = host->mmc; + + pr_info("%s: clk: %d claimer: %s pwr: %d\n", + mmc_hostname(mmc), host->clock, + mmc->claimer->comm, host->pwr); + sdhci_dump_rpm_info(host); +} + static void sdhci_dumpregs(struct sdhci_host *host) { pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", @@ -100,6 +121,10 @@ static void sdhci_dumpregs(struct sdhci_host *host) readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); } + if (host->ops->dump_vendor_regs) + host->ops->dump_vendor_regs(host); + + sdhci_dump_state(host); pr_err(DRIVER_NAME ": ===========================================\n"); } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 766df17..c055e24 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -563,6 +563,7 @@ struct sdhci_ops { struct mmc_card *card, unsigned int max_dtr, int host_drv, int card_drv, int *drv_type); + void (*dump_vendor_regs)(struct sdhci_host *host); }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS -- 2.6.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/5] sdhci: Add quirk for delayed IRQ ACK 2016-11-23 1:09 [PATCH 0/5] Enable onboard SDHCI for Nexus 5X (msm8992) Jeremy McNicoll ` (3 preceding siblings ...) 2016-11-23 1:09 ` [PATCH 4/5] sdhci: dump vendor state and regs Jeremy McNicoll @ 2016-11-23 1:09 ` Jeremy McNicoll 2016-11-23 3:36 ` Jisheng Zhang 4 siblings, 1 reply; 13+ messages in thread From: Jeremy McNicoll @ 2016-11-23 1:09 UTC (permalink / raw) To: linux-arm-msm, linux-soc, devicetree, linux-mmc Cc: andy.gross, sboyd, robh, arnd, bjorn.andersson, riteshh, jeremymc On msm8992 it has been observed that IRQs were not getting ACK'd correctly when clocked at speeds greater than 400KHz. Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> --- drivers/mmc/host/sdhci-msm.c | 7 +++++++ drivers/mmc/host/sdhci.c | 12 ++++++++++-- drivers/mmc/host/sdhci.h | 2 ++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 1fcda96..459003c 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1303,6 +1303,13 @@ static int sdhci_msm_probe(struct platform_device *pdev) CORE_VENDOR_SPEC_CAPABILITIES0); } + /* Enable delayed IRQ handling workaround on 8992 */ + if (core_major == 1 && core_minor == 0x3e) { + /* Add 40us delay in interrupt handler when operating + * at initialization frequency of 400KHz. */ + host->quirks2 |= SDHCI_QUIRK2_SLOW_INT_CLR; + } + /* Setup IRQ for handling power/voltage tasks with PMIC */ msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); if (msm_host->pwr_irq < 0) { diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 5911f98..c1aae22 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2703,11 +2703,19 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id) result = IRQ_WAKE_THREAD; } - if (intmask & SDHCI_INT_CMD_MASK) + if (intmask & SDHCI_INT_CMD_MASK) { + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && (host->clock <= 400000)) { + udelay(40); + } sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); + } - if (intmask & SDHCI_INT_DATA_MASK) + if (intmask & SDHCI_INT_DATA_MASK) { + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && (host->clock <= 400000)) { + udelay(40); + } sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); + } if (intmask & SDHCI_INT_BUS_POWER) pr_err("%s: Card is consuming too much power!\n", diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c055e24..5f8301e 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -24,6 +24,8 @@ * Controller registers */ +#define SDHCI_QUIRK2_SLOW_INT_CLR (1<<5) + #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS -- 2.6.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 5/5] sdhci: Add quirk for delayed IRQ ACK 2016-11-23 1:09 ` [PATCH 5/5] sdhci: Add quirk for delayed IRQ ACK Jeremy McNicoll @ 2016-11-23 3:36 ` Jisheng Zhang 2016-11-23 3:48 ` Jeremy McNicoll 0 siblings, 1 reply; 13+ messages in thread From: Jisheng Zhang @ 2016-11-23 3:36 UTC (permalink / raw) To: Jeremy McNicoll Cc: linux-arm-msm, linux-soc, devicetree, linux-mmc, andy.gross, sboyd, robh, arnd, bjorn.andersson, riteshh On Tue, 22 Nov 2016 17:09:48 -0800 Jeremy McNicoll <jeremymc@redhat.com> wrote: > On msm8992 it has been observed that IRQs were not getting > ACK'd correctly when clocked at speeds greater than 400KHz. > > Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> > --- > drivers/mmc/host/sdhci-msm.c | 7 +++++++ > drivers/mmc/host/sdhci.c | 12 ++++++++++-- > drivers/mmc/host/sdhci.h | 2 ++ > 3 files changed, 19 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c > index 1fcda96..459003c 100644 > --- a/drivers/mmc/host/sdhci-msm.c > +++ b/drivers/mmc/host/sdhci-msm.c > @@ -1303,6 +1303,13 @@ static int sdhci_msm_probe(struct platform_device *pdev) > CORE_VENDOR_SPEC_CAPABILITIES0); > } > > + /* Enable delayed IRQ handling workaround on 8992 */ > + if (core_major == 1 && core_minor == 0x3e) { > + /* Add 40us delay in interrupt handler when operating > + * at initialization frequency of 400KHz. */ > + host->quirks2 |= SDHCI_QUIRK2_SLOW_INT_CLR; > + } > + > /* Setup IRQ for handling power/voltage tasks with PMIC */ > msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); > if (msm_host->pwr_irq < 0) { > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c > index 5911f98..c1aae22 100644 > --- a/drivers/mmc/host/sdhci.c > +++ b/drivers/mmc/host/sdhci.c > @@ -2703,11 +2703,19 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id) > result = IRQ_WAKE_THREAD; > } > > - if (intmask & SDHCI_INT_CMD_MASK) > + if (intmask & SDHCI_INT_CMD_MASK) { > + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && (host->clock <= 400000)) { > + udelay(40); > + } > sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); > + } > > - if (intmask & SDHCI_INT_DATA_MASK) > + if (intmask & SDHCI_INT_DATA_MASK) { > + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && (host->clock <= 400000)) { > + udelay(40); > + } > sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); > + } > > if (intmask & SDHCI_INT_BUS_POWER) > pr_err("%s: Card is consuming too much power!\n", > diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h > index c055e24..5f8301e 100644 > --- a/drivers/mmc/host/sdhci.h > +++ b/drivers/mmc/host/sdhci.h > @@ -24,6 +24,8 @@ > * Controller registers > */ > > +#define SDHCI_QUIRK2_SLOW_INT_CLR (1<<5) IIRC, new quirk isn't allowed now. Thanks, Jisheng ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 5/5] sdhci: Add quirk for delayed IRQ ACK 2016-11-23 3:36 ` Jisheng Zhang @ 2016-11-23 3:48 ` Jeremy McNicoll [not found] ` <ecacec51-4b06-49cd-c756-489128729499-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> 0 siblings, 1 reply; 13+ messages in thread From: Jeremy McNicoll @ 2016-11-23 3:48 UTC (permalink / raw) To: Jisheng Zhang, Jeremy McNicoll Cc: linux-arm-msm, linux-soc, devicetree, linux-mmc, andy.gross, sboyd, robh, arnd, bjorn.andersson, riteshh On 2016-11-22 7:36 PM, Jisheng Zhang wrote: > On Tue, 22 Nov 2016 17:09:48 -0800 > Jeremy McNicoll <jeremymc@redhat.com> wrote: > >> On msm8992 it has been observed that IRQs were not getting >> ACK'd correctly when clocked at speeds greater than 400KHz. >> >> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> >> --- >> drivers/mmc/host/sdhci-msm.c | 7 +++++++ >> drivers/mmc/host/sdhci.c | 12 ++++++++++-- >> drivers/mmc/host/sdhci.h | 2 ++ >> 3 files changed, 19 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c >> index 1fcda96..459003c 100644 >> --- a/drivers/mmc/host/sdhci-msm.c >> +++ b/drivers/mmc/host/sdhci-msm.c >> @@ -1303,6 +1303,13 @@ static int sdhci_msm_probe(struct platform_device *pdev) >> CORE_VENDOR_SPEC_CAPABILITIES0); >> } >> >> + /* Enable delayed IRQ handling workaround on 8992 */ >> + if (core_major == 1 && core_minor == 0x3e) { >> + /* Add 40us delay in interrupt handler when operating >> + * at initialization frequency of 400KHz. */ >> + host->quirks2 |= SDHCI_QUIRK2_SLOW_INT_CLR; >> + } >> + >> /* Setup IRQ for handling power/voltage tasks with PMIC */ >> msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); >> if (msm_host->pwr_irq < 0) { >> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c >> index 5911f98..c1aae22 100644 >> --- a/drivers/mmc/host/sdhci.c >> +++ b/drivers/mmc/host/sdhci.c >> @@ -2703,11 +2703,19 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id) >> result = IRQ_WAKE_THREAD; >> } >> >> - if (intmask & SDHCI_INT_CMD_MASK) >> + if (intmask & SDHCI_INT_CMD_MASK) { >> + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && (host->clock <= 400000)) { >> + udelay(40); >> + } >> sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); >> + } >> >> - if (intmask & SDHCI_INT_DATA_MASK) >> + if (intmask & SDHCI_INT_DATA_MASK) { >> + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && (host->clock <= 400000)) { >> + udelay(40); >> + } >> sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); >> + } >> >> if (intmask & SDHCI_INT_BUS_POWER) >> pr_err("%s: Card is consuming too much power!\n", >> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h >> index c055e24..5f8301e 100644 >> --- a/drivers/mmc/host/sdhci.h >> +++ b/drivers/mmc/host/sdhci.h >> @@ -24,6 +24,8 @@ >> * Controller registers >> */ >> >> +#define SDHCI_QUIRK2_SLOW_INT_CLR (1<<5) > > IIRC, new quirk isn't allowed now. > Why not? -jeremy > Thanks, > Jisheng > > -- > To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > ^ permalink raw reply [flat|nested] 13+ messages in thread
[parent not found: <ecacec51-4b06-49cd-c756-489128729499-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH 5/5] sdhci: Add quirk for delayed IRQ ACK [not found] ` <ecacec51-4b06-49cd-c756-489128729499-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> @ 2016-11-23 4:12 ` Jisheng Zhang 2016-11-23 5:23 ` Jeremy McNicoll 0 siblings, 1 reply; 13+ messages in thread From: Jisheng Zhang @ 2016-11-23 4:12 UTC (permalink / raw) To: Jeremy McNicoll Cc: Jeremy McNicoll, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, linux-soc-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-mmc-u79uwXL29TY76Z2rM5mHXA, andy.gross-QSEj5FYQhm4dnm+yROfE0A, sboyd-sgV2jX0FEOL9JmXXK+q4OQ, robh-DgEjT+Ai2ygdnm+yROfE0A, arnd-r2nGTMty4D4, bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A, riteshh-sgV2jX0FEOL9JmXXK+q4OQ On Tue, 22 Nov 2016 19:48:56 -0800 Jeremy McNicoll wrote: > On 2016-11-22 7:36 PM, Jisheng Zhang wrote: > > On Tue, 22 Nov 2016 17:09:48 -0800 > > Jeremy McNicoll <jeremymc-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote: > > > >> On msm8992 it has been observed that IRQs were not getting > >> ACK'd correctly when clocked at speeds greater than 400KHz. > >> > >> Signed-off-by: Jeremy McNicoll <jeremymc-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> > >> --- > >> drivers/mmc/host/sdhci-msm.c | 7 +++++++ > >> drivers/mmc/host/sdhci.c | 12 ++++++++++-- > >> drivers/mmc/host/sdhci.h | 2 ++ > >> 3 files changed, 19 insertions(+), 2 deletions(-) > >> > >> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c > >> index 1fcda96..459003c 100644 > >> --- a/drivers/mmc/host/sdhci-msm.c > >> +++ b/drivers/mmc/host/sdhci-msm.c > >> @@ -1303,6 +1303,13 @@ static int sdhci_msm_probe(struct platform_device *pdev) > >> CORE_VENDOR_SPEC_CAPABILITIES0); > >> } > >> > >> + /* Enable delayed IRQ handling workaround on 8992 */ > >> + if (core_major == 1 && core_minor == 0x3e) { > >> + /* Add 40us delay in interrupt handler when operating > >> + * at initialization frequency of 400KHz. */ > >> + host->quirks2 |= SDHCI_QUIRK2_SLOW_INT_CLR; > >> + } > >> + > >> /* Setup IRQ for handling power/voltage tasks with PMIC */ > >> msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); > >> if (msm_host->pwr_irq < 0) { > >> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c > >> index 5911f98..c1aae22 100644 > >> --- a/drivers/mmc/host/sdhci.c > >> +++ b/drivers/mmc/host/sdhci.c > >> @@ -2703,11 +2703,19 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id) > >> result = IRQ_WAKE_THREAD; > >> } > >> > >> - if (intmask & SDHCI_INT_CMD_MASK) > >> + if (intmask & SDHCI_INT_CMD_MASK) { > >> + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && (host->clock <= 400000)) { > >> + udelay(40); > >> + } > >> sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); > >> + } > >> > >> - if (intmask & SDHCI_INT_DATA_MASK) > >> + if (intmask & SDHCI_INT_DATA_MASK) { > >> + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && (host->clock <= 400000)) { > >> + udelay(40); > >> + } > >> sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); > >> + } > >> > >> if (intmask & SDHCI_INT_BUS_POWER) > >> pr_err("%s: Card is consuming too much power!\n", > >> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h > >> index c055e24..5f8301e 100644 > >> --- a/drivers/mmc/host/sdhci.h > >> +++ b/drivers/mmc/host/sdhci.h > >> @@ -24,6 +24,8 @@ > >> * Controller registers > >> */ > >> > >> +#define SDHCI_QUIRK2_SLOW_INT_CLR (1<<5) > > > > IIRC, new quirk isn't allowed now. > > > > Why not? IIRC, mmc subsystem will behave as a lib in the long run, so the community and developers call for no new quirk. For your case, we may need to handle the udelay in sdhci-msm.c, export sdhci_irq as a helper function? Thanks -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 5/5] sdhci: Add quirk for delayed IRQ ACK 2016-11-23 4:12 ` Jisheng Zhang @ 2016-11-23 5:23 ` Jeremy McNicoll 0 siblings, 0 replies; 13+ messages in thread From: Jeremy McNicoll @ 2016-11-23 5:23 UTC (permalink / raw) To: Jisheng Zhang Cc: Jeremy McNicoll, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, linux-soc-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-mmc-u79uwXL29TY76Z2rM5mHXA, andy.gross-QSEj5FYQhm4dnm+yROfE0A, sboyd-sgV2jX0FEOL9JmXXK+q4OQ, robh-DgEjT+Ai2ygdnm+yROfE0A, arnd-r2nGTMty4D4, bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A, riteshh-sgV2jX0FEOL9JmXXK+q4OQ On 2016-11-22 8:12 PM, Jisheng Zhang wrote: > On Tue, 22 Nov 2016 19:48:56 -0800 Jeremy McNicoll wrote: > >> On 2016-11-22 7:36 PM, Jisheng Zhang wrote: >>> On Tue, 22 Nov 2016 17:09:48 -0800 >>> Jeremy McNicoll <jeremymc-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote: >>> >>>> On msm8992 it has been observed that IRQs were not getting >>>> ACK'd correctly when clocked at speeds greater than 400KHz. >>>> >>>> Signed-off-by: Jeremy McNicoll <jeremymc-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> >>>> --- >>>> drivers/mmc/host/sdhci-msm.c | 7 +++++++ >>>> drivers/mmc/host/sdhci.c | 12 ++++++++++-- >>>> drivers/mmc/host/sdhci.h | 2 ++ >>>> 3 files changed, 19 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c >>>> index 1fcda96..459003c 100644 >>>> --- a/drivers/mmc/host/sdhci-msm.c >>>> +++ b/drivers/mmc/host/sdhci-msm.c >>>> @@ -1303,6 +1303,13 @@ static int sdhci_msm_probe(struct platform_device *pdev) >>>> CORE_VENDOR_SPEC_CAPABILITIES0); >>>> } >>>> >>>> + /* Enable delayed IRQ handling workaround on 8992 */ >>>> + if (core_major == 1 && core_minor == 0x3e) { >>>> + /* Add 40us delay in interrupt handler when operating >>>> + * at initialization frequency of 400KHz. */ >>>> + host->quirks2 |= SDHCI_QUIRK2_SLOW_INT_CLR; >>>> + } >>>> + >>>> /* Setup IRQ for handling power/voltage tasks with PMIC */ >>>> msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); >>>> if (msm_host->pwr_irq < 0) { >>>> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c >>>> index 5911f98..c1aae22 100644 >>>> --- a/drivers/mmc/host/sdhci.c >>>> +++ b/drivers/mmc/host/sdhci.c >>>> @@ -2703,11 +2703,19 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id) >>>> result = IRQ_WAKE_THREAD; >>>> } >>>> >>>> - if (intmask & SDHCI_INT_CMD_MASK) >>>> + if (intmask & SDHCI_INT_CMD_MASK) { >>>> + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && (host->clock <= 400000)) { >>>> + udelay(40); >>>> + } >>>> sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); >>>> + } >>>> >>>> - if (intmask & SDHCI_INT_DATA_MASK) >>>> + if (intmask & SDHCI_INT_DATA_MASK) { >>>> + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && (host->clock <= 400000)) { >>>> + udelay(40); >>>> + } >>>> sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); >>>> + } >>>> >>>> if (intmask & SDHCI_INT_BUS_POWER) >>>> pr_err("%s: Card is consuming too much power!\n", >>>> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h >>>> index c055e24..5f8301e 100644 >>>> --- a/drivers/mmc/host/sdhci.h >>>> +++ b/drivers/mmc/host/sdhci.h >>>> @@ -24,6 +24,8 @@ >>>> * Controller registers >>>> */ >>>> >>>> +#define SDHCI_QUIRK2_SLOW_INT_CLR (1<<5) >>> >>> IIRC, new quirk isn't allowed now. >>> >> >> Why not? > > IIRC, mmc subsystem will behave as a lib in the long run, so the community > and developers call for no new quirk. For your case, we may need to handle > the udelay in sdhci-msm.c, export sdhci_irq as a helper function? > Thanks for the details and suggestions. I am going to wait until the US Thanksgiving (and cyber Monday) is over before I do any more. -jeremy -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2016-11-28 21:53 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-11-23 1:09 [PATCH 0/5] Enable onboard SDHCI for Nexus 5X (msm8992) Jeremy McNicoll
2016-11-23 1:09 ` [PATCH 1/5] clk: gcc: Updates for SDHCI enablement Jeremy McNicoll
2016-11-23 1:09 ` [PATCH 2/5] smd: Make packet size a constant Jeremy McNicoll
2016-11-24 6:14 ` Bjorn Andersson
2016-11-28 21:20 ` Jeremy McNicoll
2016-11-23 1:09 ` [PATCH 3/5] arm64: dts: Enable SDHCI for Nexus 5X (msm8992) Jeremy McNicoll
[not found] ` <1479863388-23678-4-git-send-email-jeremymc-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2016-11-28 21:53 ` Rob Herring
2016-11-23 1:09 ` [PATCH 4/5] sdhci: dump vendor state and regs Jeremy McNicoll
2016-11-23 1:09 ` [PATCH 5/5] sdhci: Add quirk for delayed IRQ ACK Jeremy McNicoll
2016-11-23 3:36 ` Jisheng Zhang
2016-11-23 3:48 ` Jeremy McNicoll
[not found] ` <ecacec51-4b06-49cd-c756-489128729499-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2016-11-23 4:12 ` Jisheng Zhang
2016-11-23 5:23 ` Jeremy McNicoll
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