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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAzNSBTYWx0ZWRfX3jP5QMoj/RFv XJrEF7BnW7+nCK0NGN78Mpkatc7REfDz6BF+dNc67V2J5SF+8IdS5VraW8BhuV8KbyneMLciVWA rlKrtVzJd6d6KtFM7S5VBYbs/xWZFsY= X-Proofpoint-ORIG-GUID: dHdHgNJh3DX61nxXyjUOyGeBAvLk3OGV X-Proofpoint-GUID: dHdHgNJh3DX61nxXyjUOyGeBAvLk3OGV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAzNSBTYWx0ZWRfX+LUp514ET0I2 tlRiJO5esLNXltZ2AKtKNPGDvMHgw7Q3cCYbf6ELSWzbRieUS2gC4Ca3nHn/gJOJ3LQimVEyFbg 3V9cdUe/eQpP/SMo7U4PWtXrsnmHijVfR9GtwMmkZzS12Y62CU9v/pMYu0RuIaBn+f2PHMjS7RE 8B+xxdVYQ7KxLQhSUmfJHQV66q1w7lX0B1VAsdfU/BN3j2td4nv4DJzOg0rSmJzBuY4/0poqcKJ FP5geFi+XrDnDHHshSXATm1hGg4pMkJfnouRoL6JA2qwe7lKFJsoegQw94kvFDaiiva4RIhjSZ1 5DDW4qv+KyILQ+ODR6uESgCbq2LQgkDFvA+b4qJuTSiJxvNlnjq/Xc9biRRx/HeCqI9+eNSESyG FOfENGopR/0Cv9BGwd0LMkMeGFCCS0njwh/KqUvJ41sejCXf7YPpzKa+uf8lzcCzImuFxrCWkvw hhml0C8/bbN//+W8xJg== X-Authority-Analysis: v=2.4 cv=NLpAaE6g c=1 sm=1 tr=0 ts=6ad87e91 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=cyixkC-7dOoUwMZJH6MA:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_02,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 impostorscore=0 phishscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210035 Hi, On 10/15/2026 8:18 AM, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: > - [Medium] dts: qcom: missing status = "okay" for pcie0_ep and pcie1_ep > - [Medium] dts: qcom: incorrect polarity for PCIe EP wake-gpios > -- > > commit 3fa46fe28ef2e9d52dd0b40b57be7d7192538595 > Author: Nikunj Kela > > arm64: dts: qcom: lemans: Enable lemans-sa8255p-ride board support > > Add initial device tree support for the Lemans SA8255P Ride board. Enable > UFS storage, UART10 as the serial console, PCIe EP interfaces, thermal > zones for PMM8654AU sensors, and SCMI protocol nodes. > >> diff --git a/arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts b/arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts >> new file mode 100644 >> index 0000000000000..4273f47c3dffc >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/lemans-sa8255p-ride.dts > > [ ... ] > >> +&pcie0_ep { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pcie0_ep_clkreq_default &pcie0_ep_perst_default >> + &pcie0_ep_wake_default>; >> + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; > > [Severity: Medium] > Since the commit message states this patch enables the PCIe EP interfaces, > should pcie0_ep include a status = "okay"; property? This needs not to be enabled by default as PCIe0 RC is enabled and both cannot be status = "okay" at the same time. > > Without explicitly overriding the status, the node will likely remain > disabled as typically defined in the base device tree, preventing the kernel > from probing the controller. > >> + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; > > [Severity: Medium] > Is the polarity for the wake-gpios correct here? Yes. > > The PCIe WAKE# signal is architecturally active-low and open-drain. By > configuring it as GPIO_ACTIVE_HIGH, the physical pad will be driven low > when the driver intends to initialize or deassert it, and high when > asserting it. > > Could this invert the wake signal and break PCIe endpoint power management > wakeups? No, this will not break the EP power management. > >> +}; >> + >> +&pcie1_ep { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pcie1_ep_clkreq_default &pcie1_ep_perst_default >> + &pcie1_ep_wake_default>; >> + reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; > > [Severity: Medium] > Similarly, should pcie1_ep also include a status = "okay"; property to > ensure it is enabled? This needs not to be enabled by default as PCIe0 RC is enabled and both cannot be status = "okay" at the same time. > >> + wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; > > [Severity: Medium] > Does this wake-gpios configuration also suffer from the same active-low > signal inversion issue as pcie0_ep? No. > >> +}; > -Shazad