From: Anurup M <anurupvasu@gmail.com>
To: robh+dt@kernel.org, mark.rutland@arm.com, will.deacon@arm.com
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, anurup.m@huawei.com,
zhangshaokun@hisilicon.com, tanxiaojun@huawei.com,
xuwei5@hisilicon.com, sanil.kumar@hisilicon.com,
john.garry@huawei.com, gabriele.paoloni@huawei.com,
shiju.jose@huawei.com, wangkefeng.wang@huawei.com,
linuxarm@huawei.com, shyju.pv@huawei.com, anurupvasu@gmail.com
Subject: [PATCH v2 02/10] dt-bindings: hisi: Add Hisilicon HiP05/06/07 Djtag dts bindings
Date: Wed, 7 Dec 2016 11:55:19 -0500 [thread overview]
Message-ID: <1481129719-159487-1-git-send-email-anurup.m@huawei.com> (raw)
From: Tan Xiaojun <tanxiaojun@huawei.com>
Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die
Signed-off-by: Tan Xiaojun <tanxiaojun@huawei.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
.../devicetree/bindings/arm/hisilicon/djtag.txt | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/djtag.txt
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt
new file mode 100644
index 0000000..733498e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt
@@ -0,0 +1,41 @@
+The Hisilicon Djtag is an independent component which connects with some other
+components in the SoC by Debug Bus. The djtag is available in CPU and IO dies
+in the chip. The djtag controls access to connecting modules of CPU and IO
+dies.
+The various connecting components in CPU die (like L3 cache, L3 cache PMU etc.)
+are accessed by djtag during real time debugging. In IO die there are connecting
+components like RSA. These components appear as devices atatched to djtag bus.
+
+Hisilicon HiP05/06 djtag for CPU and HiP05 IO die
+Required properties:
+ - compatible : "hisilicon,hisi-djtag-v1"
+ - reg : Register address and size
+ - scl-id : The Super Cluster ID for CPU or IO die
+
+Hisilicon HiP06 djtag for IO die and HiP07 djtag for CPU and IO die
+Required properties:
+ - compatible : "hisilicon,hisi-djtag-v2"
+ - reg : Register address and size
+ - scl-id : The Super Cluster ID for CPU or IO die
+
+Example 1: Djtag for CPU die
+
+ /* for Hisilicon HiP05 djtag for CPU Die */
+ djtag0: djtag@80010000 {
+ compatible = "hisilicon,hisi-djtag-v1";
+ reg = <0x0 0x80010000 0x0 0x10000>;
+ scl-id = <0x02>;
+
+ /* All connecting components will appear as child nodes */
+ };
+
+Example 2: Djtag for IO die
+
+ /* for Hisilicon HiP05 djtag for IO Die */
+ djtag1: djtag@d0000000 {
+ compatible = "hisilicon,hisi-djtag-v1";
+ reg = <0x0 0xd0000000 0x0 0x10000>;
+ scl-id = <0x01>;
+
+ /* All connecting components will appear as child nodes */
+ };
--
2.1.4
next reply other threads:[~2016-12-07 16:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-07 16:55 Anurup M [this message]
2016-12-19 16:31 ` [PATCH v2 02/10] dt-bindings: hisi: Add Hisilicon HiP05/06/07 Djtag dts bindings Rob Herring
2016-12-23 10:17 ` Anurup M
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