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From: "Cédric Le Goater" <clg@kaod.org>
To: linux-mtd@lists.infradead.org
Cc: "Mark Rutland" <mark.rutland@arm.com>,
	"Boris Brezillon" <boris.brezillon@free-electrons.com>,
	devicetree@vger.kernel.org, "Richard Weinberger" <richard@nod.at>,
	"Marek Vasut" <marek.vasut@gmail.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Joel Stanley" <joel@jms.id.au>,
	"Cyrille Pitchen" <cyrille.pitchen@atmel.com>,
	"Brian Norris" <computersforpeace@gmail.com>,
	"David Woodhouse" <dwmw2@infradead.org>,
	"Cédric Le Goater" <clg@kaod.org>
Subject: [PATCH v5 3/3] mtd: spi-nor: bindings for the Aspeed memory controllers
Date: Wed, 21 Dec 2016 17:57:19 +0100	[thread overview]
Message-ID: <1482339439-26402-4-git-send-email-clg@kaod.org> (raw)
In-Reply-To: <1482339439-26402-1-git-send-email-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/mtd/aspeed-smc.txt         | 51 ++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/aspeed-smc.txt

diff --git a/Documentation/devicetree/bindings/mtd/aspeed-smc.txt b/Documentation/devicetree/bindings/mtd/aspeed-smc.txt
new file mode 100644
index 000000000000..49f6528ef547
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/aspeed-smc.txt
@@ -0,0 +1,51 @@
+* Aspeed Firmware Memory controller
+* Aspeed SPI Flash Memory Controller
+
+The Firmware Memory Controller in the Aspeed AST2500 SoC supports
+three chip selects, two of which are always of SPI type and the third
+can be SPI or NOR type flash. These bindings only describe SPI.
+
+The two SPI flash memory controllers in the AST2500 each support two
+chip selects.
+
+Required properties:
+  - compatible : Should be one of
+	"aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
+	"aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
+	"aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
+	"aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
+
+  - reg : the first contains the control register location and length,
+          the second contains the memory window mapping address and length
+  - #address-cells : must be 1 corresponding to chip select child binding
+  - #size-cells : must be 0 corresponding to chip select child binding
+
+Optional properties:
+  - interrupts : Should contain the interrupt for the dma device if an
+    FMC
+
+The child nodes are the SPI flash modules which must have a compatible
+property as specified in bindings/mtd/jedec,spi-nor.txt
+
+Optionally, the child node can contain properties for SPI mode (may be
+ignored):
+  - spi-max-frequency - max frequency of spi bus
+
+
+Example:
+fmc: fmc@1e620000 {
+	compatible = "aspeed,ast2500-fmc";
+	reg = < 0x1e620000 0x94
+		0x20000000 0x02000000 >;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	interrupts = <19>;
+	flash@0 {
+		reg = < 0 >;
+		compatible = "jedec,spi-nor";
+		/* spi-max-frequency = <>; */
+		/* m25p,fast-read; */
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
-- 
2.7.4


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      parent reply	other threads:[~2016-12-21 16:57 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-21 16:57 [PATCH v5 0/3] Static memory controllers for the Aspeed SoC Cédric Le Goater
     [not found] ` <1482339439-26402-1-git-send-email-clg-Bxea+6Xhats@public.gmane.org>
2016-12-21 16:57   ` [PATCH v5 1/3] mtd: spi-nor: add memory controllers for the Aspeed AST2500 SoC Cédric Le Goater
2016-12-23 11:22   ` [PATCH v5 0/3] Static memory controllers for the Aspeed SoC Cyrille Pitchen
2016-12-21 16:57 ` [PATCH v5 2/3] mtd: aspeed: add memory controllers for the Aspeed AST2400 SoC Cédric Le Goater
2016-12-21 16:57 ` Cédric Le Goater [this message]

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