[PATCH v3 03/10] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU

[PATCH v3 03/10] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU

[Anurup M]

1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache and MN PMU.
3) Add child nodes of L3C and MN in djtag bindings example.

Signed-off-by: Anurup M <anurup.m-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Signed-off-by: Shaokun Zhang <zhangshaokun-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
---
 .../devicetree/bindings/arm/hisilicon/djtag.txt    |  25 ++++++
 .../devicetree/bindings/arm/hisilicon/pmu.txt      | 100 +++++++++++++++++++++
 2 files changed, 125 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt
index bbe8b45..653fdb7 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt
@@ -27,6 +27,31 @@ Example 1: Djtag for CPU die
 		hisi-scl-id = <0x02>;
 
 		/* All connecting components will appear as child nodes */
+
+		pmul3c0 {
+			compatible = "hisilicon,hip05-pmu-l3c-v1";
+			hisi-module-id = <0x04 0x02>;
+		};
+
+		pmul3c1 {
+			compatible = "hisilicon,hip05-pmu-l3c-v1";
+			hisi-module-id = <0x04 0x04>;
+		};
+
+		pmul3c2 {
+			compatible = "hisilicon,hip05-pmu-l3c-v1";
+			hisi-module-id = <0x04 0x01>;
+		};
+
+		pmul3c3 {
+			compatible = "hisilicon,hip05-pmu-l3c-v1";
+			hisi-module-id = <0x04 0x08>;
+		};
+
+		pmumn0 {
+			compatible = "hisilicon,hip05-pmu-mn-v1";
+			hisi-module-id = <0x0b>;
+		};
 	};
 
 Example 2: Djtag for IO die
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
new file mode 100644
index 0000000..fceef8d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
@@ -0,0 +1,100 @@
+Hisilicon SoC HiP05/06/07 ARMv8 PMU
+===================================
+
+The Hisilicon SoC chips like HiP05/06/07 etc. consist of various independent
+system device PMUs such as L3 cache (L3C) and Miscellaneous Nodes(MN). These
+PMU devices are independent and have hardware logic to gather statistics and
+performance information.
+
+HiSilicon SoC chip is encapsulated by multiple CPU and IO dies. The CPU die
+is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL
+in HiP05/06/07 chips are further grouped as CPU clusters (CCL) which includes
+4 cpu-cores each.
+e.g. In the case of HiP05/06/07, each SCCL has 1 L3 cache and 1 MN PMU device.
+The L3 cache is further grouped as 4 L3 cache banks in a SCCL.
+
+The Hisilicon SoC PMU DT node bindings for uncore PMU devices are as below.
+For PMU devices like L3 cache. MN etc. which are accessed using the djtag,
+the parent node will be the djtag node of the corresponding CPU die (SCCL).
+
+L3 cache
+---------
+The L3 cache is dedicated for each SCCL. Each SCCL in HiP05/06/07 chips have 4
+L3 cache banks. Each L3 cache bank have separate DT nodes.
+
+Required properties:
+
+	- compatible : This value should be as follows
+		(a) "hisilicon,hip05-pmu-l3c-v1" for v1 hw in HiP05 chipset
+		(b) "hisilicon,hip06-pmu-l3c-v1" for v1 hw in HiP06 chipset
+		(c) "hisilicon,hip07-pmu-l3c-v2" for v2 hw in HiP07 chipset
+
+	- hisi-module-id : This property is a combination of two values in the below order.
+		      a) Module ID: The module identifier for djtag.
+		      b) Instance or Bank ID: This will identify the L3 cache bank
+			 or instance.
+
+Optional properties:
+
+	- interrupt-parent : A phandle indicating which interrupt controller
+		this PMU signals interrupts to.
+
+	- interrupts : Interrupt line used by this L3 cache bank.
+
+	*The counter overflow IRQ is not supported in v1 hardware (HiP05/06).
+
+Miscellaneous Node
+------------------
+The MN is dedicated for each SCCL and hence there are separate DT nodes for MN
+for each SCCL.
+
+Required properties:
+
+	- compatible : This value should be as follows
+		(a) "hisilicon,hip05-pmu-mn-v1" for v1 hw in HiP05 chipset
+		(b) "hisilicon,hip06-pmu-mn-v1" for v1 hw in HiP06 chipset
+		(c) "hisilicon,hip07-pmu-mn-v2" for v2 hw in HiP07 chipset
+
+	- hisi-module-id : Module ID to input for djtag.
+
+Optional properties:
+
+	- interrupt-parent : A phandle indicating which interrupt controller
+		this PMU signals interrupts to.
+
+	- interrupts : Interrupt line used by this PMU.
+
+	*The counter overflow IRQ is not supported in v1 hardware (HiP05/06).
+
+Example:
+
+	djtag0: djtag@80010000 {
+		compatible = "hisilicon,hip05-djtag-v1";
+		reg = <0x0 0x80010000 0x0 0x10000>;
+		scl-id = <0x02>;
+
+		pmul3c0 {
+			compatible = "hisilicon,hip05-pmu-l3c-v1";
+			hisi-module-id = <0x04 0x02>;
+		};
+
+		pmul3c1 {
+			compatible = "hisilicon,hip05-pmu-l3c-v1";
+			hisi-module-id = <0x04 0x04>;
+		};
+
+		pmul3c2 {
+			compatible = "hisilicon,hip05-pmu-l3c-v1";
+			hisi-module-id = <0x04 0x01>;
+		};
+
+		pmul3c3 {
+			compatible = "hisilicon,hip05-pmu-l3c-v1";
+			hisi-module-id = <0x04 0x08>;
+		};
+
+		pmumn0 {
+			compatible = "hisilicon,hip05-pmu-mn-v1";
+			hisi-module-id = <0x0b>;
+		};
+	};
-- 
2.1.4

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Re: [PATCH v3 03/10] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU

[Rob Herring]

On Mon, Jan 02, 2017 at 01:49:21AM -0500, Anurup M wrote:
> 1) Device tree bindings for Hisilicon SoC PMU.
> 2) Add example for Hisilicon L3 cache and MN PMU.
> 3) Add child nodes of L3C and MN in djtag bindings example.
> 
> Signed-off-by: Anurup M <anurup.m-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
> Signed-off-by: Shaokun Zhang <zhangshaokun-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> ---
>  .../devicetree/bindings/arm/hisilicon/djtag.txt    |  25 ++++++
>  .../devicetree/bindings/arm/hisilicon/pmu.txt      | 100 +++++++++++++++++++++
>  2 files changed, 125 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt
> index bbe8b45..653fdb7 100644
> --- a/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt
> @@ -27,6 +27,31 @@ Example 1: Djtag for CPU die
>  		hisi-scl-id = <0x02>;
>  
>  		/* All connecting components will appear as child nodes */
> +
> +		pmul3c0 {
> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
> +			hisi-module-id = <0x04 0x02>;
> +		};
> +
> +		pmul3c1 {
> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
> +			hisi-module-id = <0x04 0x04>;
> +		};
> +
> +		pmul3c2 {
> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
> +			hisi-module-id = <0x04 0x01>;
> +		};
> +
> +		pmul3c3 {
> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
> +			hisi-module-id = <0x04 0x08>;
> +		};
> +
> +		pmumn0 {
> +			compatible = "hisilicon,hip05-pmu-mn-v1";
> +			hisi-module-id = <0x0b>;
> +		};
>  	};
>  
>  Example 2: Djtag for IO die
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
> new file mode 100644
> index 0000000..fceef8d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
> @@ -0,0 +1,100 @@
> +Hisilicon SoC HiP05/06/07 ARMv8 PMU
> +===================================
> +
> +The Hisilicon SoC chips like HiP05/06/07 etc. consist of various independent
> +system device PMUs such as L3 cache (L3C) and Miscellaneous Nodes(MN). These
> +PMU devices are independent and have hardware logic to gather statistics and
> +performance information.
> +
> +HiSilicon SoC chip is encapsulated by multiple CPU and IO dies. The CPU die
> +is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL
> +in HiP05/06/07 chips are further grouped as CPU clusters (CCL) which includes
> +4 cpu-cores each.
> +e.g. In the case of HiP05/06/07, each SCCL has 1 L3 cache and 1 MN PMU device.
> +The L3 cache is further grouped as 4 L3 cache banks in a SCCL.
> +
> +The Hisilicon SoC PMU DT node bindings for uncore PMU devices are as below.
> +For PMU devices like L3 cache. MN etc. which are accessed using the djtag,
> +the parent node will be the djtag node of the corresponding CPU die (SCCL).
> +
> +L3 cache
> +---------
> +The L3 cache is dedicated for each SCCL. Each SCCL in HiP05/06/07 chips have 4
> +L3 cache banks. Each L3 cache bank have separate DT nodes.
> +
> +Required properties:
> +
> +	- compatible : This value should be as follows
> +		(a) "hisilicon,hip05-pmu-l3c-v1" for v1 hw in HiP05 chipset
> +		(b) "hisilicon,hip06-pmu-l3c-v1" for v1 hw in HiP06 chipset
> +		(c) "hisilicon,hip07-pmu-l3c-v2" for v2 hw in HiP07 chipset
> +
> +	- hisi-module-id : This property is a combination of two values in the below order.

Vendor prefix: hisilicon,module-id

> +		      a) Module ID: The module identifier for djtag.
> +		      b) Instance or Bank ID: This will identify the L3 cache bank
> +			 or instance.
> +
> +Optional properties:
> +
> +	- interrupt-parent : A phandle indicating which interrupt controller
> +		this PMU signals interrupts to.
> +
> +	- interrupts : Interrupt line used by this L3 cache bank.
> +
> +	*The counter overflow IRQ is not supported in v1 hardware (HiP05/06).
> +
> +Miscellaneous Node
> +------------------
> +The MN is dedicated for each SCCL and hence there are separate DT nodes for MN
> +for each SCCL.
> +
> +Required properties:
> +
> +	- compatible : This value should be as follows
> +		(a) "hisilicon,hip05-pmu-mn-v1" for v1 hw in HiP05 chipset
> +		(b) "hisilicon,hip06-pmu-mn-v1" for v1 hw in HiP06 chipset
> +		(c) "hisilicon,hip07-pmu-mn-v2" for v2 hw in HiP07 chipset
> +
> +	- hisi-module-id : Module ID to input for djtag.

ditto

> +
> +Optional properties:
> +
> +	- interrupt-parent : A phandle indicating which interrupt controller
> +		this PMU signals interrupts to.
> +
> +	- interrupts : Interrupt line used by this PMU.
> +
> +	*The counter overflow IRQ is not supported in v1 hardware (HiP05/06).
> +
> +Example:
> +
> +	djtag0: djtag@80010000 {
> +		compatible = "hisilicon,hip05-djtag-v1";
> +		reg = <0x0 0x80010000 0x0 0x10000>;
> +		scl-id = <0x02>;
> +
> +		pmul3c0 {
> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
> +			hisi-module-id = <0x04 0x02>;
> +		};
> +
> +		pmul3c1 {
> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
> +			hisi-module-id = <0x04 0x04>;
> +		};
> +
> +		pmul3c2 {
> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
> +			hisi-module-id = <0x04 0x01>;
> +		};
> +
> +		pmul3c3 {
> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
> +			hisi-module-id = <0x04 0x08>;
> +		};
> +
> +		pmumn0 {
> +			compatible = "hisilicon,hip05-pmu-mn-v1";
> +			hisi-module-id = <0x0b>;
> +		};
> +	};
> -- 
> 2.1.4
> 
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Re: [PATCH v3 03/10] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU

[Anurup M]

On Wednesday 04 January 2017 04:29 AM, Rob Herring wrote:
> On Mon, Jan 02, 2017 at 01:49:21AM -0500, Anurup M wrote:
>> 1) Device tree bindings for Hisilicon SoC PMU.
>> 2) Add example for Hisilicon L3 cache and MN PMU.
>> 3) Add child nodes of L3C and MN in djtag bindings example.
>>
>> Signed-off-by: Anurup M <anurup.m-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
>> Signed-off-by: Shaokun Zhang <zhangshaokun-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
>> ---
>>   .../devicetree/bindings/arm/hisilicon/djtag.txt    |  25 ++++++
>>   .../devicetree/bindings/arm/hisilicon/pmu.txt      | 100 +++++++++++++++++++++
>>   2 files changed, 125 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt
>> index bbe8b45..653fdb7 100644
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt
>> @@ -27,6 +27,31 @@ Example 1: Djtag for CPU die
>>   		hisi-scl-id = <0x02>;
>>   
>>   		/* All connecting components will appear as child nodes */
>> +
>> +		pmul3c0 {
>> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
>> +			hisi-module-id = <0x04 0x02>;
>> +		};
>> +
>> +		pmul3c1 {
>> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
>> +			hisi-module-id = <0x04 0x04>;
>> +		};
>> +
>> +		pmul3c2 {
>> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
>> +			hisi-module-id = <0x04 0x01>;
>> +		};
>> +
>> +		pmul3c3 {
>> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
>> +			hisi-module-id = <0x04 0x08>;
>> +		};
>> +
>> +		pmumn0 {
>> +			compatible = "hisilicon,hip05-pmu-mn-v1";
>> +			hisi-module-id = <0x0b>;
>> +		};
>>   	};
>>   
>>   Example 2: Djtag for IO die
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
>> new file mode 100644
>> index 0000000..fceef8d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
>> @@ -0,0 +1,100 @@
>> +Hisilicon SoC HiP05/06/07 ARMv8 PMU
>> +===================================
>> +
>> +The Hisilicon SoC chips like HiP05/06/07 etc. consist of various independent
>> +system device PMUs such as L3 cache (L3C) and Miscellaneous Nodes(MN). These
>> +PMU devices are independent and have hardware logic to gather statistics and
>> +performance information.
>> +
>> +HiSilicon SoC chip is encapsulated by multiple CPU and IO dies. The CPU die
>> +is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL
>> +in HiP05/06/07 chips are further grouped as CPU clusters (CCL) which includes
>> +4 cpu-cores each.
>> +e.g. In the case of HiP05/06/07, each SCCL has 1 L3 cache and 1 MN PMU device.
>> +The L3 cache is further grouped as 4 L3 cache banks in a SCCL.
>> +
>> +The Hisilicon SoC PMU DT node bindings for uncore PMU devices are as below.
>> +For PMU devices like L3 cache. MN etc. which are accessed using the djtag,
>> +the parent node will be the djtag node of the corresponding CPU die (SCCL).
>> +
>> +L3 cache
>> +---------
>> +The L3 cache is dedicated for each SCCL. Each SCCL in HiP05/06/07 chips have 4
>> +L3 cache banks. Each L3 cache bank have separate DT nodes.
>> +
>> +Required properties:
>> +
>> +	- compatible : This value should be as follows
>> +		(a) "hisilicon,hip05-pmu-l3c-v1" for v1 hw in HiP05 chipset
>> +		(b) "hisilicon,hip06-pmu-l3c-v1" for v1 hw in HiP06 chipset
>> +		(c) "hisilicon,hip07-pmu-l3c-v2" for v2 hw in HiP07 chipset
>> +
>> +	- hisi-module-id : This property is a combination of two values in the below order.
> Vendor prefix: hisilicon,module-id

Ok. I shall modify it.

>> +		      a) Module ID: The module identifier for djtag.
>> +		      b) Instance or Bank ID: This will identify the L3 cache bank
>> +			 or instance.
>> +
>> +Optional properties:
>> +
>> +	- interrupt-parent : A phandle indicating which interrupt controller
>> +		this PMU signals interrupts to.
>> +
>> +	- interrupts : Interrupt line used by this L3 cache bank.
>> +
>> +	*The counter overflow IRQ is not supported in v1 hardware (HiP05/06).
>> +
>> +Miscellaneous Node
>> +------------------
>> +The MN is dedicated for each SCCL and hence there are separate DT nodes for MN
>> +for each SCCL.
>> +
>> +Required properties:
>> +
>> +	- compatible : This value should be as follows
>> +		(a) "hisilicon,hip05-pmu-mn-v1" for v1 hw in HiP05 chipset
>> +		(b) "hisilicon,hip06-pmu-mn-v1" for v1 hw in HiP06 chipset
>> +		(c) "hisilicon,hip07-pmu-mn-v2" for v2 hw in HiP07 chipset
>> +
>> +	- hisi-module-id : Module ID to input for djtag.
> ditto

Ok. I shall modify it.

Thanks,
Anurup

>> +
>> +Optional properties:
>> +
>> +	- interrupt-parent : A phandle indicating which interrupt controller
>> +		this PMU signals interrupts to.
>> +
>> +	- interrupts : Interrupt line used by this PMU.
>> +
>> +	*The counter overflow IRQ is not supported in v1 hardware (HiP05/06).
>> +
>> +Example:
>> +
>> +	djtag0: djtag@80010000 {
>> +		compatible = "hisilicon,hip05-djtag-v1";
>> +		reg = <0x0 0x80010000 0x0 0x10000>;
>> +		scl-id = <0x02>;
>> +
>> +		pmul3c0 {
>> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
>> +			hisi-module-id = <0x04 0x02>;
>> +		};
>> +
>> +		pmul3c1 {
>> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
>> +			hisi-module-id = <0x04 0x04>;
>> +		};
>> +
>> +		pmul3c2 {
>> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
>> +			hisi-module-id = <0x04 0x01>;
>> +		};
>> +
>> +		pmul3c3 {
>> +			compatible = "hisilicon,hip05-pmu-l3c-v1";
>> +			hisi-module-id = <0x04 0x08>;
>> +		};
>> +
>> +		pmumn0 {
>> +			compatible = "hisilicon,hip05-pmu-mn-v1";
>> +			hisi-module-id = <0x0b>;
>> +		};
>> +	};
>> -- 
>> 2.1.4
>>

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