From: Anurup M <anurupvasu@gmail.com>
To: mark.rutland@arm.com, will.deacon@arm.com, robh+dt@kernel.org,
xuwei5@hisilicon.com, catalin.marinas@arm.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, anurup.m@huawei.com,
zhangshaokun@hisilicon.com, tanxiaojun@huawei.com,
sanil.kumar@hisilicon.com, john.garry@huawei.com,
gabriele.paoloni@huawei.com, shiju.jose@huawei.com,
linuxarm@huawei.com, shyju.pv@huawei.com, anurupvasu@gmail.com
Subject: [PATCH v3 10/10] dts: arm64: hip06: Add Hisilicon SoC PMU support
Date: Mon, 2 Jan 2017 01:51:17 -0500 [thread overview]
Message-ID: <1483339877-24252-1-git-send-email-anurup.m@huawei.com> (raw)
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Anurup M <anurup.m@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 72 ++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index e861698..02ff95f 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -963,6 +963,78 @@
status = "disabled";
};
+ djtag0: djtag@60010000 {
+ compatible = "hisilicon,hip06-djtag-v1";
+ reg = <0x0 0x60010000 0x0 0x10000>;
+ hisi-scl-id = <0x02>;
+
+ /* L3 cache bank 0 for socket0 CPU die scl#2 */
+ pmul3c0 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x02>;
+ };
+
+ /* L3 cache bank 1 for socket0 CPU die scl#2 */
+ pmul3c1 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x04>;
+ };
+
+ /* L3 cache bank 2 for socket0 CPU die scl#2 */
+ pmul3c2 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x01>;
+ };
+
+ /* L3 cache bank 3 for socket0 CPU die scl#2 */
+ pmul3c3 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x08>;
+ };
+
+ /* Miscellaneous node for socket0 CPU die scl#2 */
+ pmumn0 {
+ compatible = "hisilicon,hip06-pmu-mn-v1";
+ hisi-module-id = <0x0b>;
+ };
+ };
+
+ djtag1: djtag@40010000 {
+ compatible = "hisilicon,hip06-djtag-v1";
+ reg = <0x0 0x40010000 0x0 0x10000>;
+ hisi-scl-id = <0x01>;
+
+ /* L3 cache bank 0 for socket0 CPU die scl#1 */
+ pmul3c0 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x02>;
+ };
+
+ /* L3 cache bank 1 for socket0 CPU die scl#1 */
+ pmul3c1 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x04>;
+ };
+
+ /* L3 cache bank 2 for socket0 CPU die scl#1 */
+ pmul3c2 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x01>;
+ };
+
+ /* L3 cache bank 3 for socket0 CPU die scl#1 */
+ pmul3c3 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x08>;
+ };
+
+ /* Miscellaneous node for socket0 CPU die scl#1 */
+ pmumn1 {
+ compatible = "hisilicon,hip06-pmu-mn-v1";
+ hisi-module-id = <0x0b>;
+ };
+ };
+
sas1: sas@a2000000 {
compatible = "hisilicon,hip06-sas-v2";
reg = <0 0xa2000000 0 0x10000>;
--
2.1.4
reply other threads:[~2017-01-02 6:51 UTC|newest]
Thread overview: [no followups] expand[flat|nested] mbox.gz Atom feed
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1483339877-24252-1-git-send-email-anurup.m@huawei.com \
--to=anurupvasu@gmail.com \
--cc=anurup.m@huawei.com \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=gabriele.paoloni@huawei.com \
--cc=john.garry@huawei.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linuxarm@huawei.com \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
--cc=sanil.kumar@hisilicon.com \
--cc=shiju.jose@huawei.com \
--cc=shyju.pv@huawei.com \
--cc=tanxiaojun@huawei.com \
--cc=will.deacon@arm.com \
--cc=xuwei5@hisilicon.com \
--cc=zhangshaokun@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).