From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Stephen Warren <swarren@wwwdotorg.org>,
Thierry Reding <thierry.reding@gmail.com>,
Alexandre Courbot <gnurou@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Rhyland Klein <rklein@nvidia.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCH 4/7] clk: tegra: remove non-existing pll_m_out1 clock
Date: Wed, 22 Feb 2017 17:13:59 +0200 [thread overview]
Message-ID: <1487776444-4701-5-git-send-email-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <1487776444-4701-1-git-send-email-pdeschrijver@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 7bda8ba..b7ef8a7 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2115,7 +2115,6 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
[tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true },
[tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true },
[tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true },
- [tegra_clk_pll_m_out1] = { .dt_id = TEGRA210_CLK_PLL_M_OUT1, .present = true },
[tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
[tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true },
[tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true },
@@ -2229,7 +2228,6 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
{ .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },
{ .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },
{ .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },
- { .con_id = "pll_m_out1", .dt_id = TEGRA210_CLK_PLL_M_OUT1 },
{ .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },
{ .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },
{ .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
@@ -2404,9 +2402,6 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
clk_register_clkdev(clk, "pll_mb", NULL);
clks[TEGRA210_CLK_PLL_MB] = clk;
- clk_register_clkdev(clk, "pll_m_out1", NULL);
- clks[TEGRA210_CLK_PLL_M_OUT1] = clk;
-
/* PLLM_UD */
clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
CLK_SET_RATE_PARENT, 1, 1);
--
1.9.1
next prev parent reply other threads:[~2017-02-22 15:13 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-22 15:13 [PATCH 0/7] Tegra210 clock bug fixes Peter De Schrijver
2017-02-22 15:13 ` [PATCH 2/7] clk: tegra: fix isp clock modelling Peter De Schrijver
2017-02-23 7:49 ` Mikko Perttunen
2017-02-22 15:13 ` [PATCH 3/7] clk: tegra: correct afi parent Peter De Schrijver
[not found] ` <1487776444-4701-4-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-02-23 9:01 ` Mikko Perttunen
2017-02-22 15:13 ` Peter De Schrijver [this message]
[not found] ` <1487776444-4701-5-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-02-22 16:31 ` [PATCH 4/7] clk: tegra: remove non-existing pll_m_out1 clock Mikko Perttunen
2017-02-23 8:17 ` Mikko Perttunen
[not found] ` <3be69e34-354c-81ea-0c5e-182a79aa42d0-/1wQRMveznE@public.gmane.org>
2017-02-23 8:17 ` Mikko Perttunen
[not found] ` <1487776444-4701-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-02-22 15:13 ` [PATCH 1/7] clk: tegra: fix pll_a1 iddq register, add pll_a1 Peter De Schrijver
[not found] ` <1487776444-4701-2-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-02-22 16:38 ` Mikko Perttunen
2017-02-22 15:14 ` [PATCH 5/7] clk: tegra: don't warn for PLL defaults unnecessarily Peter De Schrijver
2017-02-23 9:06 ` Mikko Perttunen
2017-02-22 15:14 ` [PATCH 6/7] clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation Peter De Schrijver
[not found] ` <1487776444-4701-7-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-02-23 9:18 ` Mikko Perttunen
2017-02-22 15:14 ` [PATCH 7/7] clk: tegra: fix type for m field Peter De Schrijver
2017-02-23 9:18 ` Mikko Perttunen
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