[PATCH 0/4] ARM: sun7i: Convert sun7i SoC to sunxi-ng

[PATCH 0/4] ARM: sun7i: Convert sun7i SoC to sunxi-ng

[Priit Laes]

Hi,

This is serie brings another SoC into the sunxi-ng world.

As mentioned in sun5i conversion, this is pretty much standard
stuff as all the required clocks were already implemented in
the sunxi-ng framework.


Priit Laes (4):
  clk: sunxi-ng: Add clocks and reset indices for sun7i-a20 SoC
  clk: sunxi-ng: Add sun7i-a20 CCU driver
  ARM: sun7i: Convert to CCU
  dt-bindings: List devicetree binding for the CCU of Allwinner A20

 .../devicetree/bindings/clock/sunxi-ccu.txt        |    1 +
 arch/arm/boot/dts/sun7i-a20.dtsi                   |  719 ++-----------
 drivers/clk/sunxi-ng/Kconfig                       |   11 +
 drivers/clk/sunxi-ng/Makefile                      |    1 +
 drivers/clk/sunxi-ng/ccu-sun7i-a20.c               | 1068 ++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-sun7i-a20.h               |  121 +++
 include/dt-bindings/clock/sun7i-ccu.h              |  127 +++
 include/dt-bindings/reset/sun7i-ccu.h              |   40 +
 8 files changed, 1455 insertions(+), 633 deletions(-)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun7i-a20.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun7i-a20.h
 create mode 100644 include/dt-bindings/clock/sun7i-ccu.h
 create mode 100644 include/dt-bindings/reset/sun7i-ccu.h

-- 
2.9.3

[PATCH 1/4] clk: sunxi-ng: Add clocks and reset indices for sun7i-a20 SoC

[Priit Laes]

Add preliminary list of exported clocks and reset indices for
sun7i-a20 SoC, based on existing sun7i-a20 devicetree implementation.

Signed-off-by: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
---
 include/dt-bindings/clock/sun7i-ccu.h | 127 ++++++++++++++++++++++++++++++++++
 include/dt-bindings/reset/sun7i-ccu.h |  40 +++++++++++
 2 files changed, 167 insertions(+)
 create mode 100644 include/dt-bindings/clock/sun7i-ccu.h
 create mode 100644 include/dt-bindings/reset/sun7i-ccu.h

diff --git a/include/dt-bindings/clock/sun7i-ccu.h b/include/dt-bindings/clock/sun7i-ccu.h
new file mode 100644
index 0000000..52c4f76
--- /dev/null
+++ b/include/dt-bindings/clock/sun7i-ccu.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2017 Priit Laes
+ *
+ * Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN7I_H_
+#define _DT_BINDINGS_CLK_SUN7I_H_
+
+#define CLK_HOSC		1
+#define CLK_PLL_PERIPH_SATA	16
+#define CLK_CPU			19
+
+/* AHB Gates */
+#define CLK_AHB_OTG		24
+#define CLK_AHB_EHCI0		25
+#define CLK_AHB_OHCI0		26
+#define CLK_AHB_EHCI1		27
+#define CLK_AHB_OHCI1		28
+#define CLK_AHB_SS		29
+#define CLK_AHB_DMA		30
+
+#define CLK_AHB_MMC0		32
+#define CLK_AHB_MMC1		33
+#define CLK_AHB_MMC2		34
+#define CLK_AHB_MMC3		35
+
+#define CLK_AHB_NAND		37
+
+#define CLK_AHB_EMAC		40
+
+#define CLK_AHB_SPI0		42
+#define CLK_AHB_SPI1		43
+#define CLK_AHB_SPI2		44
+#define CLK_AHB_SPI3		45
+#define CLK_AHB_SATA		46
+#define CLK_AHB_HSTIMER		47
+
+#define CLK_AHB_TVE0		50
+#define CLK_AHB_LCD0		52
+#define CLK_AHB_HDMI1		57
+#define CLK_AHB_DE_BE0		58
+
+#define CLK_AHB_GMAC		62
+
+/* APB0 Gates */
+#define CLK_APB0_CODEC		65
+#define CLK_APB0_SPDIF		66
+#define CLK_APB0_I2S0		68
+#define CLK_APB0_I2S1		69
+#define CLK_APB0_PIO		70
+#define CLK_APB0_IR0		71
+#define CLK_APB0_IR1		72
+#define CLK_APB0_I2S2		73
+
+/* APB1 Gates */
+#define CLK_APB1_I2C0		75
+#define CLK_APB1_I2C1		76
+#define CLK_APB1_I2C2		77
+#define CLK_APB1_I2C3		78
+
+#define CLK_APB1_PS20		81
+#define CLK_APB1_PS21		82
+#define CLK_APB1_I2C4		83
+#define CLK_APB1_UART0		84
+#define CLK_APB1_UART1		85
+#define CLK_APB1_UART2		86
+#define CLK_APB1_UART3		87
+#define CLK_APB1_UART4		88
+#define CLK_APB1_UART5		89
+#define CLK_APB1_UART6		90
+#define CLK_APB1_UART7		91
+
+/* IP blocks */
+#define CLK_NAND		92
+
+#define CLK_MMC0		94
+#define CLK_MMC0_OUTPUT		95
+#define CLK_MMC0_SAMPLE		96
+#define CLK_MMC1		97
+#define CLK_MMC1_OUTPUT		98
+#define CLK_MMC1_SAMPLE		99
+#define CLK_MMC2		100
+#define CLK_MMC2_OUTPUT		101
+#define CLK_MMC2_SAMPLE		102
+#define CLK_MMC3		103
+#define CLK_MMC3_OUTPUT		104
+#define CLK_MMC3_SAMPLE		105
+
+#define CLK_SS			107
+#define CLK_SPI0		108
+#define CLK_SPI1		109
+#define CLK_SPI2		110
+#define CLK_IR0			112
+#define CLK_IR1			113
+#define CLK_I2S0		114
+
+#define CLK_SPDIF		116
+
+#define CLK_USB_OHCI0		119
+#define CLK_USB_OHCI1		120
+#define CLK_USB_PHY		121
+#define CLK_SPI3		122
+#define CLK_I2S1		123
+#define CLK_I2S2		124
+
+/* DRAM Gates */
+#define CLK_DRAM_TVE0		130
+#define CLK_DRAM_DE_BE0		134
+
+/* Display Engine Clocks */
+#define CLK_DE_BE0		139
+#define CLK_TCON0_CH0		144
+#define CLK_TCON0_CH1		149
+#define CLK_CODEC		153
+
+#endif /* _DT_BINDINGS_CLK_SUN7I_H_ */
diff --git a/include/dt-bindings/reset/sun7i-ccu.h b/include/dt-bindings/reset/sun7i-ccu.h
new file mode 100644
index 0000000..b8709ab
--- /dev/null
+++ b/include/dt-bindings/reset/sun7i-ccu.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Priit Laes
+ *
+ * Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _RST_SUN7I_H_
+#define _RST_SUN7I_H_
+
+#define	RST_USB_PHY0		1
+#define	RST_USB_PHY1		2
+#define	RST_USB_PHY2		3
+#define	RST_DE_BE0		4
+#define	RST_DE_BE1		5
+#define	RST_DE_FE0		6
+#define	RST_DE_FE1		7
+#define	RST_DE_MP		8
+#define	RST_TCON0		9
+#define	RST_TCON1		10
+#define	RST_CSI0		11
+#define	RST_CSI1		12
+#define	RST_VE			13
+#define	RST_ACE			14
+#define	RST_LVDS		15
+#define	RST_GPU			16
+#define	RST_HDMI_H		17
+#define	RST_HDMI_SYS		18
+#define	RST_HDMI_AUDIO_DMA	19
+
+#endif /* _RST_SUN7I_H_ */
-- 
2.9.3

Re: [PATCH 1/4] clk: sunxi-ng: Add clocks and reset indices for sun7i-a20 SoC

[Emmanuel Vadot]

 Hello Priit,

On Mon, 27 Feb 2017 23:09:11 +0200
Priit Laes <plaes@plaes.org> wrote:

> Add preliminary list of exported clocks and reset indices for
> sun7i-a20 SoC, based on existing sun7i-a20 devicetree implementation.
> 
> Signed-off-by: Priit Laes <plaes@plaes.org>
> ---
>  include/dt-bindings/clock/sun7i-ccu.h | 127 ++++++++++++++++++++++++++++++++++
>  include/dt-bindings/reset/sun7i-ccu.h |  40 +++++++++++
>  2 files changed, 167 insertions(+)
>  create mode 100644 include/dt-bindings/clock/sun7i-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun7i-ccu.h
> 
> diff --git a/include/dt-bindings/clock/sun7i-ccu.h b/include/dt-bindings/clock/sun7i-ccu.h
> new file mode 100644
> index 0000000..52c4f76
> --- /dev/null
> +++ b/include/dt-bindings/clock/sun7i-ccu.h
> @@ -0,0 +1,127 @@
> +/*
> + * Copyright 2017 Priit Laes
> + *
> + * Priit Laes <plaes@plaes.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */

 Do you mind dual licence those header under GPL/MIT like the others ?
 We currently dont use those directly in FreeBSD but we should (and
will soon) and we can't if they are only GPL.

 Thanks.

> +
> +#ifndef _DT_BINDINGS_CLK_SUN7I_H_
> +#define _DT_BINDINGS_CLK_SUN7I_H_
> +
> +#define CLK_HOSC		1
> +#define CLK_PLL_PERIPH_SATA	16
> +#define CLK_CPU			19
> +
> +/* AHB Gates */
> +#define CLK_AHB_OTG		24
> +#define CLK_AHB_EHCI0		25
> +#define CLK_AHB_OHCI0		26
> +#define CLK_AHB_EHCI1		27
> +#define CLK_AHB_OHCI1		28
> +#define CLK_AHB_SS		29
> +#define CLK_AHB_DMA		30
> +
> +#define CLK_AHB_MMC0		32
> +#define CLK_AHB_MMC1		33
> +#define CLK_AHB_MMC2		34
> +#define CLK_AHB_MMC3		35
> +
> +#define CLK_AHB_NAND		37
> +
> +#define CLK_AHB_EMAC		40
> +
> +#define CLK_AHB_SPI0		42
> +#define CLK_AHB_SPI1		43
> +#define CLK_AHB_SPI2		44
> +#define CLK_AHB_SPI3		45
> +#define CLK_AHB_SATA		46
> +#define CLK_AHB_HSTIMER		47
> +
> +#define CLK_AHB_TVE0		50
> +#define CLK_AHB_LCD0		52
> +#define CLK_AHB_HDMI1		57

 We use HDMI (not HDMI1) on FreeBSD (see
https://svnweb.freebsd.org/base/head/sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi?revision=308672&view=markup#l71)

 If you could define it in your patch this will be great.

> +#define CLK_AHB_DE_BE0		58
> +
> +#define CLK_AHB_GMAC		62
> +
> +/* APB0 Gates */
> +#define CLK_APB0_CODEC		65
> +#define CLK_APB0_SPDIF		66
> +#define CLK_APB0_I2S0		68
> +#define CLK_APB0_I2S1		69
> +#define CLK_APB0_PIO		70
> +#define CLK_APB0_IR0		71
> +#define CLK_APB0_IR1		72
> +#define CLK_APB0_I2S2		73
> +
> +/* APB1 Gates */
> +#define CLK_APB1_I2C0		75
> +#define CLK_APB1_I2C1		76
> +#define CLK_APB1_I2C2		77
> +#define CLK_APB1_I2C3		78
> +
> +#define CLK_APB1_PS20		81
> +#define CLK_APB1_PS21		82
> +#define CLK_APB1_I2C4		83
> +#define CLK_APB1_UART0		84
> +#define CLK_APB1_UART1		85
> +#define CLK_APB1_UART2		86
> +#define CLK_APB1_UART3		87
> +#define CLK_APB1_UART4		88
> +#define CLK_APB1_UART5		89
> +#define CLK_APB1_UART6		90
> +#define CLK_APB1_UART7		91
> +
> +/* IP blocks */
> +#define CLK_NAND		92
> +
> +#define CLK_MMC0		94
> +#define CLK_MMC0_OUTPUT		95
> +#define CLK_MMC0_SAMPLE		96
> +#define CLK_MMC1		97
> +#define CLK_MMC1_OUTPUT		98
> +#define CLK_MMC1_SAMPLE		99
> +#define CLK_MMC2		100
> +#define CLK_MMC2_OUTPUT		101
> +#define CLK_MMC2_SAMPLE		102
> +#define CLK_MMC3		103
> +#define CLK_MMC3_OUTPUT		104
> +#define CLK_MMC3_SAMPLE		105
> +
> +#define CLK_SS			107
> +#define CLK_SPI0		108
> +#define CLK_SPI1		109
> +#define CLK_SPI2		110
> +#define CLK_IR0			112
> +#define CLK_IR1			113
> +#define CLK_I2S0		114
> +
> +#define CLK_SPDIF		116
> +
> +#define CLK_USB_OHCI0		119
> +#define CLK_USB_OHCI1		120
> +#define CLK_USB_PHY		121
> +#define CLK_SPI3		122
> +#define CLK_I2S1		123
> +#define CLK_I2S2		124
> +
> +/* DRAM Gates */
> +#define CLK_DRAM_TVE0		130
> +#define CLK_DRAM_DE_BE0		134
> +
> +/* Display Engine Clocks */
> +#define CLK_DE_BE0		139
> +#define CLK_TCON0_CH0		144
> +#define CLK_TCON0_CH1		149
> +#define CLK_CODEC		153
> +
> +#endif /* _DT_BINDINGS_CLK_SUN7I_H_ */
> diff --git a/include/dt-bindings/reset/sun7i-ccu.h b/include/dt-bindings/reset/sun7i-ccu.h
> new file mode 100644
> index 0000000..b8709ab
> --- /dev/null
> +++ b/include/dt-bindings/reset/sun7i-ccu.h
> @@ -0,0 +1,40 @@
> +/*
> + * Copyright 2017 Priit Laes
> + *
> + * Priit Laes <plaes@plaes.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef _RST_SUN7I_H_
> +#define _RST_SUN7I_H_
> +
> +#define	RST_USB_PHY0		1
> +#define	RST_USB_PHY1		2
> +#define	RST_USB_PHY2		3
> +#define	RST_DE_BE0		4
> +#define	RST_DE_BE1		5
> +#define	RST_DE_FE0		6
> +#define	RST_DE_FE1		7
> +#define	RST_DE_MP		8
> +#define	RST_TCON0		9
> +#define	RST_TCON1		10
> +#define	RST_CSI0		11
> +#define	RST_CSI1		12
> +#define	RST_VE			13
> +#define	RST_ACE			14
> +#define	RST_LVDS		15
> +#define	RST_GPU			16
> +#define	RST_HDMI_H		17
> +#define	RST_HDMI_SYS		18
> +#define	RST_HDMI_AUDIO_DMA	19
> +
> +#endif /* _RST_SUN7I_H_ */
> -- 
> 2.9.3
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


-- 
Emmanuel Vadot <manu@bidouilliste.com> <manu@freebsd.org>

[PATCH 2/4] clk: sunxi-ng: Add sun7i-a20 CCU driver

[Priit Laes]

Introduce a clock controller driver for sun7i A20 SoC.

Signed-off-by: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
---
 drivers/clk/sunxi-ng/Kconfig         |   11 +
 drivers/clk/sunxi-ng/Makefile        |    1 +
 drivers/clk/sunxi-ng/ccu-sun7i-a20.c | 1068 ++++++++++++++++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-sun7i-a20.h |  121 ++++
 4 files changed, 1201 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun7i-a20.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun7i-a20.h

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 695bbf9..4f436ab 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -85,6 +85,17 @@ config SUN6I_A31_CCU
 	select SUNXI_CCU_PHASE
 	default MACH_SUN6I
 
+config SUN7I_A20_CCU
+	bool "Support for the Allwinner A20 CCU"
+	select SUNXI_CCU_DIV
+	select SUNXI_CCU_MULT
+	select SUNXI_CCU_NK
+	select SUNXI_CCU_NKM
+	select SUNXI_CCU_NM
+	select SUNXI_CCU_MP
+	select SUNXI_CCU_PHASE
+	default MACH_SUN7I
+
 config SUN8I_A23_CCU
 	bool "Support for the Allwinner A23 CCU"
 	select SUNXI_CCU_DIV
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 6feaac0..bedda5b 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_SUNXI_CCU_MP)	+= ccu_mp.o
 obj-$(CONFIG_SUN50I_A64_CCU)	+= ccu-sun50i-a64.o
 obj-$(CONFIG_SUN5I_CCU)		+= ccu-sun5i.o
 obj-$(CONFIG_SUN6I_A31_CCU)	+= ccu-sun6i-a31.o
+obj-$(CONFIG_SUN7I_A20_CCU)	+= ccu-sun7i-a20.o
 obj-$(CONFIG_SUN8I_A23_CCU)	+= ccu-sun8i-a23.o
 obj-$(CONFIG_SUN8I_A33_CCU)	+= ccu-sun8i-a33.o
 obj-$(CONFIG_SUN8I_H3_CCU)	+= ccu-sun8i-h3.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun7i-a20.c b/drivers/clk/sunxi-ng/ccu-sun7i-a20.c
new file mode 100644
index 0000000..90d2f13
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun7i-a20.c
@@ -0,0 +1,1068 @@
+/*
+ * Copyright (c) 2017 Priit Laes. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun7i-a20.h"
+
+/*
+ * PLL1 - Core clock
+ *
+ * TODO: sigma-delta pattern bits 2 & 3
+ * TODO: PLL1 tuning register
+ */
+static struct ccu_nkmp pll_core_clk = {
+	.enable		= BIT(31),
+	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+	.k		= _SUNXI_CCU_MULT(4, 2),
+	.m		= _SUNXI_CCU_DIV(0, 2),
+	.p		= _SUNXI_CCU_DIV(16, 2),
+	.common		= {
+		.reg		= 0x000,
+		.hw.init	= CLK_HW_INIT("pll-core",
+					      "hosc",
+					      &ccu_nkmp_ops,
+					      0),
+	},
+};
+
+/* PLL2 - Audio clock */
+static struct ccu_nm pll_audio_base_clk = {
+	.enable		= BIT(31),
+	.n		= _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
+	.m		= _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
+	.common		= {
+		.reg		= 0x008,
+		.hw.init	= CLK_HW_INIT("pll-audio-base",
+					      "hosc",
+					      &ccu_nm_ops,
+					      0),
+	},
+
+};
+
+/* PLL3 - Video0 clock */
+static struct ccu_mult pll_video0_clk = {
+	.enable		= BIT(31),
+	.mult		= _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
+	.frac		= _SUNXI_CCU_FRAC(BIT(15), BIT(14),
+					  270000000, 297000000),
+	.common		= {
+		.reg		= 0x010,
+		.features	= (CCU_FEATURE_FRACTIONAL |
+				   CCU_FEATURE_ALL_PREDIV),
+		.prediv		= 8,
+		.hw.init	= CLK_HW_INIT("pll-video0",
+					      "hosc",
+					      &ccu_mult_ops,
+					      0),
+	},
+};
+
+/* PLL4 - VE clock */
+static struct ccu_nkmp pll_ve_clk = {
+	.enable		= BIT(31),
+	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+	.k		= _SUNXI_CCU_MULT(4, 2),
+	.m		= _SUNXI_CCU_DIV(0, 2),
+	.p		= _SUNXI_CCU_DIV(16, 2),
+	.common		= {
+		.reg		= 0x018,
+		.hw.init	= CLK_HW_INIT("pll-ve",
+					      "hosc",
+					      &ccu_nkmp_ops,
+					      0),
+	},
+};
+
+/*
+ * PLL5 - DDR clock
+ *
+ * TODO: PLL5 tuning register
+ */
+static struct ccu_nk pll_ddr_base_clk = {
+	.enable		= BIT(31),
+	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+	.k		= _SUNXI_CCU_MULT(4, 2),
+	.common		= {
+		.reg		= 0x020,
+		.hw.init	= CLK_HW_INIT("pll-ddr-base",
+					      "hosc",
+					      &ccu_nk_ops,
+					      0),
+	},
+};
+
+static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
+		   CLK_IS_CRITICAL);
+
+static struct ccu_div pll_ddr_other_clk = {
+	.div		= _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+	.common		= {
+		.reg		= 0x020,
+		.hw.init	= CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
+					      &ccu_div_ops,
+					      0),
+	},
+};
+
+/* PLL6 - peripheral (SATA) clock */
+static struct ccu_nk pll_periph_clk = {
+	.enable		= BIT(31),
+	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+	.k		= _SUNXI_CCU_MULT(4, 2),
+	.fixed_post_div	= 2,
+	.common		= {
+		.reg		= 0x028,
+		.features	= CCU_FEATURE_FIXED_POSTDIV,
+		.hw.init	= CLK_HW_INIT("pll-periph",
+					      "hosc",
+					      &ccu_nk_ops,
+					      0),
+	},
+};
+static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-sata", "pll-periph",
+		      0x028, BIT(14), 0);
+
+/* PLL7 - Video1 clock */
+static struct ccu_mult pll_video1_clk = {
+	.enable		= BIT(31),
+	.mult		= _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
+	.frac		= _SUNXI_CCU_FRAC(BIT(15), BIT(14),
+				  270000000, 297000000),
+	.common		= {
+		.reg		= 0x030,
+		.features	= (CCU_FEATURE_FRACTIONAL |
+				   CCU_FEATURE_ALL_PREDIV),
+		.prediv		= 8,
+		.hw.init	= CLK_HW_INIT("pll-video1",
+					      "hosc",
+					      &ccu_mult_ops,
+					      0),
+	},
+};
+
+/* TODO: pll8 gpu 0x040 */
+
+static SUNXI_CCU_GATE(hosc_clk,	"hosc",	"osc24M", 0x050, BIT(0), 0);
+
+static const char *const cpu_parents[] = { "osc32k", "hosc",
+					   "pll-core", "pll-periph" };
+static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
+	{ .index = 3, .div = 3, },
+};
+
+static struct ccu_mux cpu_clk = {
+	.mux		= {
+		.shift		= 16,
+		.width		= 2,
+		.fixed_predivs	= cpu_predivs,
+		.n_predivs	= ARRAY_SIZE(cpu_predivs),
+	},
+	.common		= {
+		.reg		= 0x054,
+		.features	= CCU_FEATURE_FIXED_PREDIV,
+		.hw.init	= CLK_HW_INIT_PARENTS("cpu",
+						      cpu_parents,
+						      &ccu_mux_ops,
+						      CLK_IS_CRITICAL),
+	}
+};
+
+static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
+
+static const char *const ahb_parents[] = { "axi", "pll-periph",
+					   "pll-periph-2x" };
+static const struct ccu_mux_fixed_prediv ahb_predivs[] = {
+	{ .index = 2, .div = 2, },
+};
+
+static struct ccu_div ahb_clk = {
+	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
+	.mux		= {
+		.shift		= 6,
+		.width		= 2,
+		.fixed_predivs	= ahb_predivs,
+		.n_predivs	= ARRAY_SIZE(ahb_predivs),
+	},
+
+	.common		= {
+		.reg		= 0x054,
+		.hw.init	= CLK_HW_INIT_PARENTS("ahb",
+						      ahb_parents,
+						      &ccu_div_ops,
+						      0),
+	},
+};
+
+static struct clk_div_table apb0_div_table[] = {
+	{ .val = 0, .div = 2 },
+	{ .val = 1, .div = 2 },
+	{ .val = 2, .div = 4 },
+	{ .val = 3, .div = 8 },
+	{ /* Sentinel */ },
+};
+static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
+			   0x054, 8, 2, apb0_div_table, 0);
+
+static const char *const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
+static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
+			     0, 5,	/* M */
+			     16, 2,	/* P */
+			     24, 2,	/* mux */
+			     0);
+
+static SUNXI_CCU_GATE(ahb_otg_clk,	"ahb-otg",	"ahb",
+		      0x060, BIT(0), 0);
+static SUNXI_CCU_GATE(ahb_ehci0_clk,	"ahb-ehci0",	"ahb",
+		      0x060, BIT(1), 0);
+static SUNXI_CCU_GATE(ahb_ohci0_clk,	"ahb-ohci0",	"ahb",
+		      0x060, BIT(2), 0);
+static SUNXI_CCU_GATE(ahb_ehci1_clk,	"ahb-ehci1",	"ahb",
+		      0x060, BIT(3), 0);
+static SUNXI_CCU_GATE(ahb_ohci1_clk,	"ahb-ohci1",	"ahb",
+		      0x060, BIT(4), 0);
+static SUNXI_CCU_GATE(ahb_ss_clk,	"ahb-ss",	"ahb",
+		      0x060, BIT(5), 0);
+static SUNXI_CCU_GATE(ahb_dma_clk,	"ahb-dma",	"ahb",
+		      0x060, BIT(6), 0);
+static SUNXI_CCU_GATE(ahb_bist_clk,	"ahb-bist",	"ahb",
+		      0x060, BIT(7), 0);
+static SUNXI_CCU_GATE(ahb_mmc0_clk,	"ahb-mmc0",	"ahb",
+		      0x060, BIT(8), 0);
+static SUNXI_CCU_GATE(ahb_mmc1_clk,	"ahb-mmc1",	"ahb",
+		      0x060, BIT(9), 0);
+static SUNXI_CCU_GATE(ahb_mmc2_clk,	"ahb-mmc2",	"ahb",
+		      0x060, BIT(10), 0);
+static SUNXI_CCU_GATE(ahb_mmc3_clk,	"ahb-mmc3",	"ahb",
+		      0x060, BIT(11), 0);
+static SUNXI_CCU_GATE(ahb_ms_clk,	"ahb-ms",	"ahb",
+		      0x060, BIT(12), 0);
+static SUNXI_CCU_GATE(ahb_nand_clk,	"ahb-nand",	"ahb",
+		      0x060, BIT(13), 0);
+static SUNXI_CCU_GATE(ahb_sdram_clk,	"ahb-sdram",	"ahb",
+		      0x060, BIT(14), CLK_IS_CRITICAL);
+/* BIT(15) - reserved */
+static SUNXI_CCU_GATE(ahb_ace_clk,	"ahb-ace",	"ahb",
+		      0x060, BIT(16), 0);
+static SUNXI_CCU_GATE(ahb_emac_clk,	"ahb-emac",	"ahb",
+		      0x060, BIT(17), 0);
+static SUNXI_CCU_GATE(ahb_ts_clk,	"ahb-ts",	"ahb",
+		      0x060, BIT(18), 0);
+/* BIT(19) - reserved */
+static SUNXI_CCU_GATE(ahb_spi0_clk,	"ahb-spi0",	"ahb",
+		      0x060, BIT(20), 0);
+static SUNXI_CCU_GATE(ahb_spi1_clk,	"ahb-spi1",	"ahb",
+		      0x060, BIT(21), 0);
+static SUNXI_CCU_GATE(ahb_spi2_clk,	"ahb-spi2",	"ahb",
+		      0x060, BIT(22), 0);
+static SUNXI_CCU_GATE(ahb_spi3_clk,	"ahb-spi3",	"ahb",
+		      0x060, BIT(23), 0);
+/* BIT(24) - reserved */
+static SUNXI_CCU_GATE(ahb_sata_clk,	"ahb-sata",	"ahb",
+		      0x060, BIT(25), 0);
+/* BIT(26 .. 27) - reserved */
+static SUNXI_CCU_GATE(ahb_hstimer_clk,	"ahb-hstimer",	"ahb",
+		      0x060, BIT(28), 0);
+/* BIT(29 .. 31) - reserved */
+
+static SUNXI_CCU_GATE(ahb_ve_clk,	"ahb-ve",	"ahb",
+		      0x064, BIT(0), 0);
+static SUNXI_CCU_GATE(ahb_tvd_clk,	"ahb-tvd",	"ahb",
+		      0x064, BIT(1), 0);
+static SUNXI_CCU_GATE(ahb_tve0_clk,	"ahb-tve0",	"ahb",
+		      0x064, BIT(2), 0);
+static SUNXI_CCU_GATE(ahb_tve1_clk,	"ahb-tve1",	"ahb",
+		      0x064, BIT(3), 0);
+static SUNXI_CCU_GATE(ahb_lcd0_clk,	"ahb-lcd0",	"ahb",
+		      0x064, BIT(4), 0);
+static SUNXI_CCU_GATE(ahb_lcd1_clk,	"ahb-lcd1",	"ahb",
+		      0x064, BIT(5), 0);
+/* BIT(6 .. 7) - reserved */
+static SUNXI_CCU_GATE(ahb_csi0_clk,	"ahb-csi0",	"ahb",
+		      0x064, BIT(8), 0);
+static SUNXI_CCU_GATE(ahb_csi1_clk,	"ahb-csi1",	"ahb",
+		      0x064, BIT(9), 0);
+static SUNXI_CCU_GATE(ahb_hdmi1_clk,	"ahb-hdmi1",	"ahb",
+		      0x064, BIT(10), 0);
+static SUNXI_CCU_GATE(ahb_hdmi0_clk,	"ahb-hdmi0",	"ahb",
+		      0x064, BIT(11), 0);
+static SUNXI_CCU_GATE(ahb_de_be0_clk,	"ahb-de-be0",	"ahb",
+		      0x064, BIT(12), 0);
+static SUNXI_CCU_GATE(ahb_de_be1_clk,	"ahb-de-be1",	"ahb",
+		      0x064, BIT(13), 0);
+static SUNXI_CCU_GATE(ahb_de_fe0_clk,	"ahb-de-fe0",	"ahb",
+		      0x064, BIT(14), 0);
+static SUNXI_CCU_GATE(ahb_de_fe1_clk,	"ahb-de-fe1",	"ahb",
+		      0x064, BIT(15), 0);
+/* BIT(16) - reserved */
+static SUNXI_CCU_GATE(ahb_gmac_clk,	"ahb-gmac",	"ahb",
+		      0x064, BIT(17), 0);
+static SUNXI_CCU_GATE(ahb_mp_clk,	"ahb-mp",	"ahb",
+		      0x064, BIT(18), 0);
+/* BIT(19) - reserved */
+static SUNXI_CCU_GATE(ahb_gpu_clk,	"ahb-gpu",	"ahb",
+		      0x064, BIT(20), 0);
+/* BIT(21 .. 31) - reserved */
+
+static SUNXI_CCU_GATE(apb0_codec_clk,	"apb0-codec",	"apb0",
+		      0x068, BIT(0), 0);
+static SUNXI_CCU_GATE(apb0_spdif_clk,	"apb0-spdif",	"apb0",
+		      0x068, BIT(1), 0);
+static SUNXI_CCU_GATE(apb0_ac97_clk,	"apb0-ac97",	"apb0",
+		      0x068, BIT(2), 0);
+static SUNXI_CCU_GATE(apb0_i2s0_clk,	"apb0-i2s0",	"apb0",
+		      0x068, BIT(3), 0);
+static SUNXI_CCU_GATE(apb0_i2s1_clk,	"apb0-i2s1",	"apb0",
+		      0x068, BIT(4), 0);
+static SUNXI_CCU_GATE(apb0_pio_clk,	"apb0-pio",	"apb0",
+		      0x068, BIT(5), 0);
+static SUNXI_CCU_GATE(apb0_ir0_clk,	"apb0-ir0",	"apb0",
+		      0x068, BIT(6), 0);
+static SUNXI_CCU_GATE(apb0_ir1_clk,	"apb0-ir1",	"apb0",
+		      0x068, BIT(7), 0);
+static SUNXI_CCU_GATE(apb0_i2s2_clk,	"apb0-i2s2",	"apb0",
+		      0x068, BIT(8), 0);
+/* BIT(8) - reserved */
+static SUNXI_CCU_GATE(apb0_keypad_clk,	"apb0-keypad",	"apb0",
+		      0x068, BIT(10), 0);
+/* BIT(11 .. 31) - reserved */
+
+static SUNXI_CCU_GATE(apb1_i2c0_clk,	"apb1-i2c0",	"apb1",
+		      0x06c, BIT(0), 0);
+static SUNXI_CCU_GATE(apb1_i2c1_clk,	"apb1-i2c1",	"apb1",
+		      0x06c, BIT(1), 0);
+static SUNXI_CCU_GATE(apb1_i2c2_clk,	"apb1-i2c2",	"apb1",
+		      0x06c, BIT(2), 0);
+static SUNXI_CCU_GATE(apb1_i2c3_clk,	"apb1-i2c3",	"apb1",
+		      0x06c, BIT(3), 0);
+static SUNXI_CCU_GATE(apb1_can_clk,	"apb1-can",	"apb1",
+		      0x06c, BIT(4), 0);
+static SUNXI_CCU_GATE(apb1_scr_clk,	"apb1-scr",	"apb1",
+		      0x06c, BIT(5), 0);
+static SUNXI_CCU_GATE(apb1_ps20_clk,	"apb1-ps20",	"apb1",
+		      0x06c, BIT(6), 0);
+static SUNXI_CCU_GATE(apb1_ps21_clk,	"apb1-ps21",	"apb1",
+		      0x06c, BIT(7), 0);
+/* BIT(8 .. 14) - reserved */
+static SUNXI_CCU_GATE(apb1_i2c4_clk,	"apb1-i2c4",	"apb1",
+		      0x06c, BIT(15), 0);
+static SUNXI_CCU_GATE(apb1_uart0_clk,	"apb1-uart0",	"apb1",
+		      0x06c, BIT(16), 0);
+static SUNXI_CCU_GATE(apb1_uart1_clk,	"apb1-uart1",	"apb1",
+		      0x06c, BIT(17), 0);
+static SUNXI_CCU_GATE(apb1_uart2_clk,	"apb1-uart2",	"apb1",
+		      0x06c, BIT(18), 0);
+static SUNXI_CCU_GATE(apb1_uart3_clk,	"apb1-uart3",	"apb1",
+		      0x06c, BIT(19), 0);
+static SUNXI_CCU_GATE(apb1_uart4_clk,	"apb1-uart4",	"apb1",
+		      0x06c, BIT(20), 0);
+static SUNXI_CCU_GATE(apb1_uart5_clk,	"apb1-uart5",	"apb1",
+		      0x06c, BIT(21), 0);
+static SUNXI_CCU_GATE(apb1_uart6_clk,	"apb1-uart6",	"apb1",
+		      0x06c, BIT(22), 0);
+static SUNXI_CCU_GATE(apb1_uart7_clk,	"apb1-uart7",	"apb1",
+		      0x06c, BIT(23), 0);
+/* BIT(24 .. 31) - reserved */
+
+static const char *const mod0_default_parents[] = { "hosc", "pll-periph",
+						     "pll-ddr-other" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(ms_clk, "ms", mod0_default_parents, 0x084,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
+		       0x088, 8, 3, 0);
+static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
+		       0x088, 20, 3, 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
+		       0x08c, 8, 3, 0);
+static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
+		       0x08c, 20, 3, 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
+		       0x090, 8, 3, 0);
+static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
+		       0x090, 20, 3, 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
+		       0x094, 8, 3, 0);
+static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
+		       0x094, 20, 3, 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(pata_clk, "pata", mod0_default_parents, 0x0ac,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static const char *const ir_parents[] = { "hosc", "pll-periph",
+					  "pll-ddr-other", "osc32k" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0b0,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0b4,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static const char *const audio_parents[] = { "pll-audio-8x", "pll-audio-4x",
+					      "pll-audio-2x", "pll-audio" };
+static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", audio_parents,
+			       0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", audio_parents,
+			       0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", audio_parents,
+			       0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+/* TODO: keypad clock, 0x0c4 parents: 00: hosc, 10: osc32k */
+
+/*
+ * TODO: SATA clock also supports external clock as parent.
+ * Currently we default to using PLL6 SATA gate.
+ */
+static SUNXI_CCU_GATE(sata_clk, "sata", "pll-periph-sata",
+		      0x0c8, BIT(31), 0);
+
+static SUNXI_CCU_GATE(usb_ohci0_clk,	"usb-ohci0",	"pll-periph",
+		      0x0cc, BIT(6), 0);
+static SUNXI_CCU_GATE(usb_ohci1_clk,	"usb-ohci1",	"pll-periph",
+		      0x0cc, BIT(7), 0);
+static SUNXI_CCU_GATE(usb_phy_clk,	"usb-phy",	"pll-periph",
+		      0x0cc, BIT(8), 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0d4,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", audio_parents,
+			       0x0d8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", audio_parents,
+			       0x0dc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"pll-ddr",
+		      0x100, BIT(0), 0);
+static SUNXI_CCU_GATE(dram_csi0_clk,	"dram-csi0",	"pll-ddr",
+		      0x100, BIT(1), 0);
+static SUNXI_CCU_GATE(dram_csi1_clk,	"dram-csi1",	"pll-ddr",
+		      0x100, BIT(2), 0);
+static SUNXI_CCU_GATE(dram_ts_clk,	"dram-ts",	"pll-ddr",
+		      0x100, BIT(3), 0);
+static SUNXI_CCU_GATE(dram_tvd_clk,	"dram-tvd",	"pll-ddr",
+		      0x100, BIT(4), 0);
+static SUNXI_CCU_GATE(dram_tve0_clk,	"dram-tve0",	"pll-ddr",
+		      0x100, BIT(5), 0);
+static SUNXI_CCU_GATE(dram_tve1_clk,	"dram-tve1",	"pll-ddr",
+		      0x100, BIT(6), 0);
+/* BIT(7 .. 14) - reserved */
+static SUNXI_CCU_GATE(dram_out_clk,	"dram-out",	"pll-ddr",
+		      0x100, BIT(15), 0);
+/* BIT(16 .. 23) - reserved */
+static SUNXI_CCU_GATE(dram_de_fe1_clk,	"dram-de-fe1",	"pll-ddr",
+		      0x100, BIT(24), 0);
+static SUNXI_CCU_GATE(dram_de_fe0_clk,	"dram-de-fe0",	"pll-ddr",
+		      0x100, BIT(25), 0);
+static SUNXI_CCU_GATE(dram_de_be0_clk,	"dram-de-be0",	"pll-ddr",
+		      0x100, BIT(26), 0);
+static SUNXI_CCU_GATE(dram_de_be1_clk,	"dram-de-be1",	"pll-ddr",
+		      0x100, BIT(27), 0);
+static SUNXI_CCU_GATE(dram_mp_clk,	"dram-mp",	"pll-ddr",
+		      0x100, BIT(28), 0);
+static SUNXI_CCU_GATE(dram_ace_clk,	"dram-ace",	"pll-ddr",
+		      0x100, BIT(29), 0);
+/* BIT(30 .. 31) - reserved */
+
+static const char *const de_parents[] = { "pll-video0", "pll-video1",
+					   "pll-ddr-other" };
+static SUNXI_CCU_M_WITH_MUX_GATE(de_be0_clk, "de-be0", de_parents,
+				 0x104, 0, 4, 24, 2, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(de_be1_clk, "de-be1", de_parents,
+				 0x108, 0, 4, 24, 2, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(de_fe0_clk, "de-fe0", de_parents,
+				 0x10c, 0, 4, 24, 2, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(de_fe1_clk, "de-fe1", de_parents,
+				 0x110, 0, 4, 24, 2, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(de_mp_clk, "de-mp", de_parents,
+				 0x114, 0, 4, 24, 2, BIT(31), 0);
+
+static const char *const tcon_parents[] = { "pll-video0", "pll-video1",
+					    "pll-video0-2x", "pll-video1-2x" };
+static SUNXI_CCU_MUX_WITH_GATE(tcon0_ch0_clk, "tcon0-ch0-sclk", tcon_parents,
+			       0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_MUX_WITH_GATE(tcon1_ch0_clk, "tcon1-ch0-sclk", tcon_parents,
+			       0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+/* TODO: CSI special clock register - 0x120 */
+/* TODO: TVD clock register - 0x128 */
+
+static SUNXI_CCU_M_WITH_MUX_GATE(tcon0_ch1_sclk2_clk, "tcon0-ch1-sclk2",
+				 tcon_parents,
+				 0x12c, 0, 4, 24, 2, BIT(31),
+				 CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_M_WITH_GATE(tcon0_ch1_clk,
+			     "tcon0-ch1-sclk1", "tcon0-ch1-sclk2",
+			     0x12c, 11, 1, BIT(15),
+			     CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_ch1_sclk2_clk, "tcon1-ch1-sclk2",
+				 tcon_parents,
+				 0x130, 0, 4, 24, 2, BIT(31),
+				 CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_M_WITH_GATE(tcon1_ch1_clk,
+			     "tcon1-ch1-sclk1", "tcon1-ch1-sclk2",
+			     0x130, 11, 1, BIT(15),
+			     CLK_SET_RATE_PARENT);
+
+/* TODO: CSI0 clock - 0x134 */
+/* TODO: CSI1 clock - 0x138 */
+static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
+			     0x13c, 16, 8, BIT(31), 0);
+
+static SUNXI_CCU_GATE(codec_clk,	"codec",	"pll-audio",
+		      0x140, BIT(31), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_GATE(avs_clk,		"avs",		"hosc",
+		      0x144, BIT(31), 0);
+/* TODO: ACE clock - 0x148 */
+/* TODO: HDMI clock - 0x150 */
+/* TODO: GPU clock - 0x154 */
+
+static const char *const mbus_parents[] = { "hosc", "pll-periph-2x",
+					    "pll-ddr-other" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
+				  0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
+				  CLK_IS_CRITICAL);
+
+/* TODO: HDMI1 slow clock 0x178 */
+/* TODO: REPEAT clock 0x17c */
+static const char *const out_parents[] = { "hosc", "osc32k", "hosc" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(out_a_clk, "out-a", out_parents,
+				  0x1f0, 8, 5, 20, 2, 24, 2, BIT(31), 0);
+static SUNXI_CCU_MP_WITH_MUX_GATE(out_b_clk, "out-b", out_parents,
+				  0x1f4, 8, 5, 20, 2, 24, 2, BIT(31), 0);
+
+static struct ccu_common *sun7i_a20_ccu_clks[] = {
+	&hosc_clk.common,
+	&pll_core_clk.common,
+	&pll_audio_base_clk.common,
+	&pll_video0_clk.common,
+	&pll_ve_clk.common,
+	&pll_ddr_base_clk.common,
+	&pll_ddr_clk.common,
+	&pll_ddr_other_clk.common,
+	&pll_periph_clk.common,
+	&pll_periph_sata_clk.common,
+	&pll_video1_clk.common,
+	&cpu_clk.common,
+	&axi_clk.common,
+	&ahb_clk.common,
+	&apb0_clk.common,
+	&apb1_clk.common,
+	&ahb_otg_clk.common,
+	&ahb_ehci0_clk.common,
+	&ahb_ohci0_clk.common,
+	&ahb_ehci1_clk.common,
+	&ahb_ohci1_clk.common,
+	&ahb_ss_clk.common,
+	&ahb_dma_clk.common,
+	&ahb_bist_clk.common,
+	&ahb_mmc0_clk.common,
+	&ahb_mmc1_clk.common,
+	&ahb_mmc2_clk.common,
+	&ahb_mmc3_clk.common,
+	&ahb_ms_clk.common,
+	&ahb_nand_clk.common,
+	&ahb_sdram_clk.common,
+	&ahb_ace_clk.common,
+	&ahb_emac_clk.common,
+	&ahb_ts_clk.common,
+	&ahb_spi0_clk.common,
+	&ahb_spi1_clk.common,
+	&ahb_spi2_clk.common,
+	&ahb_spi3_clk.common,
+	&ahb_sata_clk.common,
+	&ahb_hstimer_clk.common,
+	&ahb_ve_clk.common,
+	&ahb_tvd_clk.common,
+	&ahb_tve0_clk.common,
+	&ahb_tve1_clk.common,
+	&ahb_lcd0_clk.common,
+	&ahb_lcd1_clk.common,
+	&ahb_csi0_clk.common,
+	&ahb_csi1_clk.common,
+	&ahb_hdmi1_clk.common,
+	&ahb_hdmi0_clk.common,
+	&ahb_de_be0_clk.common,
+	&ahb_de_be1_clk.common,
+	&ahb_de_fe0_clk.common,
+	&ahb_de_fe1_clk.common,
+	&ahb_gmac_clk.common,
+	&ahb_mp_clk.common,
+	&ahb_gpu_clk.common,
+	&apb0_codec_clk.common,
+	&apb0_spdif_clk.common,
+	&apb0_ac97_clk.common,
+	&apb0_i2s0_clk.common,
+	&apb0_i2s1_clk.common,
+	&apb0_pio_clk.common,
+	&apb0_ir0_clk.common,
+	&apb0_ir1_clk.common,
+	&apb0_i2s2_clk.common,
+	&apb0_keypad_clk.common,
+	&apb1_i2c0_clk.common,
+	&apb1_i2c1_clk.common,
+	&apb1_i2c2_clk.common,
+	&apb1_i2c3_clk.common,
+	&apb1_can_clk.common,
+	&apb1_scr_clk.common,
+	&apb1_ps20_clk.common,
+	&apb1_ps21_clk.common,
+	&apb1_i2c4_clk.common,
+	&apb1_uart0_clk.common,
+	&apb1_uart1_clk.common,
+	&apb1_uart2_clk.common,
+	&apb1_uart3_clk.common,
+	&apb1_uart4_clk.common,
+	&apb1_uart5_clk.common,
+	&apb1_uart6_clk.common,
+	&apb1_uart7_clk.common,
+	&nand_clk.common,
+	&ms_clk.common,
+	&mmc0_clk.common,
+	&mmc0_output_clk.common,
+	&mmc0_sample_clk.common,
+	&mmc1_clk.common,
+	&mmc1_output_clk.common,
+	&mmc1_sample_clk.common,
+	&mmc2_clk.common,
+	&mmc2_output_clk.common,
+	&mmc2_sample_clk.common,
+	&mmc3_clk.common,
+	&mmc3_output_clk.common,
+	&mmc3_sample_clk.common,
+	&ts_clk.common,
+	&ss_clk.common,
+	&spi0_clk.common,
+	&spi1_clk.common,
+	&spi2_clk.common,
+	&pata_clk.common,
+	&ir0_clk.common,
+	&ir1_clk.common,
+	&i2s0_clk.common,
+	&ac97_clk.common,
+	&spdif_clk.common,
+//	&keypad_clk.common,
+	&sata_clk.common,
+	&usb_ohci0_clk.common,
+	&usb_ohci1_clk.common,
+	&usb_phy_clk.common,
+	&spi3_clk.common,
+	&i2s1_clk.common,
+	&i2s2_clk.common,
+	&dram_ve_clk.common,
+	&dram_csi0_clk.common,
+	&dram_csi1_clk.common,
+	&dram_ts_clk.common,
+	&dram_tvd_clk.common,
+	&dram_tve0_clk.common,
+	&dram_tve1_clk.common,
+	&dram_out_clk.common,
+	&dram_de_fe1_clk.common,
+	&dram_de_fe0_clk.common,
+	&dram_de_be0_clk.common,
+	&dram_de_be1_clk.common,
+	&dram_mp_clk.common,
+	&dram_ace_clk.common,
+	&de_be0_clk.common,
+	&de_be1_clk.common,
+	&de_fe0_clk.common,
+	&de_fe1_clk.common,
+	&de_mp_clk.common,
+	&tcon0_ch0_clk.common,
+	&tcon1_ch0_clk.common,
+//	&csi_special_clk.common,
+//	&tvd_clk.common,
+	&tcon0_ch1_sclk2_clk.common,
+	&tcon0_ch1_clk.common,
+	&tcon1_ch1_sclk2_clk.common,
+	&tcon1_ch1_clk.common,
+//	&csi0_clk.common,
+//	&csi1_clk.common,
+	&ve_clk.common,
+	&codec_clk.common,
+	&avs_clk.common,
+//	&ace_clk.common,
+//	&hdmi_clk.common,
+//	&gpu_clk.common,
+	&mbus_clk.common,
+//	&hdmi1_slow_clk.common,
+//	&hdmi1_repeat_clk.common,
+	&out_a_clk.common,
+	&out_b_clk.common
+};
+
+static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
+			"pll-periph", 1, 2, CLK_SET_RATE_PARENT);
+/* We hardcode the divider to 4 for now */
+static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
+			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
+			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
+			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
+			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
+			"pll-video0", 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
+			"pll-video1", 1, 2, CLK_SET_RATE_PARENT);
+
+
+static struct clk_hw_onecell_data sun7i_a20_hw_clks = {
+	.hws	= {
+		[CLK_HOSC]		= &hosc_clk.common.hw,
+		[CLK_PLL_CORE]		= &pll_core_clk.common.hw,
+		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
+		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
+		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
+		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
+		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
+		[CLK_PLL_VIDEO0]	= &pll_video0_clk.common.hw,
+		[CLK_PLL_VIDEO0_2X]	= &pll_video0_2x_clk.hw,
+		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
+		[CLK_PLL_DDR_BASE]	= &pll_ddr_base_clk.common.hw,
+		[CLK_PLL_DDR]		= &pll_ddr_clk.common.hw,
+		[CLK_PLL_DDR_OTHER]	= &pll_ddr_other_clk.common.hw,
+		[CLK_PLL_PERIPH]	= &pll_periph_clk.common.hw,
+		[CLK_PLL_PERIPH_2X]	= &pll_periph_2x_clk.hw,
+		[CLK_PLL_PERIPH_SATA]	= &pll_periph_sata_clk.common.hw,
+		[CLK_PLL_VIDEO1]	= &pll_video1_clk.common.hw,
+		[CLK_PLL_VIDEO1_2X]	= &pll_video1_2x_clk.hw,
+		[CLK_CPU]		= &cpu_clk.common.hw,
+		[CLK_AXI]		= &axi_clk.common.hw,
+		[CLK_AHB]		= &ahb_clk.common.hw,
+		[CLK_APB0]		= &apb0_clk.common.hw,
+		[CLK_APB1]		= &apb1_clk.common.hw,
+		[CLK_AHB_OTG]		= &ahb_otg_clk.common.hw,
+		[CLK_AHB_EHCI0]		= &ahb_ehci0_clk.common.hw,
+		[CLK_AHB_OHCI0]		= &ahb_ohci0_clk.common.hw,
+		[CLK_AHB_EHCI1]		= &ahb_ehci1_clk.common.hw,
+		[CLK_AHB_OHCI1]		= &ahb_ohci1_clk.common.hw,
+		[CLK_AHB_SS]		= &ahb_ss_clk.common.hw,
+		[CLK_AHB_DMA]		= &ahb_dma_clk.common.hw,
+		[CLK_AHB_BIST]		= &ahb_bist_clk.common.hw,
+		[CLK_AHB_MMC0]		= &ahb_mmc0_clk.common.hw,
+		[CLK_AHB_MMC1]		= &ahb_mmc1_clk.common.hw,
+		[CLK_AHB_MMC2]		= &ahb_mmc2_clk.common.hw,
+		[CLK_AHB_MMC3]		= &ahb_mmc3_clk.common.hw,
+		[CLK_AHB_MS]		= &ahb_ms_clk.common.hw,
+		[CLK_AHB_NAND]		= &ahb_nand_clk.common.hw,
+		[CLK_AHB_SDRAM]		= &ahb_sdram_clk.common.hw,
+		[CLK_AHB_ACE]		= &ahb_ace_clk.common.hw,
+		[CLK_AHB_EMAC]		= &ahb_emac_clk.common.hw,
+		[CLK_AHB_TS]		= &ahb_ts_clk.common.hw,
+		[CLK_AHB_SPI0]		= &ahb_spi0_clk.common.hw,
+		[CLK_AHB_SPI1]		= &ahb_spi1_clk.common.hw,
+		[CLK_AHB_SPI2]		= &ahb_spi2_clk.common.hw,
+		[CLK_AHB_SPI3]		= &ahb_spi3_clk.common.hw,
+		[CLK_AHB_SATA]		= &ahb_sata_clk.common.hw,
+		[CLK_AHB_HSTIMER]	= &ahb_hstimer_clk.common.hw,
+		[CLK_AHB_VE]		= &ahb_ve_clk.common.hw,
+		[CLK_AHB_TVD]		= &ahb_tvd_clk.common.hw,
+		[CLK_AHB_TVE0]		= &ahb_tve0_clk.common.hw,
+		[CLK_AHB_TVE1]		= &ahb_tve1_clk.common.hw,
+		[CLK_AHB_LCD0]		= &ahb_lcd0_clk.common.hw,
+		[CLK_AHB_LCD1]		= &ahb_lcd1_clk.common.hw,
+		[CLK_AHB_CSI0]		= &ahb_csi0_clk.common.hw,
+		[CLK_AHB_CSI1]		= &ahb_csi1_clk.common.hw,
+		[CLK_AHB_HDMI1]		= &ahb_hdmi1_clk.common.hw,
+		[CLK_AHB_HDMI0]		= &ahb_hdmi0_clk.common.hw,
+		[CLK_AHB_DE_BE0]	= &ahb_de_be0_clk.common.hw,
+		[CLK_AHB_DE_BE1]	= &ahb_de_be1_clk.common.hw,
+		[CLK_AHB_DE_FE0]	= &ahb_de_fe0_clk.common.hw,
+		[CLK_AHB_DE_FE1]	= &ahb_de_fe1_clk.common.hw,
+		[CLK_AHB_GMAC]		= &ahb_gmac_clk.common.hw,
+		[CLK_AHB_MP]		= &ahb_mp_clk.common.hw,
+		[CLK_AHB_GPU]		= &ahb_gpu_clk.common.hw,
+		[CLK_APB0_CODEC]	= &apb0_codec_clk.common.hw,
+		[CLK_APB0_SPDIF]	= &apb0_spdif_clk.common.hw,
+		[CLK_APB0_AC97]		= &apb0_ac97_clk.common.hw,
+		[CLK_APB0_I2S0]		= &apb0_i2s0_clk.common.hw,
+		[CLK_APB0_I2S1]		= &apb0_i2s1_clk.common.hw,
+		[CLK_APB0_PIO]		= &apb0_pio_clk.common.hw,
+		[CLK_APB0_IR0]		= &apb0_ir0_clk.common.hw,
+		[CLK_APB0_IR1]		= &apb0_ir1_clk.common.hw,
+		[CLK_APB0_I2S2]		= &apb0_i2s2_clk.common.hw,
+		[CLK_APB0_KEYPAD]	= &apb0_keypad_clk.common.hw,
+		[CLK_APB1_I2C0]		= &apb1_i2c0_clk.common.hw,
+		[CLK_APB1_I2C1]		= &apb1_i2c1_clk.common.hw,
+		[CLK_APB1_I2C2]		= &apb1_i2c2_clk.common.hw,
+		[CLK_APB1_I2C3]		= &apb1_i2c3_clk.common.hw,
+		[CLK_APB1_CAN]		= &apb1_can_clk.common.hw,
+		[CLK_APB1_SCR]		= &apb1_scr_clk.common.hw,
+		[CLK_APB1_PS20]		= &apb1_ps20_clk.common.hw,
+		[CLK_APB1_PS21]		= &apb1_ps21_clk.common.hw,
+		[CLK_APB1_I2C4]		= &apb1_i2c4_clk.common.hw,
+		[CLK_APB1_UART0]	= &apb1_uart0_clk.common.hw,
+		[CLK_APB1_UART1]	= &apb1_uart1_clk.common.hw,
+		[CLK_APB1_UART2]	= &apb1_uart2_clk.common.hw,
+		[CLK_APB1_UART3]	= &apb1_uart3_clk.common.hw,
+		[CLK_APB1_UART4]	= &apb1_uart4_clk.common.hw,
+		[CLK_APB1_UART5]	= &apb1_uart5_clk.common.hw,
+		[CLK_APB1_UART6]	= &apb1_uart6_clk.common.hw,
+		[CLK_APB1_UART7]	= &apb1_uart7_clk.common.hw,
+		[CLK_NAND]		= &nand_clk.common.hw,
+		[CLK_MS]		= &ms_clk.common.hw,
+		[CLK_MMC0]		= &mmc0_clk.common.hw,
+		[CLK_MMC0_OUTPUT]	= &mmc0_output_clk.common.hw,
+		[CLK_MMC0_SAMPLE]	= &mmc0_sample_clk.common.hw,
+		[CLK_MMC1]		= &mmc1_clk.common.hw,
+		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
+		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
+		[CLK_MMC2]		= &mmc2_clk.common.hw,
+		[CLK_MMC2_OUTPUT]	= &mmc2_output_clk.common.hw,
+		[CLK_MMC2_SAMPLE]	= &mmc2_sample_clk.common.hw,
+		[CLK_MMC3]		= &mmc3_clk.common.hw,
+		[CLK_MMC3_OUTPUT]	= &mmc3_output_clk.common.hw,
+		[CLK_MMC3_SAMPLE]	= &mmc3_sample_clk.common.hw,
+		[CLK_TS]		= &ts_clk.common.hw,
+		[CLK_SS]		= &ss_clk.common.hw,
+		[CLK_SPI0]		= &spi0_clk.common.hw,
+		[CLK_SPI1]		= &spi1_clk.common.hw,
+		[CLK_SPI2]		= &spi2_clk.common.hw,
+		[CLK_PATA]		= &pata_clk.common.hw,
+		[CLK_IR0]		= &ir0_clk.common.hw,
+		[CLK_IR1]		= &ir1_clk.common.hw,
+		[CLK_I2S0]		= &i2s0_clk.common.hw,
+		[CLK_AC97]		= &ac97_clk.common.hw,
+		[CLK_SPDIF]		= &spdif_clk.common.hw,
+//		[CLK_KEYPAD]		= &keypad_clk.common.hw,
+		[CLK_SATA]		= &sata_clk.common.hw,
+		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
+		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,
+		[CLK_USB_PHY]		= &usb_phy_clk.common.hw,
+		[CLK_SPI3]		= &spi3_clk.common.hw,
+		[CLK_I2S1]		= &i2s1_clk.common.hw,
+		[CLK_I2S2]		= &i2s2_clk.common.hw,
+		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
+		[CLK_DRAM_CSI0]		= &dram_csi0_clk.common.hw,
+		[CLK_DRAM_CSI1]		= &dram_csi1_clk.common.hw,
+		[CLK_DRAM_TS]		= &dram_ts_clk.common.hw,
+		[CLK_DRAM_TVD]		= &dram_tvd_clk.common.hw,
+		[CLK_DRAM_TVE0]		= &dram_tve0_clk.common.hw,
+		[CLK_DRAM_TVE1]		= &dram_tve1_clk.common.hw,
+		[CLK_DRAM_OUT]		= &dram_out_clk.common.hw,
+		[CLK_DRAM_DE_FE1]	= &dram_de_fe1_clk.common.hw,
+		[CLK_DRAM_DE_FE0]	= &dram_de_fe0_clk.common.hw,
+		[CLK_DRAM_DE_BE0]	= &dram_de_be0_clk.common.hw,
+		[CLK_DRAM_DE_BE1]	= &dram_de_be1_clk.common.hw,
+		[CLK_DRAM_MP]		= &dram_mp_clk.common.hw,
+		[CLK_DRAM_ACE]		= &dram_ace_clk.common.hw,
+		[CLK_DE_BE0]		= &de_be0_clk.common.hw,
+		[CLK_DE_BE1]		= &de_be1_clk.common.hw,
+		[CLK_DE_FE0]		= &de_fe0_clk.common.hw,
+		[CLK_DE_FE1]		= &de_fe1_clk.common.hw,
+		[CLK_DE_MP]		= &de_mp_clk.common.hw,
+		[CLK_TCON0_CH0]		= &tcon0_ch0_clk.common.hw,
+		[CLK_TCON1_CH0]		= &tcon1_ch0_clk.common.hw,
+//		[CLK_CSI_SPECIAL]	= &csi_special_clk.common.hw,
+//		[CLK_TVD]		= &tvd_clk.common.hw,
+		[CLK_TCON0_CH1_SCLK2]	= &tcon0_ch1_sclk2_clk.common.hw,
+		[CLK_TCON0_CH1]		= &tcon0_ch1_clk.common.hw,
+		[CLK_TCON1_CH1_SCLK2]	= &tcon1_ch1_sclk2_clk.common.hw,
+		[CLK_TCON1_CH1]		= &tcon1_ch1_clk.common.hw,
+//		[CLK_CSI0]		= &csi0_clk.common.hw,
+//		[CLK_CSI1]		= &csi1_clk.common.hw,
+		[CLK_VE]		= &ve_clk.common.hw,
+		[CLK_CODEC]		= &codec_clk.common.hw,
+		[CLK_AVS]		= &avs_clk.common.hw,
+//		[CLK_ACE]		= &ace_clk.common.hw,
+//		[CLK_HDMI]		= &hdmi_clk.common.hw,
+//		[CLK_GPU]		= &gpu_clk.common.hw,
+		[CLK_MBUS]		= &mbus_clk.common.hw,
+//		[CLK_HDMI1_SLOW]	= &hdmi1_slow_clk.common.hw,
+//		[CLK_HDMI1_REPEAT]	= &hdmi1_repeat_clk.common.hw,
+		[CLK_OUT_A]		= &out_a_clk.common.hw,
+		[CLK_OUT_B]		= &out_b_clk.common.hw,
+	},
+	.num	= CLK_NUMBER,
+};
+
+static struct ccu_reset_map sun7i_a20_ccu_resets[] = {
+
+	[RST_USB_PHY0]		= { 0x0cc, BIT(0) },
+	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
+	[RST_USB_PHY2]		= { 0x0cc, BIT(2) },
+	[RST_DE_BE0]		= { 0x104, BIT(30) },
+	[RST_DE_BE1]		= { 0x108, BIT(30) },
+	[RST_DE_FE0]		= { 0x10c, BIT(30) },
+	[RST_DE_FE1]		= { 0x110, BIT(30) },
+	[RST_DE_MP]		= { 0x114, BIT(30) },
+	[RST_TCON0]		= { 0x118, BIT(30) },
+	[RST_TCON1]		= { 0x11c, BIT(30) },
+	[RST_CSI0]		= { 0x134, BIT(30) },
+	[RST_CSI1]		= { 0x138, BIT(30) },
+	[RST_VE]		= { 0x13c, BIT(0) },
+	[RST_ACE]		= { 0x148, BIT(16) },
+	[RST_LVDS]		= { 0x14c, BIT(0) },
+	[RST_GPU]		= { 0x154, BIT(30) },
+	[RST_HDMI_H]		= { 0x170, BIT(0) },
+	[RST_HDMI_SYS]		= { 0x170, BIT(1) },
+	[RST_HDMI_AUDIO_DMA]	= { 0x170, BIT(2) },
+};
+
+static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {
+	.ccu_clks	= sun7i_a20_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun7i_a20_ccu_clks),
+
+	.hw_clks	= &sun7i_a20_hw_clks,
+
+	.resets		= sun7i_a20_ccu_resets,
+	.num_resets	= ARRAY_SIZE(sun7i_a20_ccu_resets),
+};
+
+static void __init sun7i_a20_ccu_setup(struct device_node *node)
+{
+	void __iomem *reg;
+	u32 val;
+
+	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+	if (IS_ERR(reg)) {
+		pr_err("%s: Could not map the clock registers\n",
+		       of_node_full_name(node));
+		return;
+	}
+
+	#define SUN7I_PLL_AUDIO_REG	0x008
+
+	/* Force the PLL-Audio-1x divider to 4 */
+	val = readl(reg + SUN7I_PLL_AUDIO_REG);
+	val &= ~GENMASK(19, 16);
+	writel(val | (3 << 16), reg + SUN7I_PLL_AUDIO_REG);
+
+	/*
+	 * Use PLL6 as parent for AHB
+	 * CPU/AXI clock changes rate when cpufreq is enabled
+	 */
+	#define SUN7I_AHB_REG		0x054
+	val = readl(reg + SUN7I_AHB_REG);
+	val &= ~GENMASK(7, 6);
+	writel(val | (2 << 6), reg + SUN7I_AHB_REG);
+
+	sunxi_ccu_probe(node, reg, &sun7i_a20_ccu_desc);
+}
+CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu",
+	       sun7i_a20_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun7i-a20.h b/drivers/clk/sunxi-ng/ccu-sun7i-a20.h
new file mode 100644
index 0000000..bf05ca7
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun7i-a20.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2017 Priit Laes
+ *
+ * Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CCU_SUN7I_A20_H_
+#define _CCU_SUN7I_A20_H_
+
+#include <dt-bindings/clock/sun7i-ccu.h>
+#include <dt-bindings/reset/sun7i-ccu.h>
+
+/* The HOSC is exported */
+#define CLK_PLL_CORE		2
+#define CLK_PLL_AUDIO_BASE	3
+#define CLK_PLL_AUDIO		4
+#define CLK_PLL_AUDIO_2X	5
+#define CLK_PLL_AUDIO_4X	6
+#define CLK_PLL_AUDIO_8X	7
+#define CLK_PLL_VIDEO0		8
+#define CLK_PLL_VIDEO0_2X	9
+#define CLK_PLL_VE		10
+#define CLK_PLL_DDR_BASE	11
+#define CLK_PLL_DDR		12
+#define CLK_PLL_DDR_OTHER	13
+#define CLK_PLL_PERIPH		14
+#define CLK_PLL_PERIPH_2X	15
+#define CLK_PLL_VIDEO1		17
+#define CLK_PLL_VIDEO1_2X	18
+
+/* The CPU clock is exported */
+#define CLK_AXI			20
+#define CLK_AHB			21
+#define CLK_APB0		22
+#define CLK_APB1		23
+
+/* Some AHB gates are exported */
+#define CLK_AHB_BIST		31
+#define CLK_AHB_MS		36
+#define CLK_AHB_SDRAM		38
+#define CLK_AHB_ACE		39
+#define CLK_AHB_TS		41
+#define CLK_AHB_VE		48
+#define CLK_AHB_TVD		49
+#define CLK_AHB_TVE1		51
+#define CLK_AHB_LCD1		53
+#define CLK_AHB_CSI0		54
+#define CLK_AHB_CSI1		55
+#define CLK_AHB_HDMI0		56
+#define CLK_AHB_DE_BE1		59
+#define CLK_AHB_DE_FE0		60
+#define CLK_AHB_DE_FE1		61
+#define CLK_AHB_MP		63
+#define CLK_AHB_GPU		64
+
+/* Some APB0 gates are exported */
+#define CLK_APB0_AC97		67
+#define CLK_APB0_KEYPAD		74
+
+/* Some APB1 gates are exported */
+#define CLK_APB1_CAN		79
+#define CLK_APB1_SCR		80
+
+/* Some IP module clocks are exported */
+#define CLK_MS			93
+#define CLK_TS			106
+#define CLK_PATA		111
+#define CLK_AC97		115
+#define CLK_KEYPAD		117
+#define CLK_SATA		118
+
+/* Some DRAM gates are exported */
+#define CLK_DRAM_VE		125
+#define CLK_DRAM_CSI0		126
+#define CLK_DRAM_CSI1		127
+#define CLK_DRAM_TS		128
+#define CLK_DRAM_TVD		129
+#define CLK_DRAM_TVE1		131
+#define CLK_DRAM_OUT		132
+#define CLK_DRAM_DE_FE1		133
+#define CLK_DRAM_DE_FE0		134
+#define CLK_DRAM_DE_BE1		136
+#define CLK_DRAM_MP		137
+#define CLK_DRAM_ACE		138
+
+#define CLK_DE_BE1		140
+#define CLK_DE_FE0		141
+#define CLK_DE_FE1		142
+#define CLK_DE_MP		143
+#define CLK_TCON1_CH0		145
+#define CLK_CSI_SPECIAL		146
+#define CLK_TVD			147
+#define CLK_TCON0_CH1_SCLK2	148
+#define CLK_TCON1_CH1_SCLK2	150
+#define CLK_TCON1_CH1		151
+#define CLK_CSI0		152
+#define CLK_CSI1		153
+#define CLK_VE			154
+#define CLK_AVS			156
+#define CLK_ACE			157
+#define CLK_HDMI		158
+#define CLK_GPU			159
+#define CLK_MBUS		160
+#define CLK_HDMI1_SLOW		161
+#define CLK_HDMI1_REPEAT	162
+#define CLK_OUT_A		163
+#define CLK_OUT_B		164
+
+#define CLK_NUMBER		(CLK_OUT_B + 1)
+
+#endif /* _CCU_SUN7I_A20_H_ */
-- 
2.9.3

Re: [PATCH 2/4] clk: sunxi-ng: Add sun7i-a20 CCU driver

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 9554 bytes --]

Hi,

On Mon, Feb 27, 2017 at 11:09:12PM +0200, Priit Laes wrote:
> Introduce a clock controller driver for sun7i A20 SoC.
> 
> Signed-off-by: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
> ---
>  drivers/clk/sunxi-ng/Kconfig         |   11 +
>  drivers/clk/sunxi-ng/Makefile        |    1 +
>  drivers/clk/sunxi-ng/ccu-sun7i-a20.c | 1068 ++++++++++++++++++++++++++++++++++
>  drivers/clk/sunxi-ng/ccu-sun7i-a20.h |  121 ++++
>  4 files changed, 1201 insertions(+)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun7i-a20.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun7i-a20.h
> 
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index 695bbf9..4f436ab 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -85,6 +85,17 @@ config SUN6I_A31_CCU
>  	select SUNXI_CCU_PHASE
>  	default MACH_SUN6I
>  
> +config SUN7I_A20_CCU
> +	bool "Support for the Allwinner A20 CCU"
> +	select SUNXI_CCU_DIV
> +	select SUNXI_CCU_MULT
> +	select SUNXI_CCU_NK
> +	select SUNXI_CCU_NKM
> +	select SUNXI_CCU_NM
> +	select SUNXI_CCU_MP
> +	select SUNXI_CCU_PHASE
> +	default MACH_SUN7I
> +
>  config SUN8I_A23_CCU
>  	bool "Support for the Allwinner A23 CCU"
>  	select SUNXI_CCU_DIV
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 6feaac0..bedda5b 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -21,6 +21,7 @@ obj-$(CONFIG_SUNXI_CCU_MP)	+= ccu_mp.o
>  obj-$(CONFIG_SUN50I_A64_CCU)	+= ccu-sun50i-a64.o
>  obj-$(CONFIG_SUN5I_CCU)		+= ccu-sun5i.o
>  obj-$(CONFIG_SUN6I_A31_CCU)	+= ccu-sun6i-a31.o
> +obj-$(CONFIG_SUN7I_A20_CCU)	+= ccu-sun7i-a20.o
>  obj-$(CONFIG_SUN8I_A23_CCU)	+= ccu-sun8i-a23.o
>  obj-$(CONFIG_SUN8I_A33_CCU)	+= ccu-sun8i-a33.o
>  obj-$(CONFIG_SUN8I_H3_CCU)	+= ccu-sun8i-h3.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun7i-a20.c b/drivers/clk/sunxi-ng/ccu-sun7i-a20.c
> new file mode 100644
> index 0000000..90d2f13
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun7i-a20.c
> @@ -0,0 +1,1068 @@
> +/*
> + * Copyright (c) 2017 Priit Laes. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +#include "ccu_mult.h"
> +#include "ccu_nk.h"
> +#include "ccu_nkm.h"
> +#include "ccu_nkmp.h"
> +#include "ccu_nm.h"
> +#include "ccu_phase.h"
> +
> +#include "ccu-sun7i-a20.h"
> +
> +/*
> + * PLL1 - Core clock
> + *
> + * TODO: sigma-delta pattern bits 2 & 3
> + * TODO: PLL1 tuning register

I don't think we need those TODO's at all, and these comments too. If
the clock name is good enough (and it is), it's redundant.

> + */
> +static struct ccu_nkmp pll_core_clk = {
> +	.enable		= BIT(31),
> +	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
> +	.k		= _SUNXI_CCU_MULT(4, 2),
> +	.m		= _SUNXI_CCU_DIV(0, 2),
> +	.p		= _SUNXI_CCU_DIV(16, 2),
> +	.common		= {
> +		.reg		= 0x000,
> +		.hw.init	= CLK_HW_INIT("pll-core",
> +					      "hosc",
> +					      &ccu_nkmp_ops,
> +					      0),
> +	},
> +};
> +
> +/* PLL2 - Audio clock */
> +static struct ccu_nm pll_audio_base_clk = {
> +	.enable		= BIT(31),
> +	.n		= _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
> +	.m		= _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
> +	.common		= {
> +		.reg		= 0x008,
> +		.hw.init	= CLK_HW_INIT("pll-audio-base",
> +					      "hosc",
> +					      &ccu_nm_ops,
> +					      0),
> +	},
> +
> +};

You're forgetting the post-divider here

> +/* TODO: pll8 gpu 0x040 */

Please add all the clocks.

> +/* BIT(21 .. 31) - reserved */

I'm not sure we need those comments either.

> +/*
> + * TODO: SATA clock also supports external clock as parent.
> + * Currently we default to using PLL6 SATA gate.
> + */

Which external clock? It should be modelled anyway. If we have a
dependency on some other clock, it should be in our DT binding, and
listed in the mux there.

Otherwise, the clock framework will not be able to deal with that mux
being already set by the bootloader, and if we need to support that
clock in the future, our binding will be ready for it.

> +static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
> +			"pll-periph", 1, 2, CLK_SET_RATE_PARENT);
> +/* We hardcode the divider to 4 for now */
> +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
> +			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
> +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
> +			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
> +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
> +			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
> +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
> +			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
> +static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
> +			"pll-video0", 1, 2, CLK_SET_RATE_PARENT);
> +static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
> +			"pll-video1", 1, 2, CLK_SET_RATE_PARENT);

It feels more natural to just have the clocks defined in the same
order than their parents. So periph shouldn't be first

> +static struct ccu_reset_map sun7i_a20_ccu_resets[] = {
> +
> +	[RST_USB_PHY0]		= { 0x0cc, BIT(0) },
> +	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
> +	[RST_USB_PHY2]		= { 0x0cc, BIT(2) },
> +	[RST_DE_BE0]		= { 0x104, BIT(30) },
> +	[RST_DE_BE1]		= { 0x108, BIT(30) },
> +	[RST_DE_FE0]		= { 0x10c, BIT(30) },
> +	[RST_DE_FE1]		= { 0x110, BIT(30) },
> +	[RST_DE_MP]		= { 0x114, BIT(30) },
> +	[RST_TCON0]		= { 0x118, BIT(30) },
> +	[RST_TCON1]		= { 0x11c, BIT(30) },
> +	[RST_CSI0]		= { 0x134, BIT(30) },
> +	[RST_CSI1]		= { 0x138, BIT(30) },
> +	[RST_VE]		= { 0x13c, BIT(0) },
> +	[RST_ACE]		= { 0x148, BIT(16) },
> +	[RST_LVDS]		= { 0x14c, BIT(0) },
> +	[RST_GPU]		= { 0x154, BIT(30) },
> +	[RST_HDMI_H]		= { 0x170, BIT(0) },
> +	[RST_HDMI_SYS]		= { 0x170, BIT(1) },
> +	[RST_HDMI_AUDIO_DMA]	= { 0x170, BIT(2) },
> +};
> +
> +static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {
> +	.ccu_clks	= sun7i_a20_ccu_clks,
> +	.num_ccu_clks	= ARRAY_SIZE(sun7i_a20_ccu_clks),
> +
> +	.hw_clks	= &sun7i_a20_hw_clks,
> +
> +	.resets		= sun7i_a20_ccu_resets,
> +	.num_resets	= ARRAY_SIZE(sun7i_a20_ccu_resets),
> +};
> +
> +static void __init sun7i_a20_ccu_setup(struct device_node *node)
> +{
> +	void __iomem *reg;
> +	u32 val;
> +
> +	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> +	if (IS_ERR(reg)) {
> +		pr_err("%s: Could not map the clock registers\n",
> +		       of_node_full_name(node));
> +		return;
> +	}
> +
> +	#define SUN7I_PLL_AUDIO_REG	0x008

This should be defined above

> +
> +	/* Force the PLL-Audio-1x divider to 4 */
> +	val = readl(reg + SUN7I_PLL_AUDIO_REG);
> +	val &= ~GENMASK(19, 16);
> +	writel(val | (3 << 16), reg + SUN7I_PLL_AUDIO_REG);
> +
> +	/*
> +	 * Use PLL6 as parent for AHB
> +	 * CPU/AXI clock changes rate when cpufreq is enabled

I'm not sure why that last sentence is needed too. A lot of clock
listed there change rate when <some-feature> is enabled.

> +/* Some AHB gates are exported */
> +#define CLK_AHB_BIST		31
> +#define CLK_AHB_MS		36
> +#define CLK_AHB_SDRAM		38
> +#define CLK_AHB_ACE		39
> +#define CLK_AHB_TS		41
> +#define CLK_AHB_VE		48
> +#define CLK_AHB_TVD		49
> +#define CLK_AHB_TVE1		51
> +#define CLK_AHB_LCD1		53
> +#define CLK_AHB_CSI0		54
> +#define CLK_AHB_CSI1		55
> +#define CLK_AHB_HDMI0		56
> +#define CLK_AHB_DE_BE1		59
> +#define CLK_AHB_DE_FE0		60
> +#define CLK_AHB_DE_FE1		61
> +#define CLK_AHB_MP		63
> +#define CLK_AHB_GPU		64
> +
> +/* Some APB0 gates are exported */
> +#define CLK_APB0_AC97		67
> +#define CLK_APB0_KEYPAD		74
> +
> +/* Some APB1 gates are exported */
> +#define CLK_APB1_CAN		79
> +#define CLK_APB1_SCR		80
> +
> +/* Some IP module clocks are exported */
> +#define CLK_MS			93
> +#define CLK_TS			106
> +#define CLK_PATA		111
> +#define CLK_AC97		115
> +#define CLK_KEYPAD		117
> +#define CLK_SATA		118
> +
> +/* Some DRAM gates are exported */
> +#define CLK_DRAM_VE		125
> +#define CLK_DRAM_CSI0		126
> +#define CLK_DRAM_CSI1		127
> +#define CLK_DRAM_TS		128
> +#define CLK_DRAM_TVD		129
> +#define CLK_DRAM_TVE1		131
> +#define CLK_DRAM_OUT		132
> +#define CLK_DRAM_DE_FE1		133
> +#define CLK_DRAM_DE_FE0		134
> +#define CLK_DRAM_DE_BE1		136
> +#define CLK_DRAM_MP		137
> +#define CLK_DRAM_ACE		138
> +
> +#define CLK_DE_BE1		140
> +#define CLK_DE_FE0		141
> +#define CLK_DE_FE1		142
> +#define CLK_DE_MP		143
> +#define CLK_TCON1_CH0		145
> +#define CLK_CSI_SPECIAL		146
> +#define CLK_TVD			147
> +#define CLK_TCON0_CH1_SCLK2	148
> +#define CLK_TCON1_CH1_SCLK2	150
> +#define CLK_TCON1_CH1		151
> +#define CLK_CSI0		152
> +#define CLK_CSI1		153
> +#define CLK_VE			154
> +#define CLK_AVS			156
> +#define CLK_ACE			157
> +#define CLK_HDMI		158
> +#define CLK_GPU			159
> +#define CLK_MBUS		160
> +#define CLK_HDMI1_SLOW		161
> +#define CLK_HDMI1_REPEAT	162
> +#define CLK_OUT_A		163
> +#define CLK_OUT_B		164

Is there a reason not to expose these clocks?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: Re: [PATCH 2/4] clk: sunxi-ng: Add sun7i-a20 CCU driver

[Priit Laes]

On Tue, 2017-02-28 at 09:21 +0100, Maxime Ripard wrote:
> Hi,
> 
> On Mon, Feb 27, 2017 at 11:09:12PM +0200, Priit Laes wrote:
> > Introduce a clock controller driver for sun7i A20 SoC.
> > 
> > > > Signed-off-by: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
> > ---
> >  drivers/clk/sunxi-ng/Kconfig         |   11 +
> >  drivers/clk/sunxi-ng/Makefile        |    1 +
> >  drivers/clk/sunxi-ng/ccu-sun7i-a20.c | 1068 ++++++++++++++++++++++++++++++++++
> >  drivers/clk/sunxi-ng/ccu-sun7i-a20.h |  121 ++++
> >  4 files changed, 1201 insertions(+)
> >  create mode 100644 drivers/clk/sunxi-ng/ccu-sun7i-a20.c
> >  create mode 100644 drivers/clk/sunxi-ng/ccu-sun7i-a20.h
> > 
> > diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> > index 695bbf9..4f436ab 100644
> > --- a/drivers/clk/sunxi-ng/Kconfig
> > +++ b/drivers/clk/sunxi-ng/Kconfig
> > @@ -85,6 +85,17 @@ config SUN6I_A31_CCU
> > > >  	select SUNXI_CCU_PHASE
> > > >  	default MACH_SUN6I
> >  
> > +config SUN7I_A20_CCU
> > > > +	bool "Support for the Allwinner A20 CCU"
> > > > +	select SUNXI_CCU_DIV
> > > > +	select SUNXI_CCU_MULT
> > > > +	select SUNXI_CCU_NK
> > > > +	select SUNXI_CCU_NKM
> > > > +	select SUNXI_CCU_NM
> > > > +	select SUNXI_CCU_MP
> > > > +	select SUNXI_CCU_PHASE
> > > > +	default MACH_SUN7I
> > +
> >  config SUN8I_A23_CCU
> > > >  	bool "Support for the Allwinner A23 CCU"
> > > >  	select SUNXI_CCU_DIV
> > diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> > index 6feaac0..bedda5b 100644
> > --- a/drivers/clk/sunxi-ng/Makefile
> > +++ b/drivers/clk/sunxi-ng/Makefile
> > > > @@ -21,6 +21,7 @@ obj-$(CONFIG_SUNXI_CCU_MP)	+= ccu_mp.o
> > > >  obj-$(CONFIG_SUN50I_A64_CCU)	+= ccu-sun50i-a64.o
> > > >  obj-$(CONFIG_SUN5I_CCU)		+= ccu-sun5i.o
> > > >  obj-$(CONFIG_SUN6I_A31_CCU)	+= ccu-sun6i-a31.o
> > > > +obj-$(CONFIG_SUN7I_A20_CCU)	+= ccu-sun7i-a20.o
> > > >  obj-$(CONFIG_SUN8I_A23_CCU)	+= ccu-sun8i-a23.o
> > > >  obj-$(CONFIG_SUN8I_A33_CCU)	+= ccu-sun8i-a33.o
> > > >  obj-$(CONFIG_SUN8I_H3_CCU)	+= ccu-sun8i-h3.o
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun7i-a20.c b/drivers/clk/sunxi-ng/ccu-sun7i-a20.c
> > new file mode 100644
> > index 0000000..90d2f13
> > --- /dev/null
> > +++ b/drivers/clk/sunxi-ng/ccu-sun7i-a20.c
> > @@ -0,0 +1,1068 @@
> > +/*
> > + * Copyright (c) 2017 Priit Laes. All rights reserved.
> > + *
> > + * This software is licensed under the terms of the GNU General Public
> > + * License version 2, as published by the Free Software Foundation, and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/of_address.h>
> > +
> > +#include "ccu_common.h"
> > +#include "ccu_reset.h"
> > +
> > +#include "ccu_div.h"
> > +#include "ccu_gate.h"
> > +#include "ccu_mp.h"
> > +#include "ccu_mult.h"
> > +#include "ccu_nk.h"
> > +#include "ccu_nkm.h"
> > +#include "ccu_nkmp.h"
> > +#include "ccu_nm.h"
> > +#include "ccu_phase.h"
> > +
> > +#include "ccu-sun7i-a20.h"
> > +
> > +/*
> > + * PLL1 - Core clock
> > + *
> > + * TODO: sigma-delta pattern bits 2 & 3
> > + * TODO: PLL1 tuning register
> 
> I don't think we need those TODO's at all, and these comments too. If
> the clock name is good enough (and it is), it's redundant.

Ok, will clean them up.

> 
> > + */
> > 
[...]
> > +};
> > +
> > +/* PLL2 - Audio clock */
> > +static struct ccu_nm pll_audio_base_clk = {
> > > > > > +	.enable		= BIT(31),
> > > > > > +	.n		= _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
> > > > > > +	.m		= _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
> > > > > > +	.common		= {
> > > > > > +		.reg		= 0x008,
> > > > > > +		.hw.init	= CLK_HW_INIT("pll-audio-base",
> > > > +					      "hosc",
> > > > +					      &ccu_nm_ops,
> > > > +					      0),
> > > > +	},
> > +
> > +};
> 
> You're forgetting the post-divider here

It's hardcoded to 4 during ccu initialization, similar to what is done
on the other SoCs (A13, A31..).

> 
> > +/* TODO: pll8 gpu 0x040 */
> 
> Please add all the clocks.

I'm not really comfortable adding clocks for blocks that currently lack
drivers.

> > +/* BIT(21 .. 31) - reserved */
> 
> I'm not sure we need those comments either.
> 
> > +/*
> > + * TODO: SATA clock also supports external clock as parent.
> > + * Currently we default to using PLL6 SATA gate.
> > + */
> 
> Which external clock? It should be modelled anyway. If we have a
> dependency on some other clock, it should be in our DT binding, and
> listed in the mux there.
> 
> Otherwise, the clock framework will not be able to deal with that mux
> being already set by the bootloader, and if we need to support that
> clock in the future, our binding will be ready for it.

I wish I knew which clock they're talking about..

User manuals (A10/A20) only specify following in the clock register
description:

BIT(24) - CLK_SRC_GATING, default 0x0
Clock Source Select:
0: PLL6 for SATA(100MHz)
1: External Clock

There's no section for SATA (called NC) in A10 manual, and in A20
manual only contains list of SATA/AHCI features.


> 
> > +static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
> > > > +			"pll-periph", 1, 2, CLK_SET_RATE_PARENT);
> > +/* We hardcode the divider to 4 for now */
> > +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
> > > > +			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
> > +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
> > > > +			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
> > +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
> > > > +			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
> > +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
> > > > +			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
> > +static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
> > > > +			"pll-video0", 1, 2, CLK_SET_RATE_PARENT);
> > +static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
> > +			"pll-video1", 1, 2, CLK_SET_RATE_PARENT);
> 
> It feels more natural to just have the clocks defined in the same
> order than their parents. So periph shouldn't be first

Ok, will move the periph clock after the video.

> > +static struct ccu_reset_map sun7i_a20_ccu_resets[] = {
> > +
> > > > > > +	[RST_USB_PHY0]		= { 0x0cc, BIT(0) },
> > > > > > +	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
> > > > > > +	[RST_USB_PHY2]		= { 0x0cc, BIT(2) },
> > > > > > +	[RST_DE_BE0]		= { 0x104, BIT(30) },
> > > > > > +	[RST_DE_BE1]		= { 0x108, BIT(30) },
> > > > > > +	[RST_DE_FE0]		= { 0x10c, BIT(30) },
> > > > > > +	[RST_DE_FE1]		= { 0x110, BIT(30) },
> > > > > > +	[RST_DE_MP]		= { 0x114, BIT(30) },
> > > > > > +	[RST_TCON0]		= { 0x118, BIT(30) },
> > > > > > +	[RST_TCON1]		= { 0x11c, BIT(30) },
> > > > > > +	[RST_CSI0]		= { 0x134, BIT(30) },
> > > > > > +	[RST_CSI1]		= { 0x138, BIT(30) },
> > > > > > +	[RST_VE]		= { 0x13c, BIT(0) },
> > > > > > +	[RST_ACE]		= { 0x148, BIT(16) },
> > > > > > +	[RST_LVDS]		= { 0x14c, BIT(0) },
> > > > > > +	[RST_GPU]		= { 0x154, BIT(30) },
> > > > > > +	[RST_HDMI_H]		= { 0x170, BIT(0) },
> > > > > > +	[RST_HDMI_SYS]		= { 0x170, BIT(1) },
> > > > > > +	[RST_HDMI_AUDIO_DMA]	= { 0x170, BIT(2) },
> > +};
> > +
> > +static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {
> > > > > > +	.ccu_clks	= sun7i_a20_ccu_clks,
> > > > > > +	.num_ccu_clks	= ARRAY_SIZE(sun7i_a20_ccu_clks),
> > +
> > > > > > +	.hw_clks	= &sun7i_a20_hw_clks,
> > +
> > > > > > +	.resets		= sun7i_a20_ccu_resets,
> > > > > > +	.num_resets	= ARRAY_SIZE(sun7i_a20_ccu_resets),
> > +};
> > +
> > +static void __init sun7i_a20_ccu_setup(struct device_node *node)
> > +{
> > > > +	void __iomem *reg;
> > > > +	u32 val;
> > +
> > > > +	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> > > > +	if (IS_ERR(reg)) {
> > > > +		pr_err("%s: Could not map the clock registers\n",
> > > > +		       of_node_full_name(node));
> > > > +		return;
> > > > +	}
> > +
> > +	#define SUN7I_PLL_AUDIO_REG	0x008
> 
> This should be defined above

Will do..
> 
> > +
> > > > +	/* Force the PLL-Audio-1x divider to 4 */
> > > > +	val = readl(reg + SUN7I_PLL_AUDIO_REG);
> > > > +	val &= ~GENMASK(19, 16);
> > > > +	writel(val | (3 << 16), reg + SUN7I_PLL_AUDIO_REG);
> > +
> > > > +	/*
> > > > +	 * Use PLL6 as parent for AHB
> > +	 * CPU/AXI clock changes rate when cpufreq is enabled
> 
> I'm not sure why that last sentence is needed too. A lot of clock
> listed there change rate when <some-feature> is enabled.

Will remove.

> 
> > +/* Some AHB gates are exported */
> > > > +#define CLK_AHB_BIST		31
> > > > +#define CLK_AHB_MS		36
> > > > +#define CLK_AHB_SDRAM		38
> > > > +#define CLK_AHB_ACE		39
> > > > +#define CLK_AHB_TS		41
> > > > +#define CLK_AHB_VE		48
> > > > +#define CLK_AHB_TVD		49
> > > > +#define CLK_AHB_TVE1		51
> > > > +#define CLK_AHB_LCD1		53
> > > > +#define CLK_AHB_CSI0		54
> > > > +#define CLK_AHB_CSI1		55
> > > > +#define CLK_AHB_HDMI0		56
> > > > +#define CLK_AHB_DE_BE1		59
> > > > +#define CLK_AHB_DE_FE0		60
> > > > +#define CLK_AHB_DE_FE1		61
> > > > +#define CLK_AHB_MP		63
> > > > +#define CLK_AHB_GPU		64
> > +
> > +/* Some APB0 gates are exported */
> > > > +#define CLK_APB0_AC97		67
> > > > +#define CLK_APB0_KEYPAD		74
> > +
> > +/* Some APB1 gates are exported */
> > > > +#define CLK_APB1_CAN		79
> > > > +#define CLK_APB1_SCR		80
> > +
> > +/* Some IP module clocks are exported */
> > > > +#define CLK_MS			93
> > > > +#define CLK_TS			106
> > > > +#define CLK_PATA		111
> > > > +#define CLK_AC97		115
> > > > +#define CLK_KEYPAD		117
> > > > +#define CLK_SATA		118
> > +
> > +/* Some DRAM gates are exported */
> > > > +#define CLK_DRAM_VE		125
> > > > +#define CLK_DRAM_CSI0		126
> > > > +#define CLK_DRAM_CSI1		127
> > > > +#define CLK_DRAM_TS		128
> > > > +#define CLK_DRAM_TVD		129
> > > > +#define CLK_DRAM_TVE1		131
> > > > +#define CLK_DRAM_OUT		132
> > > > +#define CLK_DRAM_DE_FE1		133
> > > > +#define CLK_DRAM_DE_FE0		134
> > > > +#define CLK_DRAM_DE_BE1		136
> > > > +#define CLK_DRAM_MP		137
> > > > +#define CLK_DRAM_ACE		138
> > +
> > > > +#define CLK_DE_BE1		140
> > > > +#define CLK_DE_FE0		141
> > > > +#define CLK_DE_FE1		142
> > > > +#define CLK_DE_MP		143
> > > > +#define CLK_TCON1_CH0		145
> > > > +#define CLK_CSI_SPECIAL		146
> > > > +#define CLK_TVD			147
> > > > +#define CLK_TCON0_CH1_SCLK2	148
> > > > +#define CLK_TCON1_CH1_SCLK2	150
> > > > +#define CLK_TCON1_CH1		151
> > > > +#define CLK_CSI0		152
> > > > +#define CLK_CSI1		153
> > > > +#define CLK_VE			154
> > > > +#define CLK_AVS			156
> > > > +#define CLK_ACE			157
> > > > +#define CLK_HDMI		158
> > > > +#define CLK_GPU			159
> > > > +#define CLK_MBUS		160
> > > > +#define CLK_HDMI1_SLOW		161
> > > > +#define CLK_HDMI1_REPEAT	162
> > > > +#define CLK_OUT_A		163
> > +#define CLK_OUT_B		164
> 
> Is there a reason not to expose these clocks?

I exposed them on need to have basis. And basically did one-to-one
conversion from devicetree.

Päikest,
Priit

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Re: Re: [PATCH 2/4] clk: sunxi-ng: Add sun7i-a20 CCU driver

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 5961 bytes --]

Hi Priit,

On Wed, Mar 01, 2017 at 11:38:14PM +0200, Priit Laes wrote:
> > > +/* PLL2 - Audio clock */
> > > +static struct ccu_nm pll_audio_base_clk = {
> > > > > > > +	.enable		= BIT(31),
> > > > > > > +	.n		= _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
> > > > > > > +	.m		= _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
> > > > > > > +	.common		= {
> > > > > > > +		.reg		= 0x008,
> > > > > > > +		.hw.init	= CLK_HW_INIT("pll-audio-base",
> > > > > +					      "hosc",
> > > > > +					      &ccu_nm_ops,
> > > > > +					      0),
> > > > > +	},
> > > +
> > > +};
> > 
> > You're forgetting the post-divider here
> 
> It's hardcoded to 4 during ccu initialization, similar to what is done
> on the other SoCs (A13, A31..).

Right, sorry, I only saw it later. Please move that define you've been
using here, and it will be fine :)

> > > +/* TODO: pll8 gpu 0x040 */
> > 
> > Please add all the clocks.
> 
> I'm not really comfortable adding clocks for blocks that currently lack
> drivers.

Yet, you did it for quite a significant amount already (VE, NAND,
AC97, DE MP, etc.). Don't get me wrong, this is definitely not a
criticism. One of the point of the switch to sunxi-ng was that we
would get out of the previous situation where every time you wanted to
do something, you needed to add some clocks.

We have some generic code that, if fed the right data, will
(hopefully) just work. So it's pretty safe to add (and this is better
to be consistent, and that's the policy we had for all the other CCU
drivers).

> > > +/* BIT(21 .. 31) - reserved */
> > 
> > I'm not sure we need those comments either.
> > 
> > > +/*
> > > + * TODO: SATA clock also supports external clock as parent.
> > > + * Currently we default to using PLL6 SATA gate.
> > > + */
> > 
> > Which external clock? It should be modelled anyway. If we have a
> > dependency on some other clock, it should be in our DT binding, and
> > listed in the mux there.
> > 
> > Otherwise, the clock framework will not be able to deal with that mux
> > being already set by the bootloader, and if we need to support that
> > clock in the future, our binding will be ready for it.
> 
> I wish I knew which clock they're talking about..
> 
> User manuals (A10/A20) only specify following in the clock register
> description:
> 
> BIT(24) - CLK_SRC_GATING, default 0x0
> Clock Source Select:
> 0: PLL6 for SATA(100MHz)
> 1: External Clock
> 
> There's no section for SATA (called NC) in A10 manual, and in A20
> manual only contains list of SATA/AHCI features.

Hmmmm, ok :/

> > > +/* Some AHB gates are exported */
> > > > > +#define CLK_AHB_BIST		31
> > > > > +#define CLK_AHB_MS		36
> > > > > +#define CLK_AHB_SDRAM		38
> > > > > +#define CLK_AHB_ACE		39
> > > > > +#define CLK_AHB_TS		41
> > > > > +#define CLK_AHB_VE		48
> > > > > +#define CLK_AHB_TVD		49
> > > > > +#define CLK_AHB_TVE1		51
> > > > > +#define CLK_AHB_LCD1		53
> > > > > +#define CLK_AHB_CSI0		54
> > > > > +#define CLK_AHB_CSI1		55
> > > > > +#define CLK_AHB_HDMI0		56
> > > > > +#define CLK_AHB_DE_BE1		59
> > > > > +#define CLK_AHB_DE_FE0		60
> > > > > +#define CLK_AHB_DE_FE1		61
> > > > > +#define CLK_AHB_MP		63
> > > > > +#define CLK_AHB_GPU		64
> > > +
> > > +/* Some APB0 gates are exported */
> > > > > +#define CLK_APB0_AC97		67
> > > > > +#define CLK_APB0_KEYPAD		74
> > > +
> > > +/* Some APB1 gates are exported */
> > > > > +#define CLK_APB1_CAN		79
> > > > > +#define CLK_APB1_SCR		80
> > > +
> > > +/* Some IP module clocks are exported */
> > > > > +#define CLK_MS			93
> > > > > +#define CLK_TS			106
> > > > > +#define CLK_PATA		111
> > > > > +#define CLK_AC97		115
> > > > > +#define CLK_KEYPAD		117
> > > > > +#define CLK_SATA		118
> > > +
> > > +/* Some DRAM gates are exported */
> > > > > +#define CLK_DRAM_VE		125
> > > > > +#define CLK_DRAM_CSI0		126
> > > > > +#define CLK_DRAM_CSI1		127
> > > > > +#define CLK_DRAM_TS		128
> > > > > +#define CLK_DRAM_TVD		129
> > > > > +#define CLK_DRAM_TVE1		131
> > > > > +#define CLK_DRAM_OUT		132
> > > > > +#define CLK_DRAM_DE_FE1		133
> > > > > +#define CLK_DRAM_DE_FE0		134
> > > > > +#define CLK_DRAM_DE_BE1		136
> > > > > +#define CLK_DRAM_MP		137
> > > > > +#define CLK_DRAM_ACE		138
> > > +
> > > > > +#define CLK_DE_BE1		140
> > > > > +#define CLK_DE_FE0		141
> > > > > +#define CLK_DE_FE1		142
> > > > > +#define CLK_DE_MP		143
> > > > > +#define CLK_TCON1_CH0		145
> > > > > +#define CLK_CSI_SPECIAL		146
> > > > > +#define CLK_TVD			147
> > > > > +#define CLK_TCON0_CH1_SCLK2	148
> > > > > +#define CLK_TCON1_CH1_SCLK2	150
> > > > > +#define CLK_TCON1_CH1		151
> > > > > +#define CLK_CSI0		152
> > > > > +#define CLK_CSI1		153
> > > > > +#define CLK_VE			154
> > > > > +#define CLK_AVS			156
> > > > > +#define CLK_ACE			157
> > > > > +#define CLK_HDMI		158
> > > > > +#define CLK_GPU			159
> > > > > +#define CLK_MBUS		160
> > > > > +#define CLK_HDMI1_SLOW		161
> > > > > +#define CLK_HDMI1_REPEAT	162
> > > > > +#define CLK_OUT_A		163
> > > +#define CLK_OUT_B		164
> > 
> > Is there a reason not to expose these clocks?
> 
> I exposed them on need to have basis. And basically did one-to-one
> conversion from devicetree.

I guess we can still make some pretty good assumptions on what's going
to be needed at some point.

All the mod clocks will be, the bus gates too, the CPU too. All the
internal ones (PLL, AXI, APB, etc) can remain hidden though.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: Re: [PATCH 2/4] clk: sunxi-ng: Add sun7i-a20 CCU driver

[Chen-Yu Tsai]

On Thu, Mar 2, 2017 at 10:21 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Hi Priit,
>
> On Wed, Mar 01, 2017 at 11:38:14PM +0200, Priit Laes wrote:
>> > > +/* PLL2 - Audio clock */
>> > > +static struct ccu_nm pll_audio_base_clk = {
>> > > > > > > + .enable         = BIT(31),
>> > > > > > > + .n              = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
>> > > > > > > + .m              = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
>> > > > > > > + .common         = {
>> > > > > > > +         .reg            = 0x008,
>> > > > > > > +         .hw.init        = CLK_HW_INIT("pll-audio-base",
>> > > > > +                                           "hosc",
>> > > > > +                                           &ccu_nm_ops,
>> > > > > +                                           0),
>> > > > > +     },
>> > > +
>> > > +};
>> >
>> > You're forgetting the post-divider here
>>
>> It's hardcoded to 4 during ccu initialization, similar to what is done
>> on the other SoCs (A13, A31..).
>
> Right, sorry, I only saw it later. Please move that define you've been
> using here, and it will be fine :)
>
>> > > +/* TODO: pll8 gpu 0x040 */
>> >
>> > Please add all the clocks.
>>
>> I'm not really comfortable adding clocks for blocks that currently lack
>> drivers.
>
> Yet, you did it for quite a significant amount already (VE, NAND,
> AC97, DE MP, etc.). Don't get me wrong, this is definitely not a
> criticism. One of the point of the switch to sunxi-ng was that we
> would get out of the previous situation where every time you wanted to
> do something, you needed to add some clocks.
>
> We have some generic code that, if fed the right data, will
> (hopefully) just work. So it's pretty safe to add (and this is better
> to be consistent, and that's the policy we had for all the other CCU
> drivers).
>
>> > > +/* BIT(21 .. 31) - reserved */
>> >
>> > I'm not sure we need those comments either.
>> >
>> > > +/*
>> > > + * TODO: SATA clock also supports external clock as parent.
>> > > + * Currently we default to using PLL6 SATA gate.
>> > > + */
>> >
>> > Which external clock? It should be modelled anyway. If we have a
>> > dependency on some other clock, it should be in our DT binding, and
>> > listed in the mux there.
>> >
>> > Otherwise, the clock framework will not be able to deal with that mux
>> > being already set by the bootloader, and if we need to support that
>> > clock in the future, our binding will be ready for it.
>>
>> I wish I knew which clock they're talking about..
>>
>> User manuals (A10/A20) only specify following in the clock register
>> description:
>>
>> BIT(24) - CLK_SRC_GATING, default 0x0
>> Clock Source Select:
>> 0: PLL6 for SATA(100MHz)
>> 1: External Clock
>>
>> There's no section for SATA (called NC) in A10 manual, and in A20
>> manual only contains list of SATA/AHCI features.
>
> Hmmmm, ok :/

The external clock is probably an optional crystal or oscillator
that can be connected to the SATA-CLKM / SATA-CLKP pins.

The datasheet does not say what the frequency or any other parameters
should be though. And to my knowledge no board uses it.

ChenYu

>> > > +/* Some AHB gates are exported */
>> > > > > +#define CLK_AHB_BIST         31
>> > > > > +#define CLK_AHB_MS           36
>> > > > > +#define CLK_AHB_SDRAM                38
>> > > > > +#define CLK_AHB_ACE          39
>> > > > > +#define CLK_AHB_TS           41
>> > > > > +#define CLK_AHB_VE           48
>> > > > > +#define CLK_AHB_TVD          49
>> > > > > +#define CLK_AHB_TVE1         51
>> > > > > +#define CLK_AHB_LCD1         53
>> > > > > +#define CLK_AHB_CSI0         54
>> > > > > +#define CLK_AHB_CSI1         55
>> > > > > +#define CLK_AHB_HDMI0                56
>> > > > > +#define CLK_AHB_DE_BE1               59
>> > > > > +#define CLK_AHB_DE_FE0               60
>> > > > > +#define CLK_AHB_DE_FE1               61
>> > > > > +#define CLK_AHB_MP           63
>> > > > > +#define CLK_AHB_GPU          64
>> > > +
>> > > +/* Some APB0 gates are exported */
>> > > > > +#define CLK_APB0_AC97                67
>> > > > > +#define CLK_APB0_KEYPAD              74
>> > > +
>> > > +/* Some APB1 gates are exported */
>> > > > > +#define CLK_APB1_CAN         79
>> > > > > +#define CLK_APB1_SCR         80
>> > > +
>> > > +/* Some IP module clocks are exported */
>> > > > > +#define CLK_MS                       93
>> > > > > +#define CLK_TS                       106
>> > > > > +#define CLK_PATA             111
>> > > > > +#define CLK_AC97             115
>> > > > > +#define CLK_KEYPAD           117
>> > > > > +#define CLK_SATA             118
>> > > +
>> > > +/* Some DRAM gates are exported */
>> > > > > +#define CLK_DRAM_VE          125
>> > > > > +#define CLK_DRAM_CSI0                126
>> > > > > +#define CLK_DRAM_CSI1                127
>> > > > > +#define CLK_DRAM_TS          128
>> > > > > +#define CLK_DRAM_TVD         129
>> > > > > +#define CLK_DRAM_TVE1                131
>> > > > > +#define CLK_DRAM_OUT         132
>> > > > > +#define CLK_DRAM_DE_FE1              133
>> > > > > +#define CLK_DRAM_DE_FE0              134
>> > > > > +#define CLK_DRAM_DE_BE1              136
>> > > > > +#define CLK_DRAM_MP          137
>> > > > > +#define CLK_DRAM_ACE         138
>> > > +
>> > > > > +#define CLK_DE_BE1           140
>> > > > > +#define CLK_DE_FE0           141
>> > > > > +#define CLK_DE_FE1           142
>> > > > > +#define CLK_DE_MP            143
>> > > > > +#define CLK_TCON1_CH0                145
>> > > > > +#define CLK_CSI_SPECIAL              146
>> > > > > +#define CLK_TVD                      147
>> > > > > +#define CLK_TCON0_CH1_SCLK2  148
>> > > > > +#define CLK_TCON1_CH1_SCLK2  150
>> > > > > +#define CLK_TCON1_CH1                151
>> > > > > +#define CLK_CSI0             152
>> > > > > +#define CLK_CSI1             153
>> > > > > +#define CLK_VE                       154
>> > > > > +#define CLK_AVS                      156
>> > > > > +#define CLK_ACE                      157
>> > > > > +#define CLK_HDMI             158
>> > > > > +#define CLK_GPU                      159
>> > > > > +#define CLK_MBUS             160
>> > > > > +#define CLK_HDMI1_SLOW               161
>> > > > > +#define CLK_HDMI1_REPEAT     162
>> > > > > +#define CLK_OUT_A            163
>> > > +#define CLK_OUT_B                164
>> >
>> > Is there a reason not to expose these clocks?
>>
>> I exposed them on need to have basis. And basically did one-to-one
>> conversion from devicetree.
>
> I guess we can still make some pretty good assumptions on what's going
> to be needed at some point.
>
> All the mod clocks will be, the bus gates too, the CPU too. All the
> internal ones (PLL, AXI, APB, etc) can remain hidden though.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com

[PATCH 3/4] ARM: sun7i: Convert to CCU

[Priit Laes]

Convert sun7i-a20.dtsi to new CCU driver.

Signed-off-by: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 719 +++++----------------------------------
 1 file changed, 86 insertions(+), 633 deletions(-)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 04c9977..6f80cb8 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -47,7 +47,8 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/thermal.h>
 
-#include <dt-bindings/clock/sun4i-a10-pll2.h>
+#include <dt-bindings/clock/sun7i-ccu.h>
+#include <dt-bindings/reset/sun7i-ccu.h>
 #include <dt-bindings/dma/sun4i-a10.h>
 #include <dt-bindings/pinctrl/sun4i-a10.h>
 
@@ -67,19 +68,19 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0-hdmi";
-			clocks = <&ahb_gates 36>, <&ahb_gates 43>,
-				 <&ahb_gates 44>, <&de_be0_clk>,
-				 <&tcon0_ch1_clk>, <&dram_gates 26>;
+			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI1>,
+				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
+				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
 			status = "disabled";
 		};
 
-		framebuffer@1 {
+		framebuffer@0 {
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0";
-			clocks = <&ahb_gates 36>, <&ahb_gates 44>,
-				 <&de_be0_clk>, <&tcon0_ch0_clk>,
-				 <&dram_gates 26>;
+			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
+				 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
+				 <&ccu CLK_DRAM_DE_BE0>;
 			status = "disabled";
 		};
 
@@ -87,10 +88,10 @@
 			compatible = "allwinner,simple-framebuffer",
 				     "simple-framebuffer";
 			allwinner,pipeline = "de_be0-lcd0-tve0";
-			clocks = <&ahb_gates 34>, <&ahb_gates 36>,
-				 <&ahb_gates 44>,
-				 <&de_be0_clk>, <&tcon0_ch1_clk>,
-				 <&dram_gates 5>, <&dram_gates 26>;
+			clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
+				 <&ccu CLK_AHB_DE_BE0>,
+				 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
+				 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
 			status = "disabled";
 		};
 	};
@@ -103,7 +104,7 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0>;
-			clocks = <&cpu>;
+			clocks = <&ccu CLK_CPU>;
 			clock-latency = <244144>; /* 8 32k periods */
 			operating-points = <
 				/* kHz	  uV */
@@ -184,21 +185,11 @@
 
 		osc24M: clk@01c20050 {
 			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-osc-clk";
-			reg = <0x01c20050 0x4>;
+			compatible = "fixed-clock";
 			clock-frequency = <24000000>;
 			clock-output-names = "osc24M";
 		};
 
-		osc3M: osc3M_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-factor-clock";
-			clock-div = <8>;
-			clock-mult = <1>;
-			clocks = <&osc24M>;
-			clock-output-names = "osc3M";
-		};
-
 		osc32k: clk@0 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -206,528 +197,6 @@
 			clock-output-names = "osc32k";
 		};
 
-		pll1: clk@01c20000 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-pll1-clk";
-			reg = <0x01c20000 0x4>;
-			clocks = <&osc24M>;
-			clock-output-names = "pll1";
-		};
-
-		pll2: clk@01c20008 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-pll2-clk";
-			reg = <0x01c20008 0x8>;
-			clocks = <&osc24M>;
-			clock-output-names = "pll2-1x", "pll2-2x",
-					     "pll2-4x", "pll2-8x";
-		};
-
-		pll3: clk@01c20010 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-pll3-clk";
-			reg = <0x01c20010 0x4>;
-			clocks = <&osc3M>;
-			clock-output-names = "pll3";
-		};
-
-		pll3x2: pll3x2_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-factor-clock";
-			clocks = <&pll3>;
-			clock-div = <1>;
-			clock-mult = <2>;
-			clock-output-names = "pll3-2x";
-		};
-
-		pll4: clk@01c20018 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun7i-a20-pll4-clk";
-			reg = <0x01c20018 0x4>;
-			clocks = <&osc24M>;
-			clock-output-names = "pll4";
-		};
-
-		pll5: clk@01c20020 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-pll5-clk";
-			reg = <0x01c20020 0x4>;
-			clocks = <&osc24M>;
-			clock-output-names = "pll5_ddr", "pll5_other";
-		};
-
-		pll6: clk@01c20028 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-pll6-clk";
-			reg = <0x01c20028 0x4>;
-			clocks = <&osc24M>;
-			clock-output-names = "pll6_sata", "pll6_other", "pll6",
-					     "pll6_div_4";
-		};
-
-		pll7: clk@01c20030 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-pll3-clk";
-			reg = <0x01c20030 0x4>;
-			clocks = <&osc3M>;
-			clock-output-names = "pll7";
-		};
-
-		pll7x2: pll7x2_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-factor-clock";
-			clocks = <&pll7>;
-			clock-div = <1>;
-			clock-mult = <2>;
-			clock-output-names = "pll7-2x";
-		};
-
-		pll8: clk@01c20040 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun7i-a20-pll4-clk";
-			reg = <0x01c20040 0x4>;
-			clocks = <&osc24M>;
-			clock-output-names = "pll8";
-		};
-
-		cpu: cpu@01c20054 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-cpu-clk";
-			reg = <0x01c20054 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
-			clock-output-names = "cpu";
-		};
-
-		axi: axi@01c20054 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-axi-clk";
-			reg = <0x01c20054 0x4>;
-			clocks = <&cpu>;
-			clock-output-names = "axi";
-		};
-
-		ahb: ahb@01c20054 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun5i-a13-ahb-clk";
-			reg = <0x01c20054 0x4>;
-			clocks = <&axi>, <&pll6 3>, <&pll6 1>;
-			clock-output-names = "ahb";
-			/*
-			 * Use PLL6 as parent, instead of CPU/AXI
-			 * which has rate changes due to cpufreq
-			 */
-			assigned-clocks = <&ahb>;
-			assigned-clock-parents = <&pll6 3>;
-		};
-
-		ahb_gates: clk@01c20060 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun7i-a20-ahb-gates-clk";
-			reg = <0x01c20060 0x8>;
-			clocks = <&ahb>;
-			clock-indices = <0>, <1>,
-					<2>, <3>, <4>,
-					<5>, <6>, <7>, <8>,
-					<9>, <10>, <11>, <12>,
-					<13>, <14>, <16>,
-					<17>, <18>, <20>, <21>,
-					<22>, <23>, <25>,
-					<28>, <32>, <33>, <34>,
-					<35>, <36>, <37>, <40>,
-					<41>, <42>, <43>,
-					<44>, <45>, <46>,
-					<47>, <49>, <50>,
-					<52>;
-			clock-output-names = "ahb_usb0", "ahb_ehci0",
-				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
-				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
-				"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
-				"ahb_nand", "ahb_sdram", "ahb_ace",
-				"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
-				"ahb_spi2", "ahb_spi3", "ahb_sata",
-				"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
-				"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
-				"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
-				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
-				"ahb_de_fe1", "ahb_gmac", "ahb_mp",
-				"ahb_mali";
-		};
-
-		apb0: apb0@01c20054 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-apb0-clk";
-			reg = <0x01c20054 0x4>;
-			clocks = <&ahb>;
-			clock-output-names = "apb0";
-		};
-
-		apb0_gates: clk@01c20068 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun7i-a20-apb0-gates-clk";
-			reg = <0x01c20068 0x4>;
-			clocks = <&apb0>;
-			clock-indices = <0>, <1>,
-					<2>, <3>, <4>,
-					<5>, <6>, <7>,
-					<8>, <10>;
-			clock-output-names = "apb0_codec", "apb0_spdif",
-				"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
-				"apb0_pio", "apb0_ir0", "apb0_ir1",
-				"apb0_i2s2", "apb0_keypad";
-		};
-
-		apb1: clk@01c20058 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-apb1-clk";
-			reg = <0x01c20058 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
-			clock-output-names = "apb1";
-		};
-
-		apb1_gates: clk@01c2006c {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun7i-a20-apb1-gates-clk";
-			reg = <0x01c2006c 0x4>;
-			clocks = <&apb1>;
-			clock-indices = <0>, <1>,
-					<2>, <3>, <4>,
-					<5>, <6>, <7>,
-					<15>, <16>, <17>,
-					<18>, <19>, <20>,
-					<21>, <22>, <23>;
-			clock-output-names = "apb1_i2c0", "apb1_i2c1",
-				"apb1_i2c2", "apb1_i2c3", "apb1_can",
-				"apb1_scr", "apb1_ps20", "apb1_ps21",
-				"apb1_i2c4", "apb1_uart0", "apb1_uart1",
-				"apb1_uart2", "apb1_uart3", "apb1_uart4",
-				"apb1_uart5", "apb1_uart6", "apb1_uart7";
-		};
-
-		nand_clk: clk@01c20080 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c20080 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "nand";
-		};
-
-		ms_clk: clk@01c20084 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c20084 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "ms";
-		};
-
-		mmc0_clk: clk@01c20088 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c20088 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "mmc0",
-					     "mmc0_output",
-					     "mmc0_sample";
-		};
-
-		mmc1_clk: clk@01c2008c {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c2008c 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "mmc1",
-					     "mmc1_output",
-					     "mmc1_sample";
-		};
-
-		mmc2_clk: clk@01c20090 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c20090 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "mmc2",
-					     "mmc2_output",
-					     "mmc2_sample";
-		};
-
-		mmc3_clk: clk@01c20094 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c20094 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "mmc3",
-					     "mmc3_output",
-					     "mmc3_sample";
-		};
-
-		ts_clk: clk@01c20098 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c20098 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "ts";
-		};
-
-		ss_clk: clk@01c2009c {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c2009c 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "ss";
-		};
-
-		spi0_clk: clk@01c200a0 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c200a0 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "spi0";
-		};
-
-		spi1_clk: clk@01c200a4 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c200a4 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "spi1";
-		};
-
-		spi2_clk: clk@01c200a8 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c200a8 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "spi2";
-		};
-
-		pata_clk: clk@01c200ac {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c200ac 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "pata";
-		};
-
-		ir0_clk: clk@01c200b0 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c200b0 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "ir0";
-		};
-
-		ir1_clk: clk@01c200b4 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c200b4 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "ir1";
-		};
-
-		i2s0_clk: clk@01c200b8 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod1-clk";
-			reg = <0x01c200b8 0x4>;
-			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
-				 <&pll2 SUN4I_A10_PLL2_4X>,
-				 <&pll2 SUN4I_A10_PLL2_2X>,
-				 <&pll2 SUN4I_A10_PLL2_1X>;
-			clock-output-names = "i2s0";
-		};
-
-		ac97_clk: clk@01c200bc {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod1-clk";
-			reg = <0x01c200bc 0x4>;
-			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
-				 <&pll2 SUN4I_A10_PLL2_4X>,
-				 <&pll2 SUN4I_A10_PLL2_2X>,
-				 <&pll2 SUN4I_A10_PLL2_1X>;
-			clock-output-names = "ac97";
-		};
-
-		spdif_clk: clk@01c200c0 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod1-clk";
-			reg = <0x01c200c0 0x4>;
-			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
-				 <&pll2 SUN4I_A10_PLL2_4X>,
-				 <&pll2 SUN4I_A10_PLL2_2X>,
-				 <&pll2 SUN4I_A10_PLL2_1X>;
-			clock-output-names = "spdif";
-		};
-
-		keypad_clk: clk@01c200c4 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c200c4 0x4>;
-			clocks = <&osc24M>;
-			clock-output-names = "keypad";
-		};
-
-		usb_clk: clk@01c200cc {
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-			compatible = "allwinner,sun4i-a10-usb-clk";
-			reg = <0x01c200cc 0x4>;
-			clocks = <&pll6 1>;
-			clock-output-names = "usb_ohci0", "usb_ohci1",
-					     "usb_phy";
-		};
-
-		spi3_clk: clk@01c200d4 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod0-clk";
-			reg = <0x01c200d4 0x4>;
-			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-			clock-output-names = "spi3";
-		};
-
-		i2s1_clk: clk@01c200d8 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod1-clk";
-			reg = <0x01c200d8 0x4>;
-			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
-				 <&pll2 SUN4I_A10_PLL2_4X>,
-				 <&pll2 SUN4I_A10_PLL2_2X>,
-				 <&pll2 SUN4I_A10_PLL2_1X>;
-			clock-output-names = "i2s1";
-		};
-
-		i2s2_clk: clk@01c200dc {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-mod1-clk";
-			reg = <0x01c200dc 0x4>;
-			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
-				 <&pll2 SUN4I_A10_PLL2_4X>,
-				 <&pll2 SUN4I_A10_PLL2_2X>,
-				 <&pll2 SUN4I_A10_PLL2_1X>;
-			clock-output-names = "i2s2";
-		};
-
-		dram_gates: clk@01c20100 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-dram-gates-clk";
-			reg = <0x01c20100 0x4>;
-			clocks = <&pll5 0>;
-			clock-indices = <0>,
-					<1>, <2>,
-					<3>,
-					<4>,
-					<5>, <6>,
-					<15>,
-					<24>, <25>,
-					<26>, <27>,
-					<28>, <29>;
-			clock-output-names = "dram_ve",
-					     "dram_csi0", "dram_csi1",
-					     "dram_ts",
-					     "dram_tvd",
-					     "dram_tve0", "dram_tve1",
-					     "dram_output",
-					     "dram_de_fe1", "dram_de_fe0",
-					     "dram_de_be0", "dram_de_be1",
-					     "dram_de_mp", "dram_ace";
-		};
-
-		de_be0_clk: clk@01c20104 {
-			#clock-cells = <0>;
-			#reset-cells = <0>;
-			compatible = "allwinner,sun4i-a10-display-clk";
-			reg = <0x01c20104 0x4>;
-			clocks = <&pll3>, <&pll7>, <&pll5 1>;
-			clock-output-names = "de-be0";
-		};
-
-		de_be1_clk: clk@01c20108 {
-			#clock-cells = <0>;
-			#reset-cells = <0>;
-			compatible = "allwinner,sun4i-a10-display-clk";
-			reg = <0x01c20108 0x4>;
-			clocks = <&pll3>, <&pll7>, <&pll5 1>;
-			clock-output-names = "de-be1";
-		};
-
-		de_fe0_clk: clk@01c2010c {
-			#clock-cells = <0>;
-			#reset-cells = <0>;
-			compatible = "allwinner,sun4i-a10-display-clk";
-			reg = <0x01c2010c 0x4>;
-			clocks = <&pll3>, <&pll7>, <&pll5 1>;
-			clock-output-names = "de-fe0";
-		};
-
-		de_fe1_clk: clk@01c20110 {
-			#clock-cells = <0>;
-			#reset-cells = <0>;
-			compatible = "allwinner,sun4i-a10-display-clk";
-			reg = <0x01c20110 0x4>;
-			clocks = <&pll3>, <&pll7>, <&pll5 1>;
-			clock-output-names = "de-fe1";
-		};
-
-		tcon0_ch0_clk: clk@01c20118 {
-			#clock-cells = <0>;
-			#reset-cells = <1>;
-			compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
-			reg = <0x01c20118 0x4>;
-			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
-			clock-output-names = "tcon0-ch0-sclk";
-
-		};
-
-		tcon1_ch0_clk: clk@01c2011c {
-			#clock-cells = <0>;
-			#reset-cells = <1>;
-			compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
-			reg = <0x01c2011c 0x4>;
-			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
-			clock-output-names = "tcon1-ch0-sclk";
-
-		};
-
-		tcon0_ch1_clk: clk@01c2012c {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
-			reg = <0x01c2012c 0x4>;
-			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
-			clock-output-names = "tcon0-ch1-sclk";
-
-		};
-
-		tcon1_ch1_clk: clk@01c20130 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
-			reg = <0x01c20130 0x4>;
-			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
-			clock-output-names = "tcon1-ch1-sclk";
-
-		};
-
-		ve_clk: clk@01c2013c {
-			#clock-cells = <0>;
-			#reset-cells = <0>;
-			compatible = "allwinner,sun4i-a10-ve-clk";
-			reg = <0x01c2013c 0x4>;
-			clocks = <&pll4>;
-			clock-output-names = "ve";
-		};
-
-		codec_clk: clk@01c20140 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-a10-codec-clk";
-			reg = <0x01c20140 0x4>;
-			clocks = <&pll2 SUN4I_A10_PLL2_1X>;
-			clock-output-names = "codec";
-		};
-
-		mbus_clk: clk@01c2015c {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun5i-a13-mbus-clk";
-			reg = <0x01c2015c 0x4>;
-			clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
-			clock-output-names = "mbus";
-		};
-
 		/*
 		 * The following two are dummy clocks, placeholders
 		 * used in the gmac_tx clock. The gmac driver will
@@ -737,14 +206,14 @@
 		 * The actual TX clock rate is not controlled by the
 		 * gmac_tx clock.
 		 */
-		mii_phy_tx_clk: clk@2 {
+		mii_phy_tx_clk: clk@1 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <25000000>;
 			clock-output-names = "mii_phy_tx";
 		};
 
-		gmac_int_tx_clk: clk@3 {
+		gmac_int_tx_clk: clk@2 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <125000000>;
@@ -758,34 +227,6 @@
 			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 			clock-output-names = "gmac_tx";
 		};
-
-		/*
-		 * Dummy clock used by output clocks
-		 */
-		osc24M_32k: clk@1 {
-			#clock-cells = <0>;
-			compatible = "fixed-factor-clock";
-			clock-div = <750>;
-			clock-mult = <1>;
-			clocks = <&osc24M>;
-			clock-output-names = "osc24M_32k";
-		};
-
-		clk_out_a: clk@01c201f0 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun7i-a20-out-clk";
-			reg = <0x01c201f0 0x4>;
-			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
-			clock-output-names = "clk_out_a";
-		};
-
-		clk_out_b: clk@01c201f4 {
-			#clock-cells = <0>;
-			compatible = "allwinner,sun7i-a20-out-clk";
-			reg = <0x01c201f4 0x4>;
-			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
-			clock-output-names = "clk_out_b";
-		};
 	};
 
 	soc@01c00000 {
@@ -842,7 +283,7 @@
 			compatible = "allwinner,sun4i-a10-dma";
 			reg = <0x01c02000 0x1000>;
 			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ahb_gates 6>;
+			clocks = <&ccu CLK_AHB_DMA>;
 			#dma-cells = <2>;
 		};
 
@@ -850,7 +291,7 @@
 			compatible = "allwinner,sun4i-a10-nand";
 			reg = <0x01c03000 0x1000>;
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ahb_gates 13>, <&nand_clk>;
+			clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 			clock-names = "ahb", "mod";
 			dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 			dma-names = "rxtx";
@@ -863,7 +304,7 @@
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c05000 0x1000>;
 			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ahb_gates 20>, <&spi0_clk>;
+			clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 			clock-names = "ahb", "mod";
 			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 			       <&dma SUN4I_DMA_DEDICATED 26>;
@@ -878,7 +319,7 @@
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c06000 0x1000>;
 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ahb_gates 21>, <&spi1_clk>;
+			clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 			clock-names = "ahb", "mod";
 			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 			       <&dma SUN4I_DMA_DEDICATED 8>;
@@ -893,7 +334,7 @@
 			compatible = "allwinner,sun4i-a10-emac";
 			reg = <0x01c0b000 0x1000>;
 			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ahb_gates 17>;
+			clocks = <&ccu CLK_AHB_EMAC>;
 			allwinner,sram = <&emac_sram 1>;
 			status = "disabled";
 		};
@@ -909,10 +350,10 @@
 		mmc0: mmc@01c0f000 {
 			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c0f000 0x1000>;
-			clocks = <&ahb_gates 8>,
-				 <&mmc0_clk 0>,
-				 <&mmc0_clk 1>,
-				 <&mmc0_clk 2>;
+			clocks = <&ccu CLK_AHB_MMC0>,
+				 <&ccu CLK_MMC0>,
+				 <&ccu CLK_MMC0_OUTPUT>,
+				 <&ccu CLK_MMC0_SAMPLE>;
 			clock-names = "ahb",
 				      "mmc",
 				      "output",
@@ -926,10 +367,10 @@
 		mmc1: mmc@01c10000 {
 			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c10000 0x1000>;
-			clocks = <&ahb_gates 9>,
-				 <&mmc1_clk 0>,
-				 <&mmc1_clk 1>,
-				 <&mmc1_clk 2>;
+			clocks = <&ccu CLK_AHB_MMC1>,
+				 <&ccu CLK_MMC1>,
+				 <&ccu CLK_MMC1_OUTPUT>,
+				 <&ccu CLK_MMC1_SAMPLE>;
 			clock-names = "ahb",
 				      "mmc",
 				      "output",
@@ -943,10 +384,10 @@
 		mmc2: mmc@01c11000 {
 			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c11000 0x1000>;
-			clocks = <&ahb_gates 10>,
-				 <&mmc2_clk 0>,
-				 <&mmc2_clk 1>,
-				 <&mmc2_clk 2>;
+			clocks = <&ccu CLK_AHB_MMC2>,
+				 <&ccu CLK_MMC2>,
+				 <&ccu CLK_MMC2_OUTPUT>,
+				 <&ccu CLK_MMC2_SAMPLE>;
 			clock-names = "ahb",
 				      "mmc",
 				      "output",
@@ -960,10 +401,10 @@
 		mmc3: mmc@01c12000 {
 			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c12000 0x1000>;
-			clocks = <&ahb_gates 11>,
-				 <&mmc3_clk 0>,
-				 <&mmc3_clk 1>,
-				 <&mmc3_clk 2>;
+			clocks = <&ccu CLK_AHB_MMC3>,
+				 <&ccu CLK_MMC3>,
+				 <&ccu CLK_MMC3_OUTPUT>,
+				 <&ccu CLK_MMC3_SAMPLE>;
 			clock-names = "ahb",
 				      "mmc",
 				      "output",
@@ -977,7 +418,7 @@
 		usb_otg: usb@01c13000 {
 			compatible = "allwinner,sun4i-a10-musb";
 			reg = <0x01c13000 0x0400>;
-			clocks = <&ahb_gates 0>;
+			clocks = <&ccu CLK_AHB_OTG>;
 			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mc";
 			phys = <&usbphy 0>;
@@ -992,9 +433,11 @@
 			compatible = "allwinner,sun7i-a20-usb-phy";
 			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 			reg-names = "phy_ctrl", "pmu1", "pmu2";
-			clocks = <&usb_clk 8>;
+			clocks = <&ccu CLK_USB_PHY>;
 			clock-names = "usb_phy";
-			resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
+			resets = <&ccu RST_USB_PHY0>,
+				 <&ccu RST_USB_PHY1>,
+				 <&ccu RST_USB_PHY2>;
 			reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 			status = "disabled";
 		};
@@ -1003,7 +446,7 @@
 			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 			reg = <0x01c14000 0x100>;
 			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ahb_gates 1>;
+			clocks = <&ccu CLK_AHB_EHCI0>;
 			phys = <&usbphy 1>;
 			phy-names = "usb";
 			status = "disabled";
@@ -1013,7 +456,7 @@
 			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 			reg = <0x01c14400 0x100>;
 			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&usb_clk 6>, <&ahb_gates 2>;
+			clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
 			phys = <&usbphy 1>;
 			phy-names = "usb";
 			status = "disabled";
@@ -1023,7 +466,7 @@
 			compatible = "allwinner,sun4i-a10-crypto";
 			reg = <0x01c15000 0x1000>;
 			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ahb_gates 5>, <&ss_clk>;
+			clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
 			clock-names = "ahb", "mod";
 		};
 
@@ -1031,7 +474,7 @@
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c17000 0x1000>;
 			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ahb_gates 22>, <&spi2_clk>;
+			clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 			clock-names = "ahb", "mod";
 			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 			       <&dma SUN4I_DMA_DEDICATED 28>;
@@ -1046,7 +489,8 @@
 			compatible = "allwinner,sun4i-a10-ahci";
 			reg = <0x01c18000 0x1000>;
 			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&pll6 0>, <&ahb_gates 25>;
+			clocks = <&ccu CLK_PLL_PERIPH_SATA>,
+				 <&ccu CLK_AHB_SATA>;
 			status = "disabled";
 		};
 
@@ -1054,7 +498,7 @@
 			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 			reg = <0x01c1c000 0x100>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ahb_gates 3>;
+			clocks = <&ccu CLK_AHB_EHCI1>;
 			phys = <&usbphy 2>;
 			phy-names = "usb";
 			status = "disabled";
@@ -1064,7 +508,7 @@
 			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 			reg = <0x01c1c400 0x100>;
 			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&usb_clk 7>, <&ahb_gates 4>;
+			clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
 			phys = <&usbphy 2>;
 			phy-names = "usb";
 			status = "disabled";
@@ -1074,7 +518,7 @@
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c1f000 0x1000>;
 			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ahb_gates 23>, <&spi3_clk>;
+			clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
 			clock-names = "ahb", "mod";
 			dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 			       <&dma SUN4I_DMA_DEDICATED 30>;
@@ -1085,11 +529,20 @@
 			num-cs = <1>;
 		};
 
+		ccu: clock@01c20000 {
+			compatible = "allwinner,sun7i-a20-ccu";
+			reg = <0x01c20000 0x400>;
+			clocks = <&osc24M>, <&osc32k>;
+			clock-names = "hosc", "losc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
 		pio: pinctrl@01c20800 {
 			compatible = "allwinner,sun7i-a20-pinctrl";
 			reg = <0x01c20800 0x400>;
 			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
+			clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			interrupt-controller;
@@ -1361,7 +814,7 @@
 			compatible = "allwinner,sun4i-a10-spdif";
 			reg = <0x01c21000 0x400>;
 			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb0_gates 1>, <&spdif_clk>;
+			clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
 			clock-names = "apb", "spdif";
 			dmas = <&dma SUN4I_DMA_NORMAL 2>,
 			       <&dma SUN4I_DMA_NORMAL 2>;
@@ -1371,7 +824,7 @@
 
 		ir0: ir@01c21800 {
 			compatible = "allwinner,sun4i-a10-ir";
-			clocks = <&apb0_gates 6>, <&ir0_clk>;
+			clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
 			clock-names = "apb", "ir";
 			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x01c21800 0x40>;
@@ -1380,7 +833,7 @@
 
 		ir1: ir@01c21c00 {
 			compatible = "allwinner,sun4i-a10-ir";
-			clocks = <&apb0_gates 7>, <&ir1_clk>;
+			clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
 			clock-names = "apb", "ir";
 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x01c21c00 0x40>;
@@ -1392,7 +845,7 @@
 			compatible = "allwinner,sun4i-a10-i2s";
 			reg = <0x01c22000 0x400>;
 			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb0_gates 4>, <&i2s1_clk>;
+			clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
 			clock-names = "apb", "mod";
 			dmas = <&dma SUN4I_DMA_NORMAL 4>,
 			       <&dma SUN4I_DMA_NORMAL 4>;
@@ -1405,7 +858,7 @@
 			compatible = "allwinner,sun4i-a10-i2s";
 			reg = <0x01c22400 0x400>;
 			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb0_gates 3>, <&i2s0_clk>;
+			clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
 			clock-names = "apb", "mod";
 			dmas = <&dma SUN4I_DMA_NORMAL 3>,
 			       <&dma SUN4I_DMA_NORMAL 3>;
@@ -1425,7 +878,7 @@
 			compatible = "allwinner,sun7i-a20-codec";
 			reg = <0x01c22c00 0x40>;
 			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb0_gates 0>, <&codec_clk>;
+			clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
 			clock-names = "apb", "codec";
 			dmas = <&dma SUN4I_DMA_NORMAL 19>,
 			       <&dma SUN4I_DMA_NORMAL 19>;
@@ -1443,7 +896,7 @@
 			compatible = "allwinner,sun4i-a10-i2s";
 			reg = <0x01c24400 0x400>;
 			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb0_gates 8>, <&i2s2_clk>;
+			clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
 			clock-names = "apb", "mod";
 			dmas = <&dma SUN4I_DMA_NORMAL 6>,
 			       <&dma SUN4I_DMA_NORMAL 6>;
@@ -1464,7 +917,7 @@
 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&apb1_gates 16>;
+			clocks = <&ccu CLK_APB1_UART0>;
 			status = "disabled";
 		};
 
@@ -1474,7 +927,7 @@
 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&apb1_gates 17>;
+			clocks = <&ccu CLK_APB1_UART1>;
 			status = "disabled";
 		};
 
@@ -1484,7 +937,7 @@
 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&apb1_gates 18>;
+			clocks = <&ccu CLK_APB1_UART2>;
 			status = "disabled";
 		};
 
@@ -1494,7 +947,7 @@
 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&apb1_gates 19>;
+			clocks = <&ccu CLK_APB1_UART3>;
 			status = "disabled";
 		};
 
@@ -1504,7 +957,7 @@
 			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&apb1_gates 20>;
+			clocks = <&ccu CLK_APB1_UART4>;
 			status = "disabled";
 		};
 
@@ -1514,7 +967,7 @@
 			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&apb1_gates 21>;
+			clocks = <&ccu CLK_APB1_UART5>;
 			status = "disabled";
 		};
 
@@ -1524,7 +977,7 @@
 			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&apb1_gates 22>;
+			clocks = <&ccu CLK_APB1_UART6>;
 			status = "disabled";
 		};
 
@@ -1534,7 +987,7 @@
 			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&apb1_gates 23>;
+			clocks = <&ccu CLK_APB1_UART7>;
 			status = "disabled";
 		};
 
@@ -1543,7 +996,7 @@
 				     "allwinner,sun4i-a10-i2c";
 			reg = <0x01c2ac00 0x400>;
 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb1_gates 0>;
+			clocks = <&ccu CLK_APB1_I2C0>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1554,7 +1007,7 @@
 				     "allwinner,sun4i-a10-i2c";
 			reg = <0x01c2b000 0x400>;
 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb1_gates 1>;
+			clocks = <&ccu CLK_APB1_I2C1>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1565,7 +1018,7 @@
 				     "allwinner,sun4i-a10-i2c";
 			reg = <0x01c2b400 0x400>;
 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb1_gates 2>;
+			clocks = <&ccu CLK_APB1_I2C2>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1576,7 +1029,7 @@
 				     "allwinner,sun4i-a10-i2c";
 			reg = <0x01c2b800 0x400>;
 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb1_gates 3>;
+			clocks = <&ccu CLK_APB1_I2C3>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1587,7 +1040,7 @@
 				     "allwinner,sun4i-a10-i2c";
 			reg = <0x01c2c000 0x400>;
 			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb1_gates 15>;
+			clocks = <&ccu CLK_APB1_I2C4>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -1598,7 +1051,7 @@
 			reg = <0x01c50000 0x10000>;
 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "macirq";
-			clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
+			clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
 			clock-names = "stmmaceth", "allwinner_gmac_tx";
 			snps,pbl = <2>;
 			snps,fixed-burst;
@@ -1615,7 +1068,7 @@
 				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ahb_gates 28>;
+			clocks = <&ccu CLK_AHB_HSTIMER>;
 		};
 
 		gic: interrupt-controller@01c81000 {
@@ -1633,7 +1086,7 @@
 			compatible = "allwinner,sun4i-a10-ps2";
 			reg = <0x01c2a000 0x400>;
 			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb1_gates 6>;
+			clocks = <&ccu CLK_APB1_PS20>;
 			status = "disabled";
 		};
 
@@ -1641,7 +1094,7 @@
 			compatible = "allwinner,sun4i-a10-ps2";
 			reg = <0x01c2a400 0x400>;
 			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&apb1_gates 7>;
+			clocks = <&ccu CLK_APB1_PS21>;
 			status = "disabled";
 		};
 	};
-- 
2.9.3

Re: [PATCH 3/4] ARM: sun7i: Convert to CCU

[Emilio López]

Hi,

I spotted a couple of things here on a quick look, see below

El 27/02/17 a las 18:09, Priit Laes escribió:
> Convert sun7i-a20.dtsi to new CCU driver.
> 
> Signed-off-by: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
> ---
>  arch/arm/boot/dts/sun7i-a20.dtsi | 719 +++++----------------------------------
>  1 file changed, 86 insertions(+), 633 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index 04c9977..6f80cb8 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -47,7 +47,8 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/thermal/thermal.h>
>  
> -#include <dt-bindings/clock/sun4i-a10-pll2.h>
> +#include <dt-bindings/clock/sun7i-ccu.h>
> +#include <dt-bindings/reset/sun7i-ccu.h>
>  #include <dt-bindings/dma/sun4i-a10.h>
>  #include <dt-bindings/pinctrl/sun4i-a10.h>
>  
> @@ -67,19 +68,19 @@
>  			compatible = "allwinner,simple-framebuffer",
>  				     "simple-framebuffer";
>  			allwinner,pipeline = "de_be0-lcd0-hdmi";
> -			clocks = <&ahb_gates 36>, <&ahb_gates 43>,
> -				 <&ahb_gates 44>, <&de_be0_clk>,
> -				 <&tcon0_ch1_clk>, <&dram_gates 26>;
> +			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI1>,
> +				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
> +				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
>  			status = "disabled";
>  		};
>  
> -		framebuffer@1 {
> +		framebuffer@0 {

This looks like an unrelated change

> @@ -184,21 +185,11 @@
>  
>  		osc24M: clk@01c20050 {
>  			#clock-cells = <0>;
> -			compatible = "allwinner,sun4i-a10-osc-clk";
> -			reg = <0x01c20050 0x4>;
> +			compatible = "fixed-clock";
>  			clock-frequency = <24000000>;
>  			clock-output-names = "osc24M";
>  		};

allwinner,sun4i-a10-osc-clk implements a gate apart from a fixed clock,
is the feature loss intended?

Cheers,
Emilio

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Re: [PATCH 3/4] ARM: sun7i: Convert to CCU

[Priit Laes]

On Tue, 2017-02-28 at 14:01 -0300, Emilio López wrote:
> Hi,
> 
> I spotted a couple of things here on a quick look, see below
> 
> El 27/02/17 a las 18:09, Priit Laes escribió:
> > Convert sun7i-a20.dtsi to new CCU driver.
> > 
> > > > Signed-off-by: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
> > ---
> >  arch/arm/boot/dts/sun7i-a20.dtsi | 719 +++++----------------------------------
> >  1 file changed, 86 insertions(+), 633 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> > index 04c9977..6f80cb8 100644
> > --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> > +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> > @@ -47,7 +47,8 @@
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >  #include <dt-bindings/thermal/thermal.h>
> >  
> > -#include <dt-bindings/clock/sun4i-a10-pll2.h>
> > +#include <dt-bindings/clock/sun7i-ccu.h>
> > +#include <dt-bindings/reset/sun7i-ccu.h>
> >  #include <dt-bindings/dma/sun4i-a10.h>
> >  #include <dt-bindings/pinctrl/sun4i-a10.h>
> >  
> > @@ -67,19 +68,19 @@
> > > >  			compatible = "allwinner,simple-framebuffer",
> > > >  				     "simple-framebuffer";
> > > >  			allwinner,pipeline = "de_be0-lcd0-hdmi";
> > > > -			clocks = <&ahb_gates 36>, <&ahb_gates 43>,
> > > > -				 <&ahb_gates 44>, <&de_be0_clk>,
> > > > -				 <&tcon0_ch1_clk>, <&dram_gates 26>;
> > > > +			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI1>,
> > > > +				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
> > > > +				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
> > > >  			status = "disabled";
> > > >  		};
> >  
> > > > -		framebuffer@1 {
> > +		framebuffer@0 {
> 
> This looks like an unrelated change

Yup, that 's leftover from changes made during initial debugging. Will
fix in v2.

> 
> > @@ -184,21 +185,11 @@
> >  
> > > > > >  		osc24M: clk@01c20050 {
> > > >  			#clock-cells = <0>;
> > > > -			compatible = "allwinner,sun4i-a10-osc-clk";
> > > > -			reg = <0x01c20050 0x4>;
> > > > +			compatible = "fixed-clock";
> > > >  			clock-frequency = <24000000>;
> > > >  			clock-output-names = "osc24M";
> >  		};
> 
> allwinner,sun4i-a10-osc-clk implements a gate apart from a fixed clock,
> is the feature loss intended?

This is how most of the existing drivers handle it (A13, A31, A33) so I
didn't want to do anything fancy.. 
Besides, the code for clock actually configures gate:

static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);


Päikest,
Priit 

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[PATCH 4/4] dt-bindings: List devicetree binding for the CCU of Allwinner A20

[Priit Laes]

Allwinner A20 is now driven by sunxi-ng CCU driver.

Add devicetree binding for it.

Signed-off-by: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
---
 Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index bae5668..265262c 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -4,6 +4,7 @@ Allwinner Clock Control Unit Binding
 Required properties :
 - compatible: must contain one of the following compatibles:
 		- "allwinner,sun6i-a31-ccu"
+		- "allwinner,sun7i-a20-ccu"
 		- "allwinner,sun8i-a23-ccu"
 		- "allwinner,sun8i-a33-ccu"
 		- "allwinner,sun8i-h3-ccu"
-- 
2.9.3

Re: [PATCH 4/4] dt-bindings: List devicetree binding for the CCU of Allwinner A20

[Rob Herring]

On Mon, Feb 27, 2017 at 11:09:14PM +0200, Priit Laes wrote:
> Allwinner A20 is now driven by sunxi-ng CCU driver.
> 
> Add devicetree binding for it.
> 
> Signed-off-by: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Re: [PATCH 0/4] ARM: sun7i: Convert sun7i SoC to sunxi-ng

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 600 bytes --]

Hi Priit,

On Mon, Feb 27, 2017 at 11:09:10PM +0200, Priit Laes wrote:
> Hi,
> 
> This is serie brings another SoC into the sunxi-ng world.
> 
> As mentioned in sun5i conversion, this is pretty much standard
> stuff as all the required clocks were already implemented in
> the sunxi-ng framework.

Thanks a lot for that work. I think the A10 should be converted at the
same time, and both would share the same driver.

Fortunately, if I recall properly, both are not too far off.

Thanks again,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: Re: [PATCH 2/4] clk: sunxi-ng: Add sun7i-a20 CCU driver

[Icenowy Zheng]

2017年3月2日 上午5:38于 Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org>写道：
>
> On Tue, 2017-02-28 at 09:21 +0100, Maxime Ripard wrote: 
> > Hi, 
> > 
> > On Mon, Feb 27, 2017 at 11:09:12PM +0200, Priit Laes wrote: 
> > > Introduce a clock controller driver for sun7i A20 SoC. 
> > > 
> > > > > Signed-off-by: Priit Laes <plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org> 
> > > --- 
> > >  drivers/clk/sunxi-ng/Kconfig         |   11 + 
> > >  drivers/clk/sunxi-ng/Makefile        |    1 + 
> > >  drivers/clk/sunxi-ng/ccu-sun7i-a20.c | 1068 ++++++++++++++++++++++++++++++++++ 
> > >  drivers/clk/sunxi-ng/ccu-sun7i-a20.h |  121 ++++ 
> > >  4 files changed, 1201 insertions(+) 
> > >  create mode 100644 drivers/clk/sunxi-ng/ccu-sun7i-a20.c 
> > >  create mode 100644 drivers/clk/sunxi-ng/ccu-sun7i-a20.h 
> > > 
> > > diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig 
> > > index 695bbf9..4f436ab 100644 
> > > --- a/drivers/clk/sunxi-ng/Kconfig 
> > > +++ b/drivers/clk/sunxi-ng/Kconfig 
> > > @@ -85,6 +85,17 @@ config SUN6I_A31_CCU 
> > > > >   select SUNXI_CCU_PHASE 
> > > > >   default MACH_SUN6I 
> > >   
> > > +config SUN7I_A20_CCU 
> > > > > + bool "Support for the Allwinner A20 CCU" 
> > > > > + select SUNXI_CCU_DIV 
> > > > > + select SUNXI_CCU_MULT 
> > > > > + select SUNXI_CCU_NK 
> > > > > + select SUNXI_CCU_NKM 
> > > > > + select SUNXI_CCU_NM 
> > > > > + select SUNXI_CCU_MP 
> > > > > + select SUNXI_CCU_PHASE 
> > > > > + default MACH_SUN7I 
> > > + 
> > >  config SUN8I_A23_CCU 
> > > > >   bool "Support for the Allwinner A23 CCU" 
> > > > >   select SUNXI_CCU_DIV 
> > > diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile 
> > > index 6feaac0..bedda5b 100644 
> > > --- a/drivers/clk/sunxi-ng/Makefile 
> > > +++ b/drivers/clk/sunxi-ng/Makefile 
> > > > > @@ -21,6 +21,7 @@ obj-$(CONFIG_SUNXI_CCU_MP) += ccu_mp.o 
> > > > >  obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o 
> > > > >  obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o 
> > > > >  obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o 
> > > > > +obj-$(CONFIG_SUN7I_A20_CCU) += ccu-sun7i-a20.o 
> > > > >  obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o 
> > > > >  obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o 
> > > > >  obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o 
> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun7i-a20.c b/drivers/clk/sunxi-ng/ccu-sun7i-a20.c 
> > > new file mode 100644 
> > > index 0000000..90d2f13 
> > > --- /dev/null 
> > > +++ b/drivers/clk/sunxi-ng/ccu-sun7i-a20.c 
> > > @@ -0,0 +1,1068 @@ 
> > > +/* 
> > > + * Copyright (c) 2017 Priit Laes. All rights reserved. 
> > > + * 
> > > + * This software is licensed under the terms of the GNU General Public 
> > > + * License version 2, as published by the Free Software Foundation, and 
> > > + * may be copied, distributed, and modified under those terms. 
> > > + * 
> > > + * This program is distributed in the hope that it will be useful, 
> > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of 
> > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
> > > + * GNU General Public License for more details. 
> > > + */ 
> > > + 
> > > +#include <linux/clk-provider.h> 
> > > +#include <linux/of_address.h> 
> > > + 
> > > +#include "ccu_common.h" 
> > > +#include "ccu_reset.h" 
> > > + 
> > > +#include "ccu_div.h" 
> > > +#include "ccu_gate.h" 
> > > +#include "ccu_mp.h" 
> > > +#include "ccu_mult.h" 
> > > +#include "ccu_nk.h" 
> > > +#include "ccu_nkm.h" 
> > > +#include "ccu_nkmp.h" 
> > > +#include "ccu_nm.h" 
> > > +#include "ccu_phase.h" 
> > > + 
> > > +#include "ccu-sun7i-a20.h" 
> > > + 
> > > +/* 
> > > + * PLL1 - Core clock 
> > > + * 
> > > + * TODO: sigma-delta pattern bits 2 & 3 
> > > + * TODO: PLL1 tuning register 
> > 
> > I don't think we need those TODO's at all, and these comments too. If 
> > the clock name is good enough (and it is), it's redundant. 
>
> Ok, will clean them up. 
>
> > 
> > > + */ 
> > > 
> [...] 
> > > +}; 
> > > + 
> > > +/* PLL2 - Audio clock */ 
> > > +static struct ccu_nm pll_audio_base_clk = { 
> > > > > > > + .enable = BIT(31), 
> > > > > > > + .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0), 
> > > > > > > + .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0), 
> > > > > > > + .common = { 
> > > > > > > + .reg = 0x008, 
> > > > > > > + .hw.init = CLK_HW_INIT("pll-audio-base", 
> > > > > +       "hosc", 
> > > > > +       &ccu_nm_ops, 
> > > > > +       0), 
> > > > > + }, 
> > > + 
> > > +}; 
> > 
> > You're forgetting the post-divider here 
>
> It's hardcoded to 4 during ccu initialization, similar to what is done 
> on the other SoCs (A13, A31..). 
>
> > 
> > > +/* TODO: pll8 gpu 0x040 */ 
> > 
> > Please add all the clocks. 
>
> I'm not really comfortable adding clocks for blocks that currently lack 
> drivers. 
>

1. CCU driver should implement all clocks in a CCU, as it may be needed some day.
2. We really have driver for mali, at least kernel part :-)

> > > +/* BIT(21 .. 31) - reserved */ 
> > 
> > I'm not sure we need those comments either. 
> > 
> > > +/* 
> > > + * TODO: SATA clock also supports external clock as parent. 
> > > + * Currently we default to using PLL6 SATA gate. 
> > > + */ 
> > 
> > Which external clock? It should be modelled anyway. If we have a 
> > dependency on some other clock, it should be in our DT binding, and 
> > listed in the mux there. 
> > 
> > Otherwise, the clock framework will not be able to deal with that mux 
> > being already set by the bootloader, and if we need to support that 
> > clock in the future, our binding will be ready for it. 
>
> I wish I knew which clock they're talking about.. 
>
> User manuals (A10/A20) only specify following in the clock register 
> description: 
>
> BIT(24) - CLK_SRC_GATING, default 0x0 
> Clock Source Select: 
> 0: PLL6 for SATA(100MHz) 
> 1: External Clock 
>
> There's no section for SATA (called NC) in A10 manual, and in A20 
> manual only contains list of SATA/AHCI features. 
>
>
> > 
> > > +static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x", 
> > > > > + "pll-periph", 1, 2, CLK_SET_RATE_PARENT); 
> > > +/* We hardcode the divider to 4 for now */ 
> > > +static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 
> > > > > + "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 
> > > +static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 
> > > > > + "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 
> > > +static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 
> > > > > + "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); 
> > > +static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", 
> > > > > + "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); 
> > > +static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", 
> > > > > + "pll-video0", 1, 2, CLK_SET_RATE_PARENT); 
> > > +static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x", 
> > > + "pll-video1", 1, 2, CLK_SET_RATE_PARENT); 
> > 
> > It feels more natural to just have the clocks defined in the same 
> > order than their parents. So periph shouldn't be first 
>
> Ok, will move the periph clock after the video. 
>
> > > +static struct ccu_reset_map sun7i_a20_ccu_resets[] = { 
> > > + 
> > > > > > > + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 
> > > > > > > + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, 
> > > > > > > + [RST_USB_PHY2] = { 0x0cc, BIT(2) }, 
> > > > > > > + [RST_DE_BE0] = { 0x104, BIT(30) }, 
> > > > > > > + [RST_DE_BE1] = { 0x108, BIT(30) }, 
> > > > > > > + [RST_DE_FE0] = { 0x10c, BIT(30) }, 
> > > > > > > + [RST_DE_FE1] = { 0x110, BIT(30) }, 
> > > > > > > + [RST_DE_MP] = { 0x114, BIT(30) }, 
> > > > > > > + [RST_TCON0] = { 0x118, BIT(30) }, 
> > > > > > > + [RST_TCON1] = { 0x11c, BIT(30) }, 
> > > > > > > + [RST_CSI0] = { 0x134, BIT(30) }, 
> > > > > > > + [RST_CSI1] = { 0x138, BIT(30) }, 
> > > > > > > + [RST_VE] = { 0x13c, BIT(0) }, 
> > > > > > > + [RST_ACE] = { 0x148, BIT(16) }, 
> > > > > > > + [RST_LVDS] = { 0x14c, BIT(0) }, 
> > > > > > > + [RST_GPU] = { 0x154, BIT(30) }, 
> > > > > > > + [RST_HDMI_H] = { 0x170, BIT(0) }, 
> > > > > > > + [RST_HDMI_SYS] = { 0x170, BIT(1) }, 
> > > > > > > + [RST_HDMI_AUDIO_DMA] = { 0x170, BIT(2) }, 
> > > +}; 
> > > + 
> > > +static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = { 
> > > > > > > + .ccu_clks = sun7i_a20_ccu_clks, 
> > > > > > > + .num_ccu_clks = ARRAY_SIZE(sun7i_a20_ccu_clks), 
> > > + 
> > > > > > > + .hw_clks = &sun7i_a20_hw_clks, 
> > > + 
> > > > > > > + .resets = sun7i_a20_ccu_resets, 
> > > > > > > + .num_resets = ARRAY_SIZE(sun7i_a20_ccu_resets), 
> > > +}; 
> > > + 
> > > +static void __init sun7i_a20_ccu_setup(struct device_node *node) 
> > > +{ 
> > > > > + void __iomem *reg; 
> > > > > + u32 val; 
> > > + 
> > > > > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 
> > > > > + if (IS_ERR(reg)) { 
> > > > > + pr_err("%s: Could not map the clock registers\n", 
> > > > > +        of_node_full_name(node)); 
> > > > > + return; 
> > > > > + } 
> > > + 
> > > + #define SUN7I_PLL_AUDIO_REG 0x008 
> > 
> > This should be defined above 
>
> Will do.. 
> > 
> > > + 
> > > > > + /* Force the PLL-Audio-1x divider to 4 */ 
> > > > > + val = readl(reg + SUN7I_PLL_AUDIO_REG); 
> > > > > + val &= ~GENMASK(19, 16); 
> > > > > + writel(val | (3 << 16), reg + SUN7I_PLL_AUDIO_REG); 
> > > + 
> > > > > + /* 
> > > > > +  * Use PLL6 as parent for AHB 
> > > +  * CPU/AXI clock changes rate when cpufreq is enabled 
> > 
> > I'm not sure why that last sentence is needed too. A lot of clock 
> > listed there change rate when <some-feature> is enabled. 
>
> Will remove. 
>
> > 
> > > +/* Some AHB gates are exported */ 
> > > > > +#define CLK_AHB_BIST 31 
> > > > > +#define CLK_AHB_MS 36 
> > > > > +#define CLK_AHB_SDRAM 38 
> > > > > +#define CLK_AHB_ACE 39 
> > > > > +#define CLK_AHB_TS 41 
> > > > > +#define CLK_AHB_VE 48 
> > > > > +#define CLK_AHB_TVD 49 
> > > > > +#define CLK_AHB_TVE1 51 
> > > > > +#define CLK_AHB_LCD1 53 
> > > > > +#define CLK_AHB_CSI0 54 
> > > > > +#define CLK_AHB_CSI1 55 
> > > > > +#define CLK_AHB_HDMI0 56 
> > > > > +#define CLK_AHB_DE_BE1 59 
> > > > > +#define CLK_AHB_DE_FE0 60 
> > > > > +#define CLK_AHB_DE_FE1 61 
> > > > > +#define CLK_AHB_MP 63 
> > > > > +#define CLK_AHB_GPU 64 
> > > + 
> > > +/* Some APB0 gates are exported */ 
> > > > > +#define CLK_APB0_AC97 67 
> > > > > +#define CLK_APB0_KEYPAD 74 
> > > + 
> > > +/* Some APB1 gates are exported */ 
> > > > > +#define CLK_APB1_CAN 79 
> > > > > +#define CLK_APB1_SCR 80 
> > > + 
> > > +/* Some IP module clocks are exported */ 
> > > > > +#define CLK_MS 93 
> > > > > +#define CLK_TS 106 
> > > > > +#define CLK_PATA 111 
> > > > > +#define CLK_AC97 115 
> > > > > +#define CLK_KEYPAD 117 
> > > > > +#define CLK_SATA 118 
> > > + 
> > > +/* Some DRAM gates are exported */ 
> > > > > +#define CLK_DRAM_VE 125 
> > > > > +#define CLK_DRAM_CSI0 126 
> > > > > +#define CLK_DRAM_CSI1 127 
> > > > > +#define CLK_DRAM_TS 128 
> > > > > +#define CLK_DRAM_TVD 129 
> > > > > +#define CLK_DRAM_TVE1 131 
> > > > > +#define CLK_DRAM_OUT 132 
> > > > > +#define CLK_DRAM_DE_FE1 133 
> > > > > +#define CLK_DRAM_DE_FE0 134 
> > > > > +#define CLK_DRAM_DE_BE1 136 
> > > > > +#define CLK_DRAM_MP 137 
> > > > > +#define CLK_DRAM_ACE 138 
> > > + 
> > > > > +#define CLK_DE_BE1 140 
> > > > > +#define CLK_DE_FE0 141 
> > > > > +#define CLK_DE_FE1 142 
> > > > > +#define CLK_DE_MP 143 
> > > > > +#define CLK_TCON1_CH0 145 
> > > > > +#define CLK_CSI_SPECIAL 146 
> > > > > +#define CLK_TVD 147 
> > > > > +#define CLK_TCON0_CH1_SCLK2 148 
> > > > > +#define CLK_TCON1_CH1_SCLK2 150 
> > > > > +#define CLK_TCON1_CH1 151 
> > > > > +#define CLK_CSI0 152 
> > > > > +#define CLK_CSI1 153 
> > > > > +#define CLK_VE 154 
> > > > > +#define CLK_AVS 156 
> > > > > +#define CLK_ACE 157 
> > > > > +#define CLK_HDMI 158 
> > > > > +#define CLK_GPU 159 
> > > > > +#define CLK_MBUS 160 
> > > > > +#define CLK_HDMI1_SLOW 161 
> > > > > +#define CLK_HDMI1_REPEAT 162 
> > > > > +#define CLK_OUT_A 163 
> > > +#define CLK_OUT_B 164 
> > 
> > Is there a reason not to expose these clocks? 
>
> I exposed them on need to have basis. And basically did one-to-one 
> conversion from devicetree. 
>
> Päikest, 
> Priit 

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