From: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org,
Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Subject: [PATCH v3 5/9] gpu: ipu-v3: document valid IPUv3 compatibles and extend for i.MX6 QuadPlus
Date: Tue, 14 Mar 2017 11:38:44 +0100 [thread overview]
Message-ID: <1489487928-26083-5-git-send-email-p.zabel@pengutronix.de> (raw)
In-Reply-To: <1489487928-26083-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
From: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Document the valid compatible strings for the IPUv3.
On i.MX6 QuadPlus the IPU needs to know which PRG has to be
used for this IPU instance. Add a "fsl,prg" property containing
a phandle pointing to the correct PRG device.
Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
index 62eb637630b5a..fa01db7eb66c5 100644
--- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
+++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
@@ -21,13 +21,19 @@ Freescale i.MX IPUv3
====================
Required properties:
-- compatible: Should be "fsl,<chip>-ipu"
+- compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
+ - imx51
+ - imx53
+ - imx6q
+ - imx6qp
- reg: should be register base and length as documented in the
datasheet
- interrupts: Should contain sync interrupt and error interrupt,
in this order.
- resets: phandle pointing to the system reset controller and
reset line index, see reset/fsl,imx-src.txt for details
+Additional required properties for fsl,imx6qp-ipu:
+- fsl,prg: phandle to prg node associated with this IPU instance
Optional properties:
- port@[0-3]: Port nodes with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
--
2.11.0
--
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next prev parent reply other threads:[~2017-03-14 10:38 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-14 10:38 [PATCH v3 1/9] gpu: ipu-v3: add DT binding for the Prefetch Resolve Engine Philipp Zabel
[not found] ` <1489487928-26083-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2017-03-14 10:38 ` [PATCH v3 2/9] gpu: ipu-v3: add driver for " Philipp Zabel
2017-03-14 10:38 ` [PATCH v3 3/9] gpu: ipu-v3: add DT binding for the Prefetch Resolve Gasket Philipp Zabel
2017-03-14 10:38 ` [PATCH v3 4/9] gpu: ipu-v3: add driver for " Philipp Zabel
2017-03-14 10:38 ` Philipp Zabel [this message]
2017-03-20 22:12 ` [PATCH v3 5/9] gpu: ipu-v3: document valid IPUv3 compatibles and extend for i.MX6 QuadPlus Rob Herring
2017-03-14 10:38 ` [PATCH v3 7/9] gpu: ipu-v3: only set non-zero AXI ID for IC when PRG is absent Philipp Zabel
2017-03-14 10:38 ` [PATCH v3 8/9] drm/imx: enable/disable PRG on CRTC enable/disable Philipp Zabel
2017-03-14 10:38 ` [PATCH v3 6/9] gpu: ipu-v3: hook up PRG unit Philipp Zabel
2017-03-14 10:38 ` [PATCH v3 9/9] drm/imx: use PRG/PRE when possible Philipp Zabel
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