* [PATCH v2 0/5] STM32 CRC crypto driver
@ 2017-03-21 15:13 Fabien Dessenne
2017-03-21 15:13 ` [PATCH v2 1/5] dt-bindings: Document STM32 CRC bindings Fabien Dessenne
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Fabien Dessenne @ 2017-03-21 15:13 UTC (permalink / raw)
To: Herbert Xu, David S . Miller, Rob Herring, Mark Rutland,
Maxime Coquelin, Alexandre Torgue, Russell King, linux-crypto,
devicetree, linux-arm-kernel
Cc: Benjamin Gaignard
This set of patches adds a new crypto driver for STMicroelectronics stm32f746.
The drivers uses the crypto API and provides with an HW-enabled CRC32 algorithm.
It was developed and tested (tcrypt / testmgr) on evaluation board stm32746g.
v2 changes:
- remove useless check of crc / crc->clk
- enable crypto in stm32 defconfig
- typo fix in dt-bindings
Fabien Dessenne (5):
dt-bindings: Document STM32 CRC bindings
crypto: stm32 - Support for STM32 CRC32 crypto module
ARM: dts: stm32: Add CRC support to stm32f746
ARM: dts: stm32: enable CRC on stm32746g-eval board
ARM: configs: stm32: Add crypto support
.../devicetree/bindings/crypto/st,stm32-crc.txt | 16 +
arch/arm/boot/dts/stm32746g-eval.dts | 4 +
arch/arm/boot/dts/stm32f746.dtsi | 7 +
arch/arm/configs/stm32_defconfig | 2 +
drivers/crypto/Kconfig | 2 +
drivers/crypto/Makefile | 1 +
drivers/crypto/stm32/Kconfig | 8 +
drivers/crypto/stm32/Makefile | 2 +
drivers/crypto/stm32/stm32_crc32.c | 324 +++++++++++++++++++++
9 files changed, 366 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
create mode 100644 drivers/crypto/stm32/Kconfig
create mode 100644 drivers/crypto/stm32/Makefile
create mode 100644 drivers/crypto/stm32/stm32_crc32.c
--
2.7.4
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v2 1/5] dt-bindings: Document STM32 CRC bindings 2017-03-21 15:13 [PATCH v2 0/5] STM32 CRC crypto driver Fabien Dessenne @ 2017-03-21 15:13 ` Fabien Dessenne 2017-03-29 0:28 ` Rob Herring 2017-03-21 15:13 ` [PATCH v2 2/5] crypto: stm32 - Support for STM32 CRC32 crypto module Fabien Dessenne ` (4 subsequent siblings) 5 siblings, 1 reply; 11+ messages in thread From: Fabien Dessenne @ 2017-03-21 15:13 UTC (permalink / raw) To: Herbert Xu, David S . Miller, Rob Herring, Mark Rutland, Maxime Coquelin, Alexandre Torgue, Russell King, linux-crypto, devicetree, linux-arm-kernel Cc: Benjamin Gaignard Document device tree bindings for the STM32 CRC (crypto CRC32) Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> --- .../devicetree/bindings/crypto/st,stm32-crc.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-crc.txt diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt new file mode 100644 index 0000000..3ba92a5 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt @@ -0,0 +1,16 @@ +* STMicroelectronics STM32 CRC + +Required properties: +- compatible: Should be "st,stm32f7-crc". +- reg: The address and length of the peripheral registers space +- clocks: The input clock of the CRC instance + +Optional properties: none + +Example: + +crc: crc@40023000 { + compatible = "st,stm32f7-crc"; + reg = <0x40023000 0x400>; + clocks = <&rcc 0 12>; +}; -- 2.7.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: Document STM32 CRC bindings 2017-03-21 15:13 ` [PATCH v2 1/5] dt-bindings: Document STM32 CRC bindings Fabien Dessenne @ 2017-03-29 0:28 ` Rob Herring 0 siblings, 0 replies; 11+ messages in thread From: Rob Herring @ 2017-03-29 0:28 UTC (permalink / raw) To: Fabien Dessenne Cc: Herbert Xu, David S . Miller, Mark Rutland, Maxime Coquelin, Alexandre Torgue, Russell King, linux-crypto, devicetree, linux-arm-kernel, Benjamin Gaignard On Tue, Mar 21, 2017 at 04:13:27PM +0100, Fabien Dessenne wrote: > Document device tree bindings for the STM32 CRC (crypto CRC32) > > Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> > --- > .../devicetree/bindings/crypto/st,stm32-crc.txt | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-crc.txt Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 2/5] crypto: stm32 - Support for STM32 CRC32 crypto module 2017-03-21 15:13 [PATCH v2 0/5] STM32 CRC crypto driver Fabien Dessenne 2017-03-21 15:13 ` [PATCH v2 1/5] dt-bindings: Document STM32 CRC bindings Fabien Dessenne @ 2017-03-21 15:13 ` Fabien Dessenne 2017-03-24 4:28 ` PrasannaKumar Muralidharan 2017-03-21 15:13 ` [PATCH v2 3/5] ARM: dts: stm32: Add CRC support to stm32f746 Fabien Dessenne ` (3 subsequent siblings) 5 siblings, 1 reply; 11+ messages in thread From: Fabien Dessenne @ 2017-03-21 15:13 UTC (permalink / raw) To: Herbert Xu, David S . Miller, Rob Herring, Mark Rutland, Maxime Coquelin, Alexandre Torgue, Russell King, linux-crypto, devicetree, linux-arm-kernel Cc: Benjamin Gaignard This module registers a CRC32 ("Ethernet") and a CRC32C (Castagnoli) algorithm that make use of the STMicroelectronics STM32 crypto hardware. Theses algorithms are compatible with the little-endian generic ones. Both algorithms use ~0 as default seed (key). With CRC32C the output is xored with ~0. Using TCRYPT CRC32C speed test, this shows up to 900% speedup compared to the crc32c-generic algorithm. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> --- drivers/crypto/Kconfig | 2 + drivers/crypto/Makefile | 1 + drivers/crypto/stm32/Kconfig | 8 + drivers/crypto/stm32/Makefile | 2 + drivers/crypto/stm32/stm32_crc32.c | 324 +++++++++++++++++++++++++++++++++++++ 5 files changed, 337 insertions(+) create mode 100644 drivers/crypto/stm32/Kconfig create mode 100644 drivers/crypto/stm32/Makefile create mode 100644 drivers/crypto/stm32/stm32_crc32.c diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 473d312..922b323 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -619,4 +619,6 @@ config CRYPTO_DEV_BCM_SPU Secure Processing Unit (SPU). The SPU driver registers ablkcipher, ahash, and aead algorithms with the kernel cryptographic API. +source "drivers/crypto/stm32/Kconfig" + endif # CRYPTO_HW diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 7396094..95bf2f9 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/ obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/ obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o +obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32/ obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/ obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/ diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig new file mode 100644 index 0000000..792335b --- /dev/null +++ b/drivers/crypto/stm32/Kconfig @@ -0,0 +1,8 @@ +config CRYPTO_DEV_STM32 + tristate "Support for STM32 crypto accelerators" + depends on ARCH_STM32 + select CRYPTO_HASH + help + This enables support for the CRC32 hw accelerator which can be found + on STMicroelectronis STM32 SOC. + diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile new file mode 100644 index 0000000..73b4c6e --- /dev/null +++ b/drivers/crypto/stm32/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32_cryp.o +stm32_cryp-objs := stm32_crc32.o diff --git a/drivers/crypto/stm32/stm32_crc32.c b/drivers/crypto/stm32/stm32_crc32.c new file mode 100644 index 0000000..7652822 --- /dev/null +++ b/drivers/crypto/stm32/stm32_crc32.c @@ -0,0 +1,324 @@ +/* + * Copyright (C) STMicroelectronics SA 2017 + * Author: Fabien Dessenne <fabien.dessenne@st.com> + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/bitrev.h> +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include <crypto/internal/hash.h> + +#include <asm/unaligned.h> + +#define DRIVER_NAME "stm32-crc32" +#define CHKSUM_DIGEST_SIZE 4 +#define CHKSUM_BLOCK_SIZE 1 + +/* Registers */ +#define CRC_DR 0x00000000 +#define CRC_CR 0x00000008 +#define CRC_INIT 0x00000010 +#define CRC_POL 0x00000014 + +/* Registers values */ +#define CRC_CR_RESET BIT(0) +#define CRC_CR_REVERSE (BIT(7) | BIT(6) | BIT(5)) +#define CRC_INIT_DEFAULT 0xFFFFFFFF + +/* Polynomial reversed */ +#define POLY_CRC32 0xEDB88320 +#define POLY_CRC32C 0x82F63B78 + +struct stm32_crc { + struct list_head list; + struct device *dev; + void __iomem *regs; + struct clk *clk; + u8 pending_data[sizeof(u32)]; + size_t nb_pending_bytes; +}; + +struct stm32_crc_list { + struct list_head dev_list; + spinlock_t lock; /* protect dev_list */ +}; + +static struct stm32_crc_list crc_list = { + .dev_list = LIST_HEAD_INIT(crc_list.dev_list), + .lock = __SPIN_LOCK_UNLOCKED(crc_list.lock), +}; + +struct stm32_crc_ctx { + u32 key; + u32 poly; +}; + +struct stm32_crc_desc_ctx { + u32 partial; /* crc32c: partial in first 4 bytes of that struct */ + struct stm32_crc *crc; +}; + +static int stm32_crc32_cra_init(struct crypto_tfm *tfm) +{ + struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm); + + mctx->key = CRC_INIT_DEFAULT; + mctx->poly = POLY_CRC32; + return 0; +} + +static int stm32_crc32c_cra_init(struct crypto_tfm *tfm) +{ + struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm); + + mctx->key = CRC_INIT_DEFAULT; + mctx->poly = POLY_CRC32C; + return 0; +} + +static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key, + unsigned int keylen) +{ + struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm); + + if (keylen != sizeof(u32)) { + crypto_shash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); + return -EINVAL; + } + + mctx->key = get_unaligned_le32(key); + return 0; +} + +static int stm32_crc_init(struct shash_desc *desc) +{ + struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc); + struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm); + struct stm32_crc *crc; + + spin_lock_bh(&crc_list.lock); + list_for_each_entry(crc, &crc_list.dev_list, list) { + ctx->crc = crc; + break; + } + spin_unlock_bh(&crc_list.lock); + + /* Reset, set key, poly and configure in bit reverse mode */ + writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT); + writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL); + writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR); + + /* Store partial result */ + ctx->partial = readl(ctx->crc->regs + CRC_DR); + ctx->crc->nb_pending_bytes = 0; + + return 0; +} + +static int stm32_crc_update(struct shash_desc *desc, const u8 *d8, + unsigned int length) +{ + struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc); + struct stm32_crc *crc = ctx->crc; + u32 *d32; + unsigned int i; + + if (unlikely(crc->nb_pending_bytes)) { + while (crc->nb_pending_bytes != sizeof(u32) && length) { + /* Fill in pending data */ + crc->pending_data[crc->nb_pending_bytes++] = *(d8++); + length--; + } + + if (crc->nb_pending_bytes == sizeof(u32)) { + /* Process completed pending data */ + writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR); + crc->nb_pending_bytes = 0; + } + } + + d32 = (u32 *)d8; + for (i = 0; i < length >> 2; i++) + /* Process 32 bits data */ + writel(*(d32++), crc->regs + CRC_DR); + + /* Store partial result */ + ctx->partial = readl(crc->regs + CRC_DR); + + /* Check for pending data (non 32 bits) */ + length &= 3; + if (likely(!length)) + return 0; + + if ((crc->nb_pending_bytes + length) >= sizeof(u32)) { + /* Shall not happen */ + dev_err(crc->dev, "Pending data overflow\n"); + return -EINVAL; + } + + d8 = (const u8 *)d32; + for (i = 0; i < length; i++) + /* Store pending data */ + crc->pending_data[crc->nb_pending_bytes++] = *(d8++); + + return 0; +} + +static int stm32_crc_final(struct shash_desc *desc, u8 *out) +{ + struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc); + struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm); + + /* Send computed CRC */ + put_unaligned_le32(mctx->poly == POLY_CRC32C ? + ~ctx->partial : ctx->partial, out); + + return 0; +} + +static int stm32_crc_finup(struct shash_desc *desc, const u8 *data, + unsigned int length, u8 *out) +{ + return stm32_crc_update(desc, data, length) ?: + stm32_crc_final(desc, out); +} + +static int stm32_crc_digest(struct shash_desc *desc, const u8 *data, + unsigned int length, u8 *out) +{ + return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out); +} + +static struct shash_alg algs[] = { + /* CRC-32 */ + { + .setkey = stm32_crc_setkey, + .init = stm32_crc_init, + .update = stm32_crc_update, + .final = stm32_crc_final, + .finup = stm32_crc_finup, + .digest = stm32_crc_digest, + .descsize = sizeof(struct stm32_crc_desc_ctx), + .digestsize = CHKSUM_DIGEST_SIZE, + .base = { + .cra_name = "crc32", + .cra_driver_name = DRIVER_NAME, + .cra_priority = 200, + .cra_blocksize = CHKSUM_BLOCK_SIZE, + .cra_alignmask = 3, + .cra_ctxsize = sizeof(struct stm32_crc_ctx), + .cra_module = THIS_MODULE, + .cra_init = stm32_crc32_cra_init, + } + }, + /* CRC-32Castagnoli */ + { + .setkey = stm32_crc_setkey, + .init = stm32_crc_init, + .update = stm32_crc_update, + .final = stm32_crc_final, + .finup = stm32_crc_finup, + .digest = stm32_crc_digest, + .descsize = sizeof(struct stm32_crc_desc_ctx), + .digestsize = CHKSUM_DIGEST_SIZE, + .base = { + .cra_name = "crc32c", + .cra_driver_name = DRIVER_NAME, + .cra_priority = 200, + .cra_blocksize = CHKSUM_BLOCK_SIZE, + .cra_alignmask = 3, + .cra_ctxsize = sizeof(struct stm32_crc_ctx), + .cra_module = THIS_MODULE, + .cra_init = stm32_crc32c_cra_init, + } + } +}; + +static int stm32_crc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct stm32_crc *crc; + struct resource *res; + int ret; + + crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL); + if (!crc) + return -ENOMEM; + + crc->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + crc->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(crc->regs)) { + dev_err(dev, "Cannot map CRC IO\n"); + return PTR_ERR(crc->regs); + } + + crc->clk = devm_clk_get(dev, NULL); + if (IS_ERR(crc->clk)) { + dev_err(dev, "Could not get clock\n"); + return PTR_ERR(crc->clk); + } + + ret = clk_prepare_enable(crc->clk); + if (ret) { + dev_err(crc->dev, "Failed to enable clock\n"); + return ret; + } + + platform_set_drvdata(pdev, crc); + + spin_lock(&crc_list.lock); + list_add(&crc->list, &crc_list.dev_list); + spin_unlock(&crc_list.lock); + + ret = crypto_register_shashes(algs, ARRAY_SIZE(algs)); + if (ret) { + dev_err(dev, "Failed to register\n"); + clk_disable_unprepare(crc->clk); + return ret; + } + + dev_info(dev, "Initialized\n"); + + return 0; +} + +static int stm32_crc_remove(struct platform_device *pdev) +{ + struct stm32_crc *crc = platform_get_drvdata(pdev); + + spin_lock(&crc_list.lock); + list_del(&crc->list); + spin_unlock(&crc_list.lock); + + crypto_unregister_shash(algs); + + clk_disable_unprepare(crc->clk); + + return 0; +} + +static const struct of_device_id stm32_dt_ids[] = { + { .compatible = "st,stm32f7-crc", }, + {}, +}; +MODULE_DEVICE_TABLE(of, sti_dt_ids); + +static struct platform_driver stm32_crc_driver = { + .probe = stm32_crc_probe, + .remove = stm32_crc_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = stm32_dt_ids, + }, +}; + +module_platform_driver(stm32_crc_driver); + +MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); +MODULE_DESCRIPTION("STMicrolectronics STM32 CRC32 hardware driver"); +MODULE_LICENSE("GPL"); -- 2.7.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/5] crypto: stm32 - Support for STM32 CRC32 crypto module 2017-03-21 15:13 ` [PATCH v2 2/5] crypto: stm32 - Support for STM32 CRC32 crypto module Fabien Dessenne @ 2017-03-24 4:28 ` PrasannaKumar Muralidharan 2017-03-24 9:56 ` Fabien DESSENNE 0 siblings, 1 reply; 11+ messages in thread From: PrasannaKumar Muralidharan @ 2017-03-24 4:28 UTC (permalink / raw) To: Fabien Dessenne Cc: Herbert Xu, David S . Miller, Rob Herring, Mark Rutland, Maxime Coquelin, Alexandre Torgue, Russell King, linux-crypto, devicetree, linux-arm-kernel, Benjamin Gaignard On 21 March 2017 at 20:43, Fabien Dessenne <fabien.dessenne@st.com> wrote: > This module registers a CRC32 ("Ethernet") and a CRC32C (Castagnoli) > algorithm that make use of the STMicroelectronics STM32 crypto hardware. > > Theses algorithms are compatible with the little-endian generic ones. > Both algorithms use ~0 as default seed (key). > With CRC32C the output is xored with ~0. > > Using TCRYPT CRC32C speed test, this shows up to 900% speedup compared > to the crc32c-generic algorithm. Comparing with crc3c-generic alogrithm does not sound like a good metric for someone who has to decide between hw crypto or not. Wouldn't it be better if the comparison is between crc32 using NEON with hw crypto module? It will help in choosing between hw crypto or arch optimised crc routiene. > Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> > --- > drivers/crypto/Kconfig | 2 + > drivers/crypto/Makefile | 1 + > drivers/crypto/stm32/Kconfig | 8 + > drivers/crypto/stm32/Makefile | 2 + > drivers/crypto/stm32/stm32_crc32.c | 324 +++++++++++++++++++++++++++++++++++++ > 5 files changed, 337 insertions(+) > create mode 100644 drivers/crypto/stm32/Kconfig > create mode 100644 drivers/crypto/stm32/Makefile > create mode 100644 drivers/crypto/stm32/stm32_crc32.c > > diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig > index 473d312..922b323 100644 > --- a/drivers/crypto/Kconfig > +++ b/drivers/crypto/Kconfig > @@ -619,4 +619,6 @@ config CRYPTO_DEV_BCM_SPU > Secure Processing Unit (SPU). The SPU driver registers ablkcipher, > ahash, and aead algorithms with the kernel cryptographic API. > > +source "drivers/crypto/stm32/Kconfig" > + > endif # CRYPTO_HW > diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile > index 7396094..95bf2f9 100644 > --- a/drivers/crypto/Makefile > +++ b/drivers/crypto/Makefile > @@ -30,6 +30,7 @@ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/ > obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/ > obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o > obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o > +obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32/ > obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/ > obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o > obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/ > diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig > new file mode 100644 > index 0000000..792335b > --- /dev/null > +++ b/drivers/crypto/stm32/Kconfig > @@ -0,0 +1,8 @@ > +config CRYPTO_DEV_STM32 > + tristate "Support for STM32 crypto accelerators" > + depends on ARCH_STM32 > + select CRYPTO_HASH > + help > + This enables support for the CRC32 hw accelerator which can be found > + on STMicroelectronis STM32 SOC. > + > diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile > new file mode 100644 > index 0000000..73b4c6e > --- /dev/null > +++ b/drivers/crypto/stm32/Makefile > @@ -0,0 +1,2 @@ > +obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32_cryp.o > +stm32_cryp-objs := stm32_crc32.o > diff --git a/drivers/crypto/stm32/stm32_crc32.c b/drivers/crypto/stm32/stm32_crc32.c > new file mode 100644 > index 0000000..7652822 > --- /dev/null > +++ b/drivers/crypto/stm32/stm32_crc32.c > @@ -0,0 +1,324 @@ > +/* > + * Copyright (C) STMicroelectronics SA 2017 > + * Author: Fabien Dessenne <fabien.dessenne@st.com> > + * License terms: GNU General Public License (GPL), version 2 > + */ > + > +#include <linux/bitrev.h> > +#include <linux/clk.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > + > +#include <crypto/internal/hash.h> > + > +#include <asm/unaligned.h> > + > +#define DRIVER_NAME "stm32-crc32" > +#define CHKSUM_DIGEST_SIZE 4 > +#define CHKSUM_BLOCK_SIZE 1 > + > +/* Registers */ > +#define CRC_DR 0x00000000 > +#define CRC_CR 0x00000008 > +#define CRC_INIT 0x00000010 > +#define CRC_POL 0x00000014 > + > +/* Registers values */ > +#define CRC_CR_RESET BIT(0) > +#define CRC_CR_REVERSE (BIT(7) | BIT(6) | BIT(5)) > +#define CRC_INIT_DEFAULT 0xFFFFFFFF > + > +/* Polynomial reversed */ > +#define POLY_CRC32 0xEDB88320 > +#define POLY_CRC32C 0x82F63B78 > + > +struct stm32_crc { > + struct list_head list; > + struct device *dev; > + void __iomem *regs; > + struct clk *clk; > + u8 pending_data[sizeof(u32)]; > + size_t nb_pending_bytes; > +}; > + > +struct stm32_crc_list { > + struct list_head dev_list; > + spinlock_t lock; /* protect dev_list */ > +}; > + > +static struct stm32_crc_list crc_list = { > + .dev_list = LIST_HEAD_INIT(crc_list.dev_list), > + .lock = __SPIN_LOCK_UNLOCKED(crc_list.lock), > +}; > + > +struct stm32_crc_ctx { > + u32 key; > + u32 poly; > +}; > + > +struct stm32_crc_desc_ctx { > + u32 partial; /* crc32c: partial in first 4 bytes of that struct */ > + struct stm32_crc *crc; > +}; > + > +static int stm32_crc32_cra_init(struct crypto_tfm *tfm) > +{ > + struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm); > + > + mctx->key = CRC_INIT_DEFAULT; > + mctx->poly = POLY_CRC32; > + return 0; > +} > + > +static int stm32_crc32c_cra_init(struct crypto_tfm *tfm) > +{ > + struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm); > + > + mctx->key = CRC_INIT_DEFAULT; > + mctx->poly = POLY_CRC32C; > + return 0; > +} > + > +static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key, > + unsigned int keylen) > +{ > + struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm); > + > + if (keylen != sizeof(u32)) { > + crypto_shash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); > + return -EINVAL; > + } > + > + mctx->key = get_unaligned_le32(key); > + return 0; > +} > + > +static int stm32_crc_init(struct shash_desc *desc) > +{ > + struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc); > + struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm); > + struct stm32_crc *crc; > + > + spin_lock_bh(&crc_list.lock); > + list_for_each_entry(crc, &crc_list.dev_list, list) { > + ctx->crc = crc; > + break; > + } > + spin_unlock_bh(&crc_list.lock); > + > + /* Reset, set key, poly and configure in bit reverse mode */ > + writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT); > + writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL); > + writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR); > + > + /* Store partial result */ > + ctx->partial = readl(ctx->crc->regs + CRC_DR); > + ctx->crc->nb_pending_bytes = 0; > + > + return 0; > +} > + > +static int stm32_crc_update(struct shash_desc *desc, const u8 *d8, > + unsigned int length) > +{ > + struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc); > + struct stm32_crc *crc = ctx->crc; > + u32 *d32; > + unsigned int i; > + > + if (unlikely(crc->nb_pending_bytes)) { > + while (crc->nb_pending_bytes != sizeof(u32) && length) { > + /* Fill in pending data */ > + crc->pending_data[crc->nb_pending_bytes++] = *(d8++); > + length--; > + } > + > + if (crc->nb_pending_bytes == sizeof(u32)) { > + /* Process completed pending data */ > + writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR); > + crc->nb_pending_bytes = 0; > + } > + } > + > + d32 = (u32 *)d8; > + for (i = 0; i < length >> 2; i++) > + /* Process 32 bits data */ > + writel(*(d32++), crc->regs + CRC_DR); > + > + /* Store partial result */ > + ctx->partial = readl(crc->regs + CRC_DR); > + > + /* Check for pending data (non 32 bits) */ > + length &= 3; > + if (likely(!length)) > + return 0; > + > + if ((crc->nb_pending_bytes + length) >= sizeof(u32)) { > + /* Shall not happen */ > + dev_err(crc->dev, "Pending data overflow\n"); > + return -EINVAL; > + } > + > + d8 = (const u8 *)d32; > + for (i = 0; i < length; i++) > + /* Store pending data */ > + crc->pending_data[crc->nb_pending_bytes++] = *(d8++); > + > + return 0; > +} > + > +static int stm32_crc_final(struct shash_desc *desc, u8 *out) > +{ > + struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc); > + struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm); > + > + /* Send computed CRC */ > + put_unaligned_le32(mctx->poly == POLY_CRC32C ? > + ~ctx->partial : ctx->partial, out); > + > + return 0; > +} > + > +static int stm32_crc_finup(struct shash_desc *desc, const u8 *data, > + unsigned int length, u8 *out) > +{ > + return stm32_crc_update(desc, data, length) ?: > + stm32_crc_final(desc, out); > +} > + > +static int stm32_crc_digest(struct shash_desc *desc, const u8 *data, > + unsigned int length, u8 *out) > +{ > + return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out); > +} > + > +static struct shash_alg algs[] = { > + /* CRC-32 */ > + { > + .setkey = stm32_crc_setkey, > + .init = stm32_crc_init, > + .update = stm32_crc_update, > + .final = stm32_crc_final, > + .finup = stm32_crc_finup, > + .digest = stm32_crc_digest, > + .descsize = sizeof(struct stm32_crc_desc_ctx), > + .digestsize = CHKSUM_DIGEST_SIZE, > + .base = { > + .cra_name = "crc32", > + .cra_driver_name = DRIVER_NAME, > + .cra_priority = 200, > + .cra_blocksize = CHKSUM_BLOCK_SIZE, > + .cra_alignmask = 3, > + .cra_ctxsize = sizeof(struct stm32_crc_ctx), > + .cra_module = THIS_MODULE, > + .cra_init = stm32_crc32_cra_init, > + } > + }, > + /* CRC-32Castagnoli */ > + { > + .setkey = stm32_crc_setkey, > + .init = stm32_crc_init, > + .update = stm32_crc_update, > + .final = stm32_crc_final, > + .finup = stm32_crc_finup, > + .digest = stm32_crc_digest, > + .descsize = sizeof(struct stm32_crc_desc_ctx), > + .digestsize = CHKSUM_DIGEST_SIZE, > + .base = { > + .cra_name = "crc32c", > + .cra_driver_name = DRIVER_NAME, > + .cra_priority = 200, > + .cra_blocksize = CHKSUM_BLOCK_SIZE, > + .cra_alignmask = 3, > + .cra_ctxsize = sizeof(struct stm32_crc_ctx), > + .cra_module = THIS_MODULE, > + .cra_init = stm32_crc32c_cra_init, > + } > + } > +}; Will be better if the priority is based on benchmark result. ARM arch optimised crc32 also defines its priority as 200. Choose a higher priority if the hw crypto is either faster or consumes less power. Regards, PrasannaKumar ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/5] crypto: stm32 - Support for STM32 CRC32 crypto module 2017-03-24 4:28 ` PrasannaKumar Muralidharan @ 2017-03-24 9:56 ` Fabien DESSENNE 2017-03-24 10:00 ` PrasannaKumar Muralidharan 0 siblings, 1 reply; 11+ messages in thread From: Fabien DESSENNE @ 2017-03-24 9:56 UTC (permalink / raw) To: PrasannaKumar Muralidharan Cc: Mark Rutland, devicetree@vger.kernel.org, Alexandre TORGUE, Russell King, Rob Herring, linux-crypto@vger.kernel.org, Maxime Coquelin, Benjamin GAIGNARD, David S . Miller, linux-arm-kernel@lists.infradead.org, Herbert Xu On 24/03/17 05:28, PrasannaKumar Muralidharan wrote: > On 21 March 2017 at 20:43, Fabien Dessenne <fabien.dessenne@st.com> wrote: >> This module registers a CRC32 ("Ethernet") and a CRC32C (Castagnoli) >> algorithm that make use of the STMicroelectronics STM32 crypto hardware. >> >> Theses algorithms are compatible with the little-endian generic ones. >> Both algorithms use ~0 as default seed (key). >> With CRC32C the output is xored with ~0. >> >> Using TCRYPT CRC32C speed test, this shows up to 900% speedup compared >> to the crc32c-generic algorithm. > Comparing with crc3c-generic alogrithm does not sound like a good > metric for someone who has to decide between hw crypto or not. > Wouldn't it be better if the comparison is between crc32 using NEON > with hw crypto module? It will help in choosing between hw crypto or > arch optimised crc routiene. The STM32 microcontrollers are based on ARM Cortex-M7 (or older core) that do not have NEON support. Moreover, the purpose of this introduction is not to provide with a (full) benchmark. It just gives a hint of the HW performance. >> Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> >> --- >> drivers/crypto/Kconfig | 2 + >> drivers/crypto/Makefile | 1 + >> drivers/crypto/stm32/Kconfig | 8 + >> drivers/crypto/stm32/Makefile | 2 + >> drivers/crypto/stm32/stm32_crc32.c | 324 +++++++++++++++++++++++++++++++++++++ >> 5 files changed, 337 insertions(+) >> create mode 100644 drivers/crypto/stm32/Kconfig >> create mode 100644 drivers/crypto/stm32/Makefile >> create mode 100644 drivers/crypto/stm32/stm32_crc32.c >> >> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig >> index 473d312..922b323 100644 >> --- a/drivers/crypto/Kconfig >> +++ b/drivers/crypto/Kconfig >> @@ -619,4 +619,6 @@ config CRYPTO_DEV_BCM_SPU >> Secure Processing Unit (SPU). The SPU driver registers ablkcipher, >> ahash, and aead algorithms with the kernel cryptographic API. >> >> +source "drivers/crypto/stm32/Kconfig" >> + >> endif # CRYPTO_HW >> diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile >> index 7396094..95bf2f9 100644 >> --- a/drivers/crypto/Makefile >> +++ b/drivers/crypto/Makefile >> @@ -30,6 +30,7 @@ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/ >> obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/ >> obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o >> obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o >> +obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32/ >> obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/ >> obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o >> obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/ >> diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig >> new file mode 100644 >> index 0000000..792335b >> --- /dev/null >> +++ b/drivers/crypto/stm32/Kconfig >> @@ -0,0 +1,8 @@ >> +config CRYPTO_DEV_STM32 >> + tristate "Support for STM32 crypto accelerators" >> + depends on ARCH_STM32 >> + select CRYPTO_HASH >> + help >> + This enables support for the CRC32 hw accelerator which can be found >> + on STMicroelectronis STM32 SOC. >> + >> diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile >> new file mode 100644 >> index 0000000..73b4c6e >> --- /dev/null >> +++ b/drivers/crypto/stm32/Makefile >> @@ -0,0 +1,2 @@ >> +obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32_cryp.o >> +stm32_cryp-objs := stm32_crc32.o >> diff --git a/drivers/crypto/stm32/stm32_crc32.c b/drivers/crypto/stm32/stm32_crc32.c >> new file mode 100644 >> index 0000000..7652822 >> --- /dev/null >> +++ b/drivers/crypto/stm32/stm32_crc32.c >> @@ -0,0 +1,324 @@ >> +/* >> + * Copyright (C) STMicroelectronics SA 2017 >> + * Author: Fabien Dessenne <fabien.dessenne@st.com> >> + * License terms: GNU General Public License (GPL), version 2 >> + */ >> + >> +#include <linux/bitrev.h> >> +#include <linux/clk.h> >> +#include <linux/module.h> >> +#include <linux/platform_device.h> >> + >> +#include <crypto/internal/hash.h> >> + >> +#include <asm/unaligned.h> >> + >> +#define DRIVER_NAME "stm32-crc32" >> +#define CHKSUM_DIGEST_SIZE 4 >> +#define CHKSUM_BLOCK_SIZE 1 >> + >> +/* Registers */ >> +#define CRC_DR 0x00000000 >> +#define CRC_CR 0x00000008 >> +#define CRC_INIT 0x00000010 >> +#define CRC_POL 0x00000014 >> + >> +/* Registers values */ >> +#define CRC_CR_RESET BIT(0) >> +#define CRC_CR_REVERSE (BIT(7) | BIT(6) | BIT(5)) >> +#define CRC_INIT_DEFAULT 0xFFFFFFFF >> + >> +/* Polynomial reversed */ >> +#define POLY_CRC32 0xEDB88320 >> +#define POLY_CRC32C 0x82F63B78 >> + >> +struct stm32_crc { >> + struct list_head list; >> + struct device *dev; >> + void __iomem *regs; >> + struct clk *clk; >> + u8 pending_data[sizeof(u32)]; >> + size_t nb_pending_bytes; >> +}; >> + >> +struct stm32_crc_list { >> + struct list_head dev_list; >> + spinlock_t lock; /* protect dev_list */ >> +}; >> + >> +static struct stm32_crc_list crc_list = { >> + .dev_list = LIST_HEAD_INIT(crc_list.dev_list), >> + .lock = __SPIN_LOCK_UNLOCKED(crc_list.lock), >> +}; >> + >> +struct stm32_crc_ctx { >> + u32 key; >> + u32 poly; >> +}; >> + >> +struct stm32_crc_desc_ctx { >> + u32 partial; /* crc32c: partial in first 4 bytes of that struct */ >> + struct stm32_crc *crc; >> +}; >> + >> +static int stm32_crc32_cra_init(struct crypto_tfm *tfm) >> +{ >> + struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm); >> + >> + mctx->key = CRC_INIT_DEFAULT; >> + mctx->poly = POLY_CRC32; >> + return 0; >> +} >> + >> +static int stm32_crc32c_cra_init(struct crypto_tfm *tfm) >> +{ >> + struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm); >> + >> + mctx->key = CRC_INIT_DEFAULT; >> + mctx->poly = POLY_CRC32C; >> + return 0; >> +} >> + >> +static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key, >> + unsigned int keylen) >> +{ >> + struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm); >> + >> + if (keylen != sizeof(u32)) { >> + crypto_shash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); >> + return -EINVAL; >> + } >> + >> + mctx->key = get_unaligned_le32(key); >> + return 0; >> +} >> + >> +static int stm32_crc_init(struct shash_desc *desc) >> +{ >> + struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc); >> + struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm); >> + struct stm32_crc *crc; >> + >> + spin_lock_bh(&crc_list.lock); >> + list_for_each_entry(crc, &crc_list.dev_list, list) { >> + ctx->crc = crc; >> + break; >> + } >> + spin_unlock_bh(&crc_list.lock); >> + >> + /* Reset, set key, poly and configure in bit reverse mode */ >> + writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT); >> + writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL); >> + writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR); >> + >> + /* Store partial result */ >> + ctx->partial = readl(ctx->crc->regs + CRC_DR); >> + ctx->crc->nb_pending_bytes = 0; >> + >> + return 0; >> +} >> + >> +static int stm32_crc_update(struct shash_desc *desc, const u8 *d8, >> + unsigned int length) >> +{ >> + struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc); >> + struct stm32_crc *crc = ctx->crc; >> + u32 *d32; >> + unsigned int i; >> + >> + if (unlikely(crc->nb_pending_bytes)) { >> + while (crc->nb_pending_bytes != sizeof(u32) && length) { >> + /* Fill in pending data */ >> + crc->pending_data[crc->nb_pending_bytes++] = *(d8++); >> + length--; >> + } >> + >> + if (crc->nb_pending_bytes == sizeof(u32)) { >> + /* Process completed pending data */ >> + writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR); >> + crc->nb_pending_bytes = 0; >> + } >> + } >> + >> + d32 = (u32 *)d8; >> + for (i = 0; i < length >> 2; i++) >> + /* Process 32 bits data */ >> + writel(*(d32++), crc->regs + CRC_DR); >> + >> + /* Store partial result */ >> + ctx->partial = readl(crc->regs + CRC_DR); >> + >> + /* Check for pending data (non 32 bits) */ >> + length &= 3; >> + if (likely(!length)) >> + return 0; >> + >> + if ((crc->nb_pending_bytes + length) >= sizeof(u32)) { >> + /* Shall not happen */ >> + dev_err(crc->dev, "Pending data overflow\n"); >> + return -EINVAL; >> + } >> + >> + d8 = (const u8 *)d32; >> + for (i = 0; i < length; i++) >> + /* Store pending data */ >> + crc->pending_data[crc->nb_pending_bytes++] = *(d8++); >> + >> + return 0; >> +} >> + >> +static int stm32_crc_final(struct shash_desc *desc, u8 *out) >> +{ >> + struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc); >> + struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm); >> + >> + /* Send computed CRC */ >> + put_unaligned_le32(mctx->poly == POLY_CRC32C ? >> + ~ctx->partial : ctx->partial, out); >> + >> + return 0; >> +} >> + >> +static int stm32_crc_finup(struct shash_desc *desc, const u8 *data, >> + unsigned int length, u8 *out) >> +{ >> + return stm32_crc_update(desc, data, length) ?: >> + stm32_crc_final(desc, out); >> +} >> + >> +static int stm32_crc_digest(struct shash_desc *desc, const u8 *data, >> + unsigned int length, u8 *out) >> +{ >> + return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out); >> +} >> + >> +static struct shash_alg algs[] = { >> + /* CRC-32 */ >> + { >> + .setkey = stm32_crc_setkey, >> + .init = stm32_crc_init, >> + .update = stm32_crc_update, >> + .final = stm32_crc_final, >> + .finup = stm32_crc_finup, >> + .digest = stm32_crc_digest, >> + .descsize = sizeof(struct stm32_crc_desc_ctx), >> + .digestsize = CHKSUM_DIGEST_SIZE, >> + .base = { >> + .cra_name = "crc32", >> + .cra_driver_name = DRIVER_NAME, >> + .cra_priority = 200, >> + .cra_blocksize = CHKSUM_BLOCK_SIZE, >> + .cra_alignmask = 3, >> + .cra_ctxsize = sizeof(struct stm32_crc_ctx), >> + .cra_module = THIS_MODULE, >> + .cra_init = stm32_crc32_cra_init, >> + } >> + }, >> + /* CRC-32Castagnoli */ >> + { >> + .setkey = stm32_crc_setkey, >> + .init = stm32_crc_init, >> + .update = stm32_crc_update, >> + .final = stm32_crc_final, >> + .finup = stm32_crc_finup, >> + .digest = stm32_crc_digest, >> + .descsize = sizeof(struct stm32_crc_desc_ctx), >> + .digestsize = CHKSUM_DIGEST_SIZE, >> + .base = { >> + .cra_name = "crc32c", >> + .cra_driver_name = DRIVER_NAME, >> + .cra_priority = 200, >> + .cra_blocksize = CHKSUM_BLOCK_SIZE, >> + .cra_alignmask = 3, >> + .cra_ctxsize = sizeof(struct stm32_crc_ctx), >> + .cra_module = THIS_MODULE, >> + .cra_init = stm32_crc32c_cra_init, >> + } >> + } >> +}; > Will be better if the priority is based on benchmark result. ARM arch > optimised crc32 also defines its priority as 200. Choose a higher > priority if the hw crypto is either faster or consumes less power. > > Regards, > PrasannaKumar ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/5] crypto: stm32 - Support for STM32 CRC32 crypto module 2017-03-24 9:56 ` Fabien DESSENNE @ 2017-03-24 10:00 ` PrasannaKumar Muralidharan 0 siblings, 0 replies; 11+ messages in thread From: PrasannaKumar Muralidharan @ 2017-03-24 10:00 UTC (permalink / raw) To: Fabien DESSENNE Cc: Mark Rutland, devicetree@vger.kernel.org, Alexandre TORGUE, Russell King, Rob Herring, linux-crypto@vger.kernel.org, Maxime Coquelin, Benjamin GAIGNARD, David S . Miller, linux-arm-kernel@lists.infradead.org, Herbert Xu On 24 March 2017 at 15:26, Fabien DESSENNE <fabien.dessenne@st.com> wrote: > On 24/03/17 05:28, PrasannaKumar Muralidharan wrote: >> On 21 March 2017 at 20:43, Fabien Dessenne <fabien.dessenne@st.com> wrote: >>> This module registers a CRC32 ("Ethernet") and a CRC32C (Castagnoli) >>> algorithm that make use of the STMicroelectronics STM32 crypto hardware. >>> >>> Theses algorithms are compatible with the little-endian generic ones. >>> Both algorithms use ~0 as default seed (key). >>> With CRC32C the output is xored with ~0. >>> >>> Using TCRYPT CRC32C speed test, this shows up to 900% speedup compared >>> to the crc32c-generic algorithm. >> Comparing with crc3c-generic alogrithm does not sound like a good >> metric for someone who has to decide between hw crypto or not. >> Wouldn't it be better if the comparison is between crc32 using NEON >> with hw crypto module? It will help in choosing between hw crypto or >> arch optimised crc routiene. > > The STM32 microcontrollers are based on ARM Cortex-M7 (or older core) > that do not have NEON support. I was not aware of the absence of NEON support. Sorry for the noise. ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 3/5] ARM: dts: stm32: Add CRC support to stm32f746 2017-03-21 15:13 [PATCH v2 0/5] STM32 CRC crypto driver Fabien Dessenne 2017-03-21 15:13 ` [PATCH v2 1/5] dt-bindings: Document STM32 CRC bindings Fabien Dessenne 2017-03-21 15:13 ` [PATCH v2 2/5] crypto: stm32 - Support for STM32 CRC32 crypto module Fabien Dessenne @ 2017-03-21 15:13 ` Fabien Dessenne 2017-03-21 15:13 ` [PATCH v2 4/5] ARM: dts: stm32: enable CRC on stm32746g-eval board Fabien Dessenne ` (2 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: Fabien Dessenne @ 2017-03-21 15:13 UTC (permalink / raw) To: Herbert Xu, David S . Miller, Rob Herring, Mark Rutland, Maxime Coquelin, Alexandre Torgue, Russell King, linux-crypto, devicetree, linux-arm-kernel Cc: Benjamin Gaignard Add CRC (CRC32 crypto) support to stm32f746. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> --- arch/arm/boot/dts/stm32f746.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index f321ffe..755fb92 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -289,6 +289,13 @@ }; }; + crc: crc@40023000 { + compatible = "st,stm32f7-crc"; + reg = <0x40023000 0x400>; + clocks = <&rcc 0 12>; + status = "disabled"; + }; + rcc: rcc@40023800 { #clock-cells = <2>; compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; -- 2.7.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 4/5] ARM: dts: stm32: enable CRC on stm32746g-eval board 2017-03-21 15:13 [PATCH v2 0/5] STM32 CRC crypto driver Fabien Dessenne ` (2 preceding siblings ...) 2017-03-21 15:13 ` [PATCH v2 3/5] ARM: dts: stm32: Add CRC support to stm32f746 Fabien Dessenne @ 2017-03-21 15:13 ` Fabien Dessenne 2017-03-21 15:13 ` [PATCH v2 5/5] ARM: configs: stm32: Add crypto support Fabien Dessenne 2017-04-05 14:09 ` [PATCH v2 0/5] STM32 CRC crypto driver Herbert Xu 5 siblings, 0 replies; 11+ messages in thread From: Fabien Dessenne @ 2017-03-21 15:13 UTC (permalink / raw) To: Herbert Xu, David S . Miller, Rob Herring, Mark Rutland, Maxime Coquelin, Alexandre Torgue, Russell King, linux-crypto, devicetree, linux-arm-kernel Cc: Benjamin Gaignard Enable the CRC (CRC32 crypto) on stm32746g-eval board Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> --- arch/arm/boot/dts/stm32746g-eval.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index aa03fac..0dc18a0 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -89,6 +89,10 @@ clock-frequency = <25000000>; }; +&crc { + status = "okay"; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; -- 2.7.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 5/5] ARM: configs: stm32: Add crypto support 2017-03-21 15:13 [PATCH v2 0/5] STM32 CRC crypto driver Fabien Dessenne ` (3 preceding siblings ...) 2017-03-21 15:13 ` [PATCH v2 4/5] ARM: dts: stm32: enable CRC on stm32746g-eval board Fabien Dessenne @ 2017-03-21 15:13 ` Fabien Dessenne 2017-04-05 14:09 ` [PATCH v2 0/5] STM32 CRC crypto driver Herbert Xu 5 siblings, 0 replies; 11+ messages in thread From: Fabien Dessenne @ 2017-03-21 15:13 UTC (permalink / raw) To: Herbert Xu, David S . Miller, Rob Herring, Mark Rutland, Maxime Coquelin, Alexandre Torgue, Russell King, linux-crypto, devicetree, linux-arm-kernel Cc: Benjamin Gaignard Add STM32 crypto support in stm32_defconfig file. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> --- arch/arm/configs/stm32_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index a9d8e3c..03437f8 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -75,5 +75,7 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_FTRACE is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_DEV_STM32=y CONFIG_CRC_ITU_T=y CONFIG_CRC7=y -- 2.7.4 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 0/5] STM32 CRC crypto driver 2017-03-21 15:13 [PATCH v2 0/5] STM32 CRC crypto driver Fabien Dessenne ` (4 preceding siblings ...) 2017-03-21 15:13 ` [PATCH v2 5/5] ARM: configs: stm32: Add crypto support Fabien Dessenne @ 2017-04-05 14:09 ` Herbert Xu 5 siblings, 0 replies; 11+ messages in thread From: Herbert Xu @ 2017-04-05 14:09 UTC (permalink / raw) To: Fabien Dessenne Cc: David S . Miller, Rob Herring, Mark Rutland, Maxime Coquelin, Alexandre Torgue, Russell King, linux-crypto, devicetree, linux-arm-kernel, Benjamin Gaignard On Tue, Mar 21, 2017 at 04:13:26PM +0100, Fabien Dessenne wrote: > This set of patches adds a new crypto driver for STMicroelectronics stm32f746. > The drivers uses the crypto API and provides with an HW-enabled CRC32 algorithm. > It was developed and tested (tcrypt / testmgr) on evaluation board stm32746g. > > v2 changes: > - remove useless check of crc / crc->clk > - enable crypto in stm32 defconfig > - typo fix in dt-bindings All applied. Thanks. -- Email: Herbert Xu <herbert@gondor.apana.org.au> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2017-04-05 14:09 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-03-21 15:13 [PATCH v2 0/5] STM32 CRC crypto driver Fabien Dessenne 2017-03-21 15:13 ` [PATCH v2 1/5] dt-bindings: Document STM32 CRC bindings Fabien Dessenne 2017-03-29 0:28 ` Rob Herring 2017-03-21 15:13 ` [PATCH v2 2/5] crypto: stm32 - Support for STM32 CRC32 crypto module Fabien Dessenne 2017-03-24 4:28 ` PrasannaKumar Muralidharan 2017-03-24 9:56 ` Fabien DESSENNE 2017-03-24 10:00 ` PrasannaKumar Muralidharan 2017-03-21 15:13 ` [PATCH v2 3/5] ARM: dts: stm32: Add CRC support to stm32f746 Fabien Dessenne 2017-03-21 15:13 ` [PATCH v2 4/5] ARM: dts: stm32: enable CRC on stm32746g-eval board Fabien Dessenne 2017-03-21 15:13 ` [PATCH v2 5/5] ARM: configs: stm32: Add crypto support Fabien Dessenne 2017-04-05 14:09 ` [PATCH v2 0/5] STM32 CRC crypto driver Herbert Xu
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