[PATCH v4 0/4] RK3399 dw-mipi-dsi patches

[PATCH v4 0/4] RK3399 dw-mipi-dsi patches

[Chris Zhong]

Hi all

This series set the phy_cfg_clk to be a required clock for RK3399, and
add a grf clock control in dw-mipi-dsi driver. And then correct a
register name.


Changes in v4:
- remove "additional"
- print the err after clk_prepare_enable(dsi->grf_clk)

Changes in v3:
- add a DW_MIPI_NEEDS_PHY_CFG_CLK for RK3399
- add a DW_MIPI_NEEDS_GRF_CLK for RK3399

Changes in v2:
- check the grf_clk only for RK3399

Chris Zhong (4):
  drm/rockchip/dsi: check phy_cfg_clk only for RK3399
  dt-bindings: add the grf clock for dw-mipi-dsi
  drm/rockchip/dsi: enable the grf clk before writing grf registers
  drm/rockchip/dsi: correct the grf_switch_reg name

 .../display/rockchip/dw_mipi_dsi_rockchip.txt      |  2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c             | 42 +++++++++++++++++-----
 2 files changed, 35 insertions(+), 9 deletions(-)

-- 
2.6.3

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[PATCH v4 2/4] dt-bindings: add the grf clock for dw-mipi-dsi

[Chris Zhong]

For RK3399, the grf clock should be controlled by dw-mipi-dsi driver,
add the description for this clock.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---

Changes in v4:
- remove "additional"

Changes in v3: None
Changes in v2: None

 .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 188f6f7..1d722f5 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -10,7 +10,7 @@ Required properties:
 - interrupts: Represent the controller's interrupt to the CPU(s).
 - clocks, clock-names: Phandles to the controller's pll reference
   clock(ref) and APB clock(pclk). For RK3399, a phy config clock
-  (phy_cfg) is additional required. As described in [1].
+  (phy_cfg) and a grf clock(grf) are required. As described in [1].
 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
 - ports: contain a port node with endpoint definitions as defined in [2].
   For vopb,set the reg = <0> and set the reg = <1> for vopl.
-- 
2.6.3

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Re: [PATCH v4 2/4] dt-bindings: add the grf clock for dw-mipi-dsi

[Rob Herring]

On Wed, Mar 22, 2017 at 09:54:49AM +0800, Chris Zhong wrote:
> For RK3399, the grf clock should be controlled by dw-mipi-dsi driver,
> add the description for this clock.
> 
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> Reviewed-by: Sean Paul <seanpaul@chromium.org>
> ---
> 
> Changes in v4:
> - remove "additional"
> 
> Changes in v3: None
> Changes in v2: None
> 
>  .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt       | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Rob Herring <robh@kernel.org>
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Re: [PATCH v4 0/4] RK3399 dw-mipi-dsi patches

[Sean Paul]

On Wed, Mar 22, 2017 at 09:54:47AM +0800, Chris Zhong wrote:
> Hi all
> 
> This series set the phy_cfg_clk to be a required clock for RK3399, and
> add a grf clock control in dw-mipi-dsi driver. And then correct a
> register name.
> 

Applied to drm-misc

Thanks,

Sean


> 
> Changes in v4:
> - remove "additional"
> - print the err after clk_prepare_enable(dsi->grf_clk)
> 
> Changes in v3:
> - add a DW_MIPI_NEEDS_PHY_CFG_CLK for RK3399
> - add a DW_MIPI_NEEDS_GRF_CLK for RK3399
> 
> Changes in v2:
> - check the grf_clk only for RK3399
> 
> Chris Zhong (4):
>   drm/rockchip/dsi: check phy_cfg_clk only for RK3399
>   dt-bindings: add the grf clock for dw-mipi-dsi
>   drm/rockchip/dsi: enable the grf clk before writing grf registers
>   drm/rockchip/dsi: correct the grf_switch_reg name
> 
>  .../display/rockchip/dw_mipi_dsi_rockchip.txt      |  2 +-
>  drivers/gpu/drm/rockchip/dw-mipi-dsi.c             | 42 +++++++++++++++++-----
>  2 files changed, 35 insertions(+), 9 deletions(-)
> 
> -- 
> 2.6.3
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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