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* [PATCH 3/6] dt-bindings: serial: fsl-lpuart: add i.MX7ULP support
       [not found] <1494316248-24052-1-git-send-email-aisheng.dong@nxp.com>
@ 2017-05-09  7:50 ` Dong Aisheng
       [not found]   ` <1494316248-24052-4-git-send-email-aisheng.dong-3arQi8VN3Tc@public.gmane.org>
  0 siblings, 1 reply; 2+ messages in thread
From: Dong Aisheng @ 2017-05-09  7:50 UTC (permalink / raw)
  To: linux-serial
  Cc: linux-kernel, linux-arm-kernel, gregkh, jslaby, fugang.duan,
	stefan, Mingkai.Hu, yangbo.lu, Dong Aisheng, devicetree,
	Rob Herring

The lpuart of imx7ulp is basically the same as ls1021a. It's also
32 bit width register, but unlike ls1021a, it's little endian.
Besides that, imx7ulp lpuart has a minor different register layout
from ls1021a.

Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.com>
Cc: Fugang Duan <fugang.duan@nxp.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Mingkai Hu <Mingkai.Hu@nxp.com>
Cc: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
index c95005e..a1252a0 100644
--- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
+++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
@@ -6,6 +6,8 @@ Required properties:
     on Vybrid vf610 SoC with 8-bit register organization
   - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated
     on LS1021A SoC with 32-bit big-endian register organization
+  - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated
+    on i.MX7ULP SoC with 32-bit little-endian register organization
 - reg : Address and length of the register set for the device
 - interrupts : Should contain uart interrupt
 - clocks : phandle + clock specifier pairs, one for each entry in clock-names
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH 3/6] dt-bindings: serial: fsl-lpuart: add i.MX7ULP support
       [not found]   ` <1494316248-24052-4-git-send-email-aisheng.dong-3arQi8VN3Tc@public.gmane.org>
@ 2017-05-12 20:12     ` Rob Herring
  0 siblings, 0 replies; 2+ messages in thread
From: Rob Herring @ 2017-05-12 20:12 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: linux-serial-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, jslaby-IBi9RG/b67k,
	fugang.duan-3arQi8VN3Tc, stefan-XLVq0VzYD2Y,
	Mingkai.Hu-3arQi8VN3Tc, yangbo.lu-3arQi8VN3Tc,
	devicetree-u79uwXL29TY76Z2rM5mHXA

On Tue, May 09, 2017 at 03:50:45PM +0800, Dong Aisheng wrote:
> The lpuart of imx7ulp is basically the same as ls1021a. It's also
> 32 bit width register, but unlike ls1021a, it's little endian.
> Besides that, imx7ulp lpuart has a minor different register layout
> from ls1021a.
> 
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
> Cc: Jiri Slaby <jslaby-IBi9RG/b67k@public.gmane.org>
> Cc: Fugang Duan <fugang.duan-3arQi8VN3Tc@public.gmane.org>
> Cc: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org>
> Cc: Mingkai Hu <Mingkai.Hu-3arQi8VN3Tc@public.gmane.org>
> Cc: Yangbo Lu <yangbo.lu-3arQi8VN3Tc@public.gmane.org>
> Signed-off-by: Dong Aisheng <aisheng.dong-3arQi8VN3Tc@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 2 ++
>  1 file changed, 2 insertions(+)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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2017-05-09  7:50 ` [PATCH 3/6] dt-bindings: serial: fsl-lpuart: add i.MX7ULP support Dong Aisheng
     [not found]   ` <1494316248-24052-4-git-send-email-aisheng.dong-3arQi8VN3Tc@public.gmane.org>
2017-05-12 20:12     ` Rob Herring

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