* [PATCH v3 02/11] dt-bindings: clk: Extend binding doc for Stingray SOC
[not found] ` <1494934256-1350-1-git-send-email-anup.patel-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
@ 2017-05-16 11:30 ` Anup Patel
2017-05-16 11:30 ` [PATCH v3 03/11] clk: bcm: Add clocks " Anup Patel
` (4 subsequent siblings)
5 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2017-05-16 11:30 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Michael Turquette
Cc: Catalin Marinas, Will Deacon, Ray Jui, Scott Branden, Jon Mason,
Florian Fainelli, Oza Pawandeep, Srinath Mannam, Pramod Kumar,
Sandeep Tripathy, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w
From: Sandeep Tripathy <sandeep.tripathy-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Update iproc clock dt-binding documentation with
Stingray pll and clock details.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Reviewed-by: Ray Jui <ray.jui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Reviewed-by: Scott Branden <scott.branden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
.../bindings/clock/brcm,iproc-clocks.txt | 76 ++++++++++++++++
include/dt-bindings/clock/bcm-sr.h | 101 +++++++++++++++++++++
2 files changed, 177 insertions(+)
create mode 100644 include/dt-bindings/clock/bcm-sr.h
diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
index 6f66e9a..f2c5f0e4a 100644
--- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
@@ -219,3 +219,79 @@ BCM63138
--------
PLL and leaf clock compatible strings for BCM63138 are:
"brcm,bcm63138-armpll"
+
+Stingray
+-----------
+PLL and leaf clock compatible strings for Stingray are:
+ "brcm,sr-genpll0"
+ "brcm,sr-genpll1"
+ "brcm,sr-genpll2"
+ "brcm,sr-genpll3"
+ "brcm,sr-genpll4"
+ "brcm,sr-genpll5"
+ "brcm,sr-genpll6"
+
+ "brcm,sr-lcpll0"
+ "brcm,sr-lcpll1"
+ "brcm,sr-lcpll-pcie"
+
+
+The following table defines the set of PLL/clock index and ID for Stingray.
+These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-sr.h"
+
+ Clock Source Index ID
+ --- ----- ----- ---------
+ crystal N/A N/A N/A
+ crmu_ref25m crystal N/A N/A
+
+ genpll0 crystal 0 BCM_SR_GENPLL0
+ clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
+ clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
+ clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
+ clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
+ clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
+ clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
+
+ genpll1 crystal 0 BCM_SR_GENPLL1
+ clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
+ clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
+
+ genpll2 crystal 0 BCM_SR_GENPLL2
+ clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
+ clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
+ clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
+ clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
+ clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH
+
+ genpll3 crystal 0 BCM_SR_GENPLL3
+ clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
+ clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
+
+ genpll4 crystal 0 BCM_SR_GENPLL4
+ ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
+ clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
+ noc_clk genpll4 3 BCM_SR_GENPLL4_NOC_CLK
+ clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
+ clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
+
+
+ genpll5 crystal 0 BCM_SR_GENPLL5
+ fs4_hf_clk genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
+ crypto_ae_clk genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
+ raid_ae_clk genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
+
+ genpll6 crystal 0 BCM_SR_GENPLL6
+ 48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
+
+ lcpll0 crystal 0 BCM_SR_LCPLL0
+ clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
+ clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
+ clk_usb_ref lcpll0 3 BCM_SR_LCPLL0_USB_REF_CLK
+ sata_refpn lcpll0 3 BCM_SR_LCPLL0_SATA_REFPN_CLK
+
+ lcpll1 crystal 0 BCM_SR_LCPLL1
+ wan lcpll1 1 BCM_SR_LCPLL0_WAN_CLK
+
+ lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
+ pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
diff --git a/include/dt-bindings/clock/bcm-sr.h b/include/dt-bindings/clock/bcm-sr.h
new file mode 100644
index 0000000..cff6c6f
--- /dev/null
+++ b/include/dt-bindings/clock/bcm-sr.h
@@ -0,0 +1,101 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_SR_H
+#define _CLOCK_BCM_SR_H
+
+/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
+#define BCM_SR_GENPLL0 0
+#define BCM_SR_GENPLL0_SATA_CLK 1
+#define BCM_SR_GENPLL0_SCR_CLK 2
+#define BCM_SR_GENPLL0_250M_CLK 3
+#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
+#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 5
+#define BCM_SR_GENPLL0_PAXC_AXI_CLK 6
+
+/* GENPLL 1 clock channel ID MHB PCIE NITRO */
+#define BCM_SR_GENPLL1 0
+#define BCM_SR_GENPLL1_PCIE_TL_CLK 1
+#define BCM_SR_GENPLL1_MHB_APB_CLK 2
+
+/* GENPLL 2 clock channel ID NITRO MHB*/
+#define BCM_SR_GENPLL2 0
+#define BCM_SR_GENPLL2_NIC_CLK 1
+#define BCM_SR_GENPLL2_250_NITRO_CLK 2
+#define BCM_SR_GENPLL2_125_NITRO_CLK 3
+#define BCM_SR_GENPLL2_CHIMP_CLK 4
+
+/* GENPLL 3 HSLS clock channel ID */
+#define BCM_SR_GENPLL3 0
+#define BCM_SR_GENPLL3_HSLS_CLK 1
+#define BCM_SR_GENPLL3_SDIO_CLK 2
+
+/* GENPLL 4 SCR clock channel ID */
+#define BCM_SR_GENPLL4 0
+#define BCM_SR_GENPLL4_CCN_CLK 1
+
+/* GENPLL 5 FS4 clock channel ID */
+#define BCM_SR_GENPLL5 0
+#define BCM_SR_GENPLL5_FS_CLK 1
+#define BCM_SR_GENPLL5_SPU_CLK 2
+
+/* GENPLL 6 NITRO clock channel ID */
+#define BCM_SR_GENPLL6 0
+#define BCM_SR_GENPLL6_48_USB_CLK 1
+
+/* LCPLL0 clock channel ID */
+#define BCM_SR_LCPLL0 0
+#define BCM_SR_LCPLL0_SATA_REF_CLK 1
+#define BCM_SR_LCPLL0_USB_REF_CLK 2
+#define BCM_SR_LCPLL0_SATA_REFPN_CLK 3
+
+/* LCPLL1 clock channel ID */
+#define BCM_SR_LCPLL1 0
+#define BCM_SR_LCPLL1_WAN_CLK 1
+
+/* LCPLL PCIE clock channel ID */
+#define BCM_SR_LCPLL_PCIE 0
+#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL0 0
+#define BCM_SR_EMEMPLL0_EMEM_CLK 1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL1 0
+#define BCM_SR_EMEMPLL1_EMEM_CLK 1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL2 0
+#define BCM_SR_EMEMPLL2_EMEM_CLK 1
+
+#endif /* _CLOCK_BCM_SR_H */
--
2.7.4
--
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 03/11] clk: bcm: Add clocks for Stingray SOC
[not found] ` <1494934256-1350-1-git-send-email-anup.patel-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2017-05-16 11:30 ` [PATCH v3 02/11] dt-bindings: clk: Extend binding doc for Stingray SOC Anup Patel
@ 2017-05-16 11:30 ` Anup Patel
2017-05-16 11:30 ` [PATCH v3 04/11] arm64: dts: Initial DTS files for Broadcom " Anup Patel
` (3 subsequent siblings)
5 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2017-05-16 11:30 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Michael Turquette
Cc: Catalin Marinas, Will Deacon, Ray Jui, Scott Branden, Jon Mason,
Florian Fainelli, Oza Pawandeep, Srinath Mannam, Pramod Kumar,
Sandeep Tripathy, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w
From: Sandeep Tripathy <sandeep.tripathy-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
This patch adds support for Stingray clocks in iproc
ccf. The Stingray SOC has various plls based on iproc
pll architecture.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Reviewed-by: Ray Jui <ray.jui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Reviewed-by: Scott Branden <scott.branden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
drivers/clk/bcm/Kconfig | 8 ++
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-sr.c | 300 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 309 insertions(+)
create mode 100644 drivers/clk/bcm/clk-sr.c
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index b5ae531..1d9187d 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -46,3 +46,11 @@ config CLK_BCM_NS2
default ARCH_BCM_IPROC
help
Enable common clock framework support for the Broadcom Northstar 2 SoC
+
+config CLK_BCM_SR
+ bool "Broadcom Stingray clock support"
+ depends on ARCH_BCM_IPROC || COMPILE_TEST
+ select COMMON_CLK_IPROC
+ default ARCH_BCM_IPROC
+ help
+ Enable common clock framework support for the Broadcom Stingray SoC
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index d9dc848..a0c14fa 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_ARCH_BCM_53573) += clk-bcm53573-ilp.o
obj-$(CONFIG_CLK_BCM_CYGNUS) += clk-cygnus.o
obj-$(CONFIG_CLK_BCM_NSP) += clk-nsp.o
obj-$(CONFIG_CLK_BCM_NS2) += clk-ns2.o
+obj-$(CONFIG_CLK_BCM_SR) += clk-sr.o
diff --git a/drivers/clk/bcm/clk-sr.c b/drivers/clk/bcm/clk-sr.c
new file mode 100644
index 0000000..0ef08cf
--- /dev/null
+++ b/drivers/clk/bcm/clk-sr.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright 2017 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation (the "GPL").
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License version 2 (GPLv2) for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * version 2 (GPLv2) along with this source code.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/bcm-sr.h>
+#include "clk-iproc.h"
+
+#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
+
+#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
+ .pwr_shift = ps, .iso_shift = is }
+
+#define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }
+
+#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
+ .p_reset_shift = prs }
+
+#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
+ .ka_width = kaw }
+
+#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
+
+#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
+ .hold_shift = hs, .bypass_shift = bs }
+
+
+static const struct iproc_pll_ctrl genpll0 = {
+ .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
+ IPROC_CLK_PLL_NEEDS_SW_CFG,
+ .aon = AON_VAL(0x0, 5, 1, 0),
+ .reset = RESET_VAL(0x0, 12, 11),
+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
+ .sw_ctrl = SW_CTRL_VAL(0x10, 31),
+ .ndiv_int = REG_VAL(0x10, 20, 10),
+ .ndiv_frac = REG_VAL(0x10, 0, 20),
+ .pdiv = REG_VAL(0x14, 0, 4),
+ .status = REG_VAL(0x30, 12, 1),
+};
+
+static const struct iproc_clk_ctrl genpll0_clk[] = {
+ [BCM_SR_GENPLL0_SATA_CLK] = {
+ .channel = BCM_SR_GENPLL0_SATA_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 6, 0, 12),
+ .mdiv = REG_VAL(0x18, 0, 9),
+ },
+ [BCM_SR_GENPLL0_SCR_CLK] = {
+ .channel = BCM_SR_GENPLL0_SCR_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 7, 1, 13),
+ .mdiv = REG_VAL(0x18, 10, 9),
+ },
+ [BCM_SR_GENPLL0_250M_CLK] = {
+ .channel = BCM_SR_GENPLL0_250M_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 8, 2, 14),
+ .mdiv = REG_VAL(0x18, 20, 9),
+ },
+ [BCM_SR_GENPLL0_PCIE_AXI_CLK] = {
+ .channel = BCM_SR_GENPLL0_PCIE_AXI_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 9, 3, 15),
+ .mdiv = REG_VAL(0x1c, 0, 9),
+ },
+ [BCM_SR_GENPLL0_PAXC_AXI_X2_CLK] = {
+ .channel = BCM_SR_GENPLL0_PAXC_AXI_X2_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 10, 4, 16),
+ .mdiv = REG_VAL(0x1c, 10, 9),
+ },
+ [BCM_SR_GENPLL0_PAXC_AXI_CLK] = {
+ .channel = BCM_SR_GENPLL0_PAXC_AXI_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 11, 5, 17),
+ .mdiv = REG_VAL(0x1c, 20, 9),
+ },
+};
+
+static void __init sr_genpll0_clk_init(struct device_node *node)
+{
+ iproc_pll_clk_setup(node, &genpll0, NULL, 0, genpll0_clk,
+ ARRAY_SIZE(genpll0_clk));
+}
+CLK_OF_DECLARE(sr_genpll0_clk, "brcm,sr-genpll0",
+ sr_genpll0_clk_init);
+
+static const struct iproc_pll_ctrl genpll3 = {
+ .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
+ IPROC_CLK_PLL_NEEDS_SW_CFG,
+ .aon = AON_VAL(0x0, 1, 19, 18),
+ .reset = RESET_VAL(0x0, 12, 11),
+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
+ .sw_ctrl = SW_CTRL_VAL(0x10, 31),
+ .ndiv_int = REG_VAL(0x10, 20, 10),
+ .ndiv_frac = REG_VAL(0x10, 0, 20),
+ .pdiv = REG_VAL(0x14, 0, 4),
+ .status = REG_VAL(0x30, 12, 1),
+};
+
+static const struct iproc_clk_ctrl genpll3_clk[] = {
+ [BCM_SR_GENPLL3_HSLS_CLK] = {
+ .channel = BCM_SR_GENPLL3_HSLS_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 6, 0, 12),
+ .mdiv = REG_VAL(0x18, 0, 9),
+ },
+ [BCM_SR_GENPLL3_SDIO_CLK] = {
+ .channel = BCM_SR_GENPLL3_SDIO_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 7, 1, 13),
+ .mdiv = REG_VAL(0x18, 10, 9),
+ },
+};
+
+static void __init sr_genpll3_clk_init(struct device_node *node)
+{
+ iproc_pll_clk_setup(node, &genpll3, NULL, 0, genpll3_clk,
+ ARRAY_SIZE(genpll3_clk));
+}
+CLK_OF_DECLARE(sr_genpll3_clk, "brcm,sr-genpll3",
+ sr_genpll3_clk_init);
+
+static const struct iproc_pll_ctrl genpll4 = {
+ .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
+ IPROC_CLK_PLL_NEEDS_SW_CFG,
+ .aon = AON_VAL(0x0, 1, 25, 24),
+ .reset = RESET_VAL(0x0, 12, 11),
+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
+ .sw_ctrl = SW_CTRL_VAL(0x10, 31),
+ .ndiv_int = REG_VAL(0x10, 20, 10),
+ .ndiv_frac = REG_VAL(0x10, 0, 20),
+ .pdiv = REG_VAL(0x14, 0, 4),
+ .status = REG_VAL(0x30, 12, 1),
+};
+
+static const struct iproc_clk_ctrl genpll4_clk[] = {
+ [BCM_SR_GENPLL4_CCN_CLK] = {
+ .channel = BCM_SR_GENPLL4_CCN_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 6, 0, 12),
+ .mdiv = REG_VAL(0x18, 0, 9),
+ },
+};
+
+static void __init sr_genpll4_clk_init(struct device_node *node)
+{
+ iproc_pll_clk_setup(node, &genpll4, NULL, 0, genpll4_clk,
+ ARRAY_SIZE(genpll4_clk));
+}
+CLK_OF_DECLARE(sr_genpll4_clk, "brcm,sr-genpll4",
+ sr_genpll4_clk_init);
+
+static const struct iproc_pll_ctrl genpll5 = {
+ .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
+ IPROC_CLK_PLL_NEEDS_SW_CFG,
+ .aon = AON_VAL(0x0, 1, 1, 0),
+ .reset = RESET_VAL(0x0, 12, 11),
+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
+ .sw_ctrl = SW_CTRL_VAL(0x10, 31),
+ .ndiv_int = REG_VAL(0x10, 20, 10),
+ .ndiv_frac = REG_VAL(0x10, 0, 20),
+ .pdiv = REG_VAL(0x14, 0, 4),
+ .status = REG_VAL(0x30, 12, 1),
+};
+
+static const struct iproc_clk_ctrl genpll5_clk[] = {
+ [BCM_SR_GENPLL5_FS_CLK] = {
+ .channel = BCM_SR_GENPLL5_FS_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 6, 0, 12),
+ .mdiv = REG_VAL(0x18, 0, 9),
+ },
+ [BCM_SR_GENPLL5_SPU_CLK] = {
+ .channel = BCM_SR_GENPLL5_SPU_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x4, 6, 0, 12),
+ .mdiv = REG_VAL(0x18, 10, 9),
+ },
+};
+
+static void __init sr_genpll5_clk_init(struct device_node *node)
+{
+ iproc_pll_clk_setup(node, &genpll5, NULL, 0, genpll5_clk,
+ ARRAY_SIZE(genpll5_clk));
+}
+CLK_OF_DECLARE(sr_genpll5_clk, "brcm,sr-genpll5",
+ sr_genpll5_clk_init);
+
+static const struct iproc_pll_ctrl lcpll0 = {
+ .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
+ .aon = AON_VAL(0x0, 2, 19, 18),
+ .reset = RESET_VAL(0x0, 31, 30),
+ .sw_ctrl = SW_CTRL_VAL(0x4, 31),
+ .ndiv_int = REG_VAL(0x4, 16, 10),
+ .pdiv = REG_VAL(0x4, 26, 4),
+ .status = REG_VAL(0x38, 12, 1),
+};
+
+static const struct iproc_clk_ctrl lcpll0_clk[] = {
+ [BCM_SR_LCPLL0_SATA_REF_CLK] = {
+ .channel = BCM_SR_LCPLL0_SATA_REF_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x0, 7, 1, 13),
+ .mdiv = REG_VAL(0x14, 0, 9),
+ },
+ [BCM_SR_LCPLL0_USB_REF_CLK] = {
+ .channel = BCM_SR_LCPLL0_USB_REF_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x0, 8, 2, 14),
+ .mdiv = REG_VAL(0x14, 10, 9),
+ },
+ [BCM_SR_LCPLL0_SATA_REFPN_CLK] = {
+ .channel = BCM_SR_LCPLL0_SATA_REFPN_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x0, 9, 3, 15),
+ .mdiv = REG_VAL(0x14, 20, 9),
+ },
+};
+
+static void __init sr_lcpll0_clk_init(struct device_node *node)
+{
+ iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk,
+ ARRAY_SIZE(lcpll0_clk));
+}
+CLK_OF_DECLARE(sr_lcpll0_clk, "brcm,sr-lcpll0",
+ sr_lcpll0_clk_init);
+
+static const struct iproc_pll_ctrl lcpll1 = {
+ .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
+ .aon = AON_VAL(0x0, 2, 22, 21),
+ .reset = RESET_VAL(0x0, 31, 30),
+ .sw_ctrl = SW_CTRL_VAL(0x4, 31),
+ .ndiv_int = REG_VAL(0x4, 16, 10),
+ .pdiv = REG_VAL(0x4, 26, 4),
+ .status = REG_VAL(0x38, 12, 1),
+};
+
+static const struct iproc_clk_ctrl lcpll1_clk[] = {
+ [BCM_SR_LCPLL1_WAN_CLK] = {
+ .channel = BCM_SR_LCPLL1_WAN_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x0, 7, 1, 13),
+ .mdiv = REG_VAL(0x14, 0, 9),
+ },
+};
+
+static void __init sr_lcpll1_clk_init(struct device_node *node)
+{
+ iproc_pll_clk_setup(node, &lcpll1, NULL, 0, lcpll1_clk,
+ ARRAY_SIZE(lcpll1_clk));
+}
+CLK_OF_DECLARE(sr_lcpll1_clk, "brcm,sr-lcpll1",
+ sr_lcpll1_clk_init);
+
+static const struct iproc_pll_ctrl lcpll_pcie = {
+ .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
+ .aon = AON_VAL(0x0, 2, 25, 24),
+ .reset = RESET_VAL(0x0, 31, 30),
+ .sw_ctrl = SW_CTRL_VAL(0x4, 31),
+ .ndiv_int = REG_VAL(0x4, 16, 10),
+ .pdiv = REG_VAL(0x4, 26, 4),
+ .status = REG_VAL(0x38, 12, 1),
+};
+
+static const struct iproc_clk_ctrl lcpll_pcie_clk[] = {
+ [BCM_SR_LCPLL_PCIE_PHY_REF_CLK] = {
+ .channel = BCM_SR_LCPLL_PCIE_PHY_REF_CLK,
+ .flags = IPROC_CLK_AON,
+ .enable = ENABLE_VAL(0x0, 7, 1, 13),
+ .mdiv = REG_VAL(0x14, 0, 9),
+ },
+};
+
+static void __init sr_lcpll_pcie_clk_init(struct device_node *node)
+{
+ iproc_pll_clk_setup(node, &lcpll_pcie, NULL, 0, lcpll_pcie_clk,
+ ARRAY_SIZE(lcpll_pcie_clk));
+}
+CLK_OF_DECLARE(sr_lcpll_pcie_clk, "brcm,sr-lcpll-pcie",
+ sr_lcpll_pcie_clk_init);
--
2.7.4
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 04/11] arm64: dts: Initial DTS files for Broadcom Stingray SOC
[not found] ` <1494934256-1350-1-git-send-email-anup.patel-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
2017-05-16 11:30 ` [PATCH v3 02/11] dt-bindings: clk: Extend binding doc for Stingray SOC Anup Patel
2017-05-16 11:30 ` [PATCH v3 03/11] clk: bcm: Add clocks " Anup Patel
@ 2017-05-16 11:30 ` Anup Patel
2017-05-16 11:30 ` [PATCH v3 06/11] arm64: dts: Add NAND DT nodes for " Anup Patel
` (2 subsequent siblings)
5 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2017-05-16 11:30 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Michael Turquette
Cc: Catalin Marinas, Will Deacon, Ray Jui, Scott Branden, Jon Mason,
Florian Fainelli, Oza Pawandeep, Srinath Mannam, Pramod Kumar,
Sandeep Tripathy, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Anup Patel,
Scott Branden
The Broadcom Stingray SoC is a new member in Broadcom iProc
SoC family.
This patch adds initial DTS files for Broadcom Stingray SoC
and two of its reference boards (bcm958742k and bcm958742t).
We have lot of reference boards and large number of devices
in Broadcom Stingray SoC so eventually we will have quite
a few DTS files for Stingray. To tackle, we have added a
separate directory for Stingray DTS files.
Signed-off-by: Anup Patel <anup.patel-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Signed-off-by: Scott Branden <scott.branden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Reviewed-by: Ray Jui <rjui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
arch/arm64/boot/dts/broadcom/Makefile | 1 +
arch/arm64/boot/dts/broadcom/stingray/Makefile | 6 +
.../boot/dts/broadcom/stingray/bcm958742-base.dtsi | 55 ++++
.../boot/dts/broadcom/stingray/bcm958742k.dts | 48 ++++
.../boot/dts/broadcom/stingray/bcm958742t.dts | 40 +++
.../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 302 +++++++++++++++++++++
6 files changed, 452 insertions(+)
create mode 100644 arch/arm64/boot/dts/broadcom/stingray/Makefile
create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile
index bfa8f8e..f11bdd6 100644
--- a/arch/arm64/boot/dts/broadcom/Makefile
+++ b/arch/arm64/boot/dts/broadcom/Makefile
@@ -1,6 +1,7 @@
dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb
+dts-dirs := stingray
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/broadcom/stingray/Makefile b/arch/arm64/boot/dts/broadcom/stingray/Makefile
new file mode 100644
index 0000000..f70028e
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/stingray/Makefile
@@ -0,0 +1,6 @@
+dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742k.dtb
+dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742t.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
new file mode 100644
index 0000000..992944b
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
@@ -0,0 +1,55 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016-2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "stingray.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart0;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+};
+
+&memory { /* Default DRAM banks */
+ reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
+ <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
new file mode 100644
index 0000000..c309cda
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
@@ -0,0 +1,48 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016-2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm958742-base.dtsi"
+
+/ {
+ compatible = "brcm,bcm958742k", "brcm,stingray";
+ model = "Stingray Combo SVK (BCM958742K)";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
new file mode 100644
index 0000000..6ebe399
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
@@ -0,0 +1,40 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm958742-base.dtsi"
+
+/ {
+ compatible = "brcm,bcm958742t", "brcm,stingray";
+ model = "Stingray SST100 (BCM958742T)";
+};
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
new file mode 100644
index 0000000..9fe19a2
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -0,0 +1,302 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015-2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "brcm,stingray";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER0_L2>;
+ };
+
+ cpu@001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER0_L2>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER1_L2>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER1_L2>;
+ };
+
+ cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER2_L2>;
+ };
+
+ cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x201>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER2_L2>;
+ };
+
+ cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER3_L2>;
+ };
+
+ cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x0 0x301>;
+ enable-method = "psci";
+ next-level-cache = <&CLUSTER3_L2>;
+ };
+
+ CLUSTER0_L2: l2-cache@000 {
+ compatible = "cache";
+ };
+
+ CLUSTER1_L2: l2-cache@100 {
+ compatible = "cache";
+ };
+
+ CLUSTER2_L2: l2-cache@200 {
+ compatible = "cache";
+ };
+
+ CLUSTER3_L2: l2-cache@300 {
+ compatible = "cache";
+ };
+ };
+
+ memory: memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ scr {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x61000000 0x05000000>;
+
+ gic: interrupt-controller@63c00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-controller;
+ reg = <0x02c00000 0x010000>, /* GICD */
+ <0x02e00000 0x600000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: gic-its@63c20000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0x02c20000 0x10000>;
+ };
+ };
+
+ smmu: mmu@64000000 {
+ compatible = "arm,mmu-500";
+ reg = <0x03000000 0x80000>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <2>;
+ };
+ };
+
+ hsls {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x68900000 0x17700000>;
+
+ uart0: uart@68a00000 {
+ device_type = "serial";
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00100000 0x1000>;
+ reg-shift = <2>;
+ clock-frequency = <25000000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart1: uart@68a10000 {
+ device_type = "serial";
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00110000 0x1000>;
+ reg-shift = <2>;
+ clock-frequency = <25000000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart2: uart@68a20000 {
+ device_type = "serial";
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00120000 0x1000>;
+ reg-shift = <2>;
+ clock-frequency = <25000000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart3: uart@68a30000 {
+ device_type = "serial";
+ compatible = "snps,dw-apb-uart";
+ reg = <0x00130000 0x1000>;
+ reg-shift = <2>;
+ clock-frequency = <25000000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ hwrng: hwrng@68b20000 {
+ compatible = "brcm,iproc-rng200";
+ reg = <0x00220000 0x28>;
+ };
+ };
+};
--
2.7.4
--
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 06/11] arm64: dts: Add NAND DT nodes for Stingray SOC
[not found] ` <1494934256-1350-1-git-send-email-anup.patel-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
` (2 preceding siblings ...)
2017-05-16 11:30 ` [PATCH v3 04/11] arm64: dts: Initial DTS files for Broadcom " Anup Patel
@ 2017-05-16 11:30 ` Anup Patel
2017-05-16 11:30 ` [PATCH v3 07/11] arm64: dts: Add pinctrl " Anup Patel
2017-05-16 18:53 ` [PATCH v3 00/11] Broadcom Stingray SOC Initial Support Olof Johansson
5 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2017-05-16 11:30 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Michael Turquette
Cc: Catalin Marinas, Will Deacon, Ray Jui, Scott Branden, Jon Mason,
Florian Fainelli, Oza Pawandeep, Srinath Mannam, Pramod Kumar,
Sandeep Tripathy, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Abhishek Shah
From: Pramod Kumar <pramod.kumar-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
This patch adds NAND controller DT Node and NAND chip DT
node for Stingray SOC and Stingray reference boards.
Signed-off-by: Pramod Kumar <pramod.kumar-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Signed-off-by: Abhishek Shah <abhishek.shah-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Reviewed-by: Vikram Prakash <vikram.prakash-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Reviewed-by: Ray Jui <ray.jui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Reviewed-by: Scott Branden <scott.branden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi | 15 +++++++++++++++
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 13 +++++++++++++
2 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
index 992944b..aad45a2 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
@@ -53,3 +53,18 @@
&uart1 {
status = "okay";
};
+
+&nand {
+ status = "ok";
+ nandcs@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <16>;
+ brcm,nand-oob-sector-size = <16>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index 6b690db..003f814 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -307,5 +307,18 @@
compatible = "brcm,iproc-rng200";
reg = <0x00220000 0x28>;
};
+
+ nand: nand@68c60000 {
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
+ reg = <0x00360000 0x600>,
+ <0x0050a408 0x600>,
+ <0x00360f00 0x20>;
+ reg-names = "nand", "iproc-idm", "iproc-ext";
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ brcm,nand-has-wp;
+ status = "disabled";
+ };
};
};
--
2.7.4
--
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 07/11] arm64: dts: Add pinctrl DT nodes for Stingray SOC
[not found] ` <1494934256-1350-1-git-send-email-anup.patel-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
` (3 preceding siblings ...)
2017-05-16 11:30 ` [PATCH v3 06/11] arm64: dts: Add NAND DT nodes for " Anup Patel
@ 2017-05-16 11:30 ` Anup Patel
2017-05-16 18:53 ` [PATCH v3 00/11] Broadcom Stingray SOC Initial Support Olof Johansson
5 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2017-05-16 11:30 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Michael Turquette
Cc: Catalin Marinas, Will Deacon, Ray Jui, Scott Branden, Jon Mason,
Florian Fainelli, Oza Pawandeep, Srinath Mannam, Pramod Kumar,
Sandeep Tripathy, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w, Anup Patel
From: Pramod Kumar <pramod.kumar-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
This patch adds pinctrl and pinmux related DT nodes for
Stingray SOC.
For manageability, pinctrl and pinmum DT nodes are added
as separate DTSi file and included in main DTSi file.
Signed-off-by: Pramod Kumar <pramod.kumar-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Signed-off-by: Anup Patel <anup.patel-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Reviewed-by: Ray Jui <ray.jui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Reviewed-by: Vikram Prakash <vikram.prakash-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Reviewed-by: Scott Branden <scott.branden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
.../dts/broadcom/stingray/stingray-pinctrl.dtsi | 345 +++++++++++++++++++++
.../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 +
.../dt-bindings/pinctrl/brcm,pinctrl-stingray.h | 68 ++++
3 files changed, 415 insertions(+)
create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi
create mode 100644 include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi
new file mode 100644
index 0000000..af5d480
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi
@@ -0,0 +1,345 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016-2017 Broadcom. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h>
+
+ pinconf: pinconf@68a40000 {
+ compatible = "pinconf-single";
+ reg = <0x00140000 0x250>;
+ pinctrl-single,register-width = <32>;
+
+ /* pinconf functions */
+ };
+
+ pinmux: pinmux@68a4029c {
+ compatible = "pinctrl-single";
+ reg = <0x0014029c 0x250>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xf>;
+ pinctrl-single,gpio-range = <
+ &range 0 154 MODE_GPIO
+ >;
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+
+ /* pinctrl functions */
+ tsio_pins: pinmux_gpio_14 {
+ pinctrl-single,pins = <
+ 0x038 MODE_NITRO /* tsio_0 */
+ 0x03c MODE_NITRO /* tsio_1 */
+ >;
+ };
+
+ nor_pins: pinmux_pnor_adv_n {
+ pinctrl-single,pins = <
+ 0x0ac MODE_PNOR /* nand_ce1_n */
+ 0x0b0 MODE_PNOR /* nand_ce0_n */
+ 0x0b4 MODE_PNOR /* nand_we_n */
+ 0x0b8 MODE_PNOR /* nand_wp_n */
+ 0x0bc MODE_PNOR /* nand_re_n */
+ 0x0c0 MODE_PNOR /* nand_rdy_bsy_n */
+ 0x0c4 MODE_PNOR /* nand_io0_0 */
+ 0x0c8 MODE_PNOR /* nand_io1_0 */
+ 0x0cc MODE_PNOR /* nand_io2_0 */
+ 0x0d0 MODE_PNOR /* nand_io3_0 */
+ 0x0d4 MODE_PNOR /* nand_io4_0 */
+ 0x0d8 MODE_PNOR /* nand_io5_0 */
+ 0x0dc MODE_PNOR /* nand_io6_0 */
+ 0x0e0 MODE_PNOR /* nand_io7_0 */
+ 0x0e4 MODE_PNOR /* nand_io8_0 */
+ 0x0e8 MODE_PNOR /* nand_io9_0 */
+ 0x0ec MODE_PNOR /* nand_io10_0 */
+ 0x0f0 MODE_PNOR /* nand_io11_0 */
+ 0x0f4 MODE_PNOR /* nand_io12_0 */
+ 0x0f8 MODE_PNOR /* nand_io13_0 */
+ 0x0fc MODE_PNOR /* nand_io14_0 */
+ 0x100 MODE_PNOR /* nand_io15_0 */
+ 0x104 MODE_PNOR /* nand_ale_0 */
+ 0x108 MODE_PNOR /* nand_cle_0 */
+ 0x040 MODE_PNOR /* pnor_adv_n */
+ 0x044 MODE_PNOR /* pnor_baa_n */
+ 0x048 MODE_PNOR /* pnor_bls_0_n */
+ 0x04c MODE_PNOR /* pnor_bls_1_n */
+ 0x050 MODE_PNOR /* pnor_cre */
+ 0x054 MODE_PNOR /* pnor_cs_2_n */
+ 0x058 MODE_PNOR /* pnor_cs_1_n */
+ 0x05c MODE_PNOR /* pnor_cs_0_n */
+ 0x060 MODE_PNOR /* pnor_we_n */
+ 0x064 MODE_PNOR /* pnor_oe_n */
+ 0x068 MODE_PNOR /* pnor_intr */
+ 0x06c MODE_PNOR /* pnor_dat_0 */
+ 0x070 MODE_PNOR /* pnor_dat_1 */
+ 0x074 MODE_PNOR /* pnor_dat_2 */
+ 0x078 MODE_PNOR /* pnor_dat_3 */
+ 0x07c MODE_PNOR /* pnor_dat_4 */
+ 0x080 MODE_PNOR /* pnor_dat_5 */
+ 0x084 MODE_PNOR /* pnor_dat_6 */
+ 0x088 MODE_PNOR /* pnor_dat_7 */
+ 0x08c MODE_PNOR /* pnor_dat_8 */
+ 0x090 MODE_PNOR /* pnor_dat_9 */
+ 0x094 MODE_PNOR /* pnor_dat_10 */
+ 0x098 MODE_PNOR /* pnor_dat_11 */
+ 0x09c MODE_PNOR /* pnor_dat_12 */
+ 0x0a0 MODE_PNOR /* pnor_dat_13 */
+ 0x0a4 MODE_PNOR /* pnor_dat_14 */
+ 0x0a8 MODE_PNOR /* pnor_dat_15 */
+ >;
+ };
+
+ nand_pins: pinmux_nand_ce1_n {
+ pinctrl-single,pins = <
+ 0x0ac MODE_NAND /* nand_ce1_n */
+ 0x0b0 MODE_NAND /* nand_ce0_n */
+ 0x0b4 MODE_NAND /* nand_we_n */
+ 0x0b8 MODE_NAND /* nand_wp_n */
+ 0x0bc MODE_NAND /* nand_re_n */
+ 0x0c0 MODE_NAND /* nand_rdy_bsy_n */
+ 0x0c4 MODE_NAND /* nand_io0_0 */
+ 0x0c8 MODE_NAND /* nand_io1_0 */
+ 0x0cc MODE_NAND /* nand_io2_0 */
+ 0x0d0 MODE_NAND /* nand_io3_0 */
+ 0x0d4 MODE_NAND /* nand_io4_0 */
+ 0x0d8 MODE_NAND /* nand_io5_0 */
+ 0x0dc MODE_NAND /* nand_io6_0 */
+ 0x0e0 MODE_NAND /* nand_io7_0 */
+ 0x0e4 MODE_NAND /* nand_io8_0 */
+ 0x0e8 MODE_NAND /* nand_io9_0 */
+ 0x0ec MODE_NAND /* nand_io10_0 */
+ 0x0f0 MODE_NAND /* nand_io11_0 */
+ 0x0f4 MODE_NAND /* nand_io12_0 */
+ 0x0f8 MODE_NAND /* nand_io13_0 */
+ 0x0fc MODE_NAND /* nand_io14_0 */
+ 0x100 MODE_NAND /* nand_io15_0 */
+ 0x104 MODE_NAND /* nand_ale_0 */
+ 0x108 MODE_NAND /* nand_cle_0 */
+ >;
+ };
+
+ pwm0_pins: pinmux_pwm_0 {
+ pinctrl-single,pins = <
+ 0x10c MODE_NITRO
+ >;
+ };
+
+ pwm1_pins: pinmux_pwm_1 {
+ pinctrl-single,pins = <
+ 0x110 MODE_NITRO
+ >;
+ };
+
+ pwm2_pins: pinmux_pwm_2 {
+ pinctrl-single,pins = <
+ 0x114 MODE_NITRO
+ >;
+ };
+
+ pwm3_pins: pinmux_pwm_3 {
+ pinctrl-single,pins = <
+ 0x118 MODE_NITRO
+ >;
+ };
+
+ dbu_rxd_pins: pinmux_uart1_sin_nitro {
+ pinctrl-single,pins = <
+ 0x11c MODE_NITRO /* dbu_rxd */
+ 0x120 MODE_NITRO /* dbu_txd */
+ >;
+ };
+
+ uart1_pins: pinmux_uart1_sin_nand {
+ pinctrl-single,pins = <
+ 0x11c MODE_NAND /* uart1_sin */
+ 0x120 MODE_NAND /* uart1_out */
+ >;
+ };
+
+ uart2_pins: pinmux_uart2_sin {
+ pinctrl-single,pins = <
+ 0x124 MODE_NITRO /* uart2_sin */
+ 0x128 MODE_NITRO /* uart2_out */
+ >;
+ };
+
+ uart3_pins: pinmux_uart3_sin {
+ pinctrl-single,pins = <
+ 0x12c MODE_NITRO /* uart3_sin */
+ 0x130 MODE_NITRO /* uart3_out */
+ >;
+ };
+
+ i2s_pins: pinmux_i2s_bitclk {
+ pinctrl-single,pins = <
+ 0x134 MODE_NITRO /* i2s_bitclk */
+ 0x138 MODE_NITRO /* i2s_sdout */
+ 0x13c MODE_NITRO /* i2s_sdin */
+ 0x140 MODE_NITRO /* i2s_ws */
+ 0x144 MODE_NITRO /* i2s_mclk */
+ 0x148 MODE_NITRO /* i2s_spdif_out */
+ >;
+ };
+
+ qspi_pins: pinumx_qspi_hold_n {
+ pinctrl-single,pins = <
+ 0x14c MODE_NAND /* qspi_hold_n */
+ 0x150 MODE_NAND /* qspi_wp_n */
+ 0x154 MODE_NAND /* qspi_sck */
+ 0x158 MODE_NAND /* qspi_cs_n */
+ 0x15c MODE_NAND /* qspi_mosi */
+ 0x160 MODE_NAND /* qspi_miso */
+ >;
+ };
+
+ mdio_pins: pinumx_ext_mdio {
+ pinctrl-single,pins = <
+ 0x164 MODE_NITRO /* ext_mdio */
+ 0x168 MODE_NITRO /* ext_mdc */
+ >;
+ };
+
+ i2c0_pins: pinmux_i2c0_sda {
+ pinctrl-single,pins = <
+ 0x16c MODE_NITRO /* i2c0_sda */
+ 0x170 MODE_NITRO /* i2c0_scl */
+ >;
+ };
+
+ i2c1_pins: pinmux_i2c1_sda {
+ pinctrl-single,pins = <
+ 0x174 MODE_NITRO /* i2c1_sda */
+ 0x178 MODE_NITRO /* i2c1_scl */
+ >;
+ };
+
+ sdio0_pins: pinmux_sdio0_cd_l {
+ pinctrl-single,pins = <
+ 0x17c MODE_NITRO /* sdio0_cd_l */
+ 0x180 MODE_NITRO /* sdio0_clk_sdcard */
+ 0x184 MODE_NITRO /* sdio0_data0 */
+ 0x188 MODE_NITRO /* sdio0_data1 */
+ 0x18c MODE_NITRO /* sdio0_data2 */
+ 0x190 MODE_NITRO /* sdio0_data3 */
+ 0x194 MODE_NITRO /* sdio0_data4 */
+ 0x198 MODE_NITRO /* sdio0_data5 */
+ 0x19c MODE_NITRO /* sdio0_data6 */
+ 0x1a0 MODE_NITRO /* sdio0_data7 */
+ 0x1a4 MODE_NITRO /* sdio0_cmd */
+ 0x1a8 MODE_NITRO /* sdio0_emmc_rst_n */
+ 0x1ac MODE_NITRO /* sdio0_led_on */
+ 0x1b0 MODE_NITRO /* sdio0_wp */
+ >;
+ };
+
+ sdio1_pins: pinmux_sdio1_cd_l {
+ pinctrl-single,pins = <
+ 0x1b4 MODE_NITRO /* sdio1_cd_l */
+ 0x1b8 MODE_NITRO /* sdio1_clk_sdcard */
+ 0x1bc MODE_NITRO /* sdio1_data0 */
+ 0x1c0 MODE_NITRO /* sdio1_data1 */
+ 0x1c4 MODE_NITRO /* sdio1_data2 */
+ 0x1c8 MODE_NITRO /* sdio1_data3 */
+ 0x1cc MODE_NITRO /* sdio1_data4 */
+ 0x1d0 MODE_NITRO /* sdio1_data5 */
+ 0x1d4 MODE_NITRO /* sdio1_data6 */
+ 0x1d8 MODE_NITRO /* sdio1_data7 */
+ 0x1dc MODE_NITRO /* sdio1_cmd */
+ 0x1e0 MODE_NITRO /* sdio1_emmc_rst_n */
+ 0x1e4 MODE_NITRO /* sdio1_led_on */
+ 0x1e8 MODE_NITRO /* sdio1_wp */
+ >;
+ };
+
+ spi0_pins: pinmux_spi0_sck_nand {
+ pinctrl-single,pins = <
+ 0x1ec MODE_NITRO /* spi0_sck */
+ 0x1f0 MODE_NITRO /* spi0_rxd */
+ 0x1f4 MODE_NITRO /* spi0_fss */
+ 0x1f8 MODE_NITRO /* spi0_txd */
+ >;
+ };
+
+ spi1_pins: pinmux_spi1_sck_nand {
+ pinctrl-single,pins = <
+ 0x1fc MODE_NITRO /* spi1_sck */
+ 0x200 MODE_NITRO /* spi1_rxd */
+ 0x204 MODE_NITRO /* spi1_fss */
+ 0x208 MODE_NITRO /* spi1_txd */
+ >;
+ };
+
+ nuart_pins: pinmux_uart0_sin_nitro {
+ pinctrl-single,pins = <
+ 0x20c MODE_NITRO /* nuart_rxd */
+ 0x210 MODE_NITRO /* nuart_txd */
+ >;
+ };
+
+ uart0_pins: pinumux_uart0_sin_nand {
+ pinctrl-single,pins = <
+ 0x20c MODE_NAND /* uart0_sin */
+ 0x210 MODE_NAND /* uart0_out */
+ 0x214 MODE_NAND /* uart0_rts */
+ 0x218 MODE_NAND /* uart0_cts */
+ 0x21c MODE_NAND /* uart0_dtr */
+ 0x220 MODE_NAND /* uart0_dcd */
+ 0x224 MODE_NAND /* uart0_dsr */
+ 0x228 MODE_NAND /* uart0_ri */
+ >;
+ };
+
+ drdu2_pins: pinmux_drdu2_overcurrent {
+ pinctrl-single,pins = <
+ 0x22c MODE_NITRO /* drdu2_overcurrent */
+ 0x230 MODE_NITRO /* drdu2_vbus_ppc */
+ 0x234 MODE_NITRO /* drdu2_vbus_present */
+ 0x238 MODE_NITRO /* drdu2_id */
+ >;
+ };
+
+ drdu3_pins: pinmux_drdu3_overcurrent {
+ pinctrl-single,pins = <
+ 0x23c MODE_NITRO /* drdu3_overcurrent */
+ 0x240 MODE_NITRO /* drdu3_vbus_ppc */
+ 0x244 MODE_NITRO /* drdu3_vbus_present */
+ 0x248 MODE_NITRO /* drdu3_id */
+ >;
+ };
+
+ usb3h_pins: pinmux_usb3h_overcurrent {
+ pinctrl-single,pins = <
+ 0x24c MODE_NITRO /* usb3h_overcurrent */
+ 0x250 MODE_NITRO /* usb3h_vbus_ppc */
+ >;
+ };
+ };
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index 003f814..a4afd44 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -259,6 +259,8 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x68900000 0x17700000>;
+ #include "stingray-pinctrl.dtsi"
+
uart0: uart@68a00000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
diff --git a/include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h b/include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h
new file mode 100644
index 0000000..caa6c66
--- /dev/null
+++ b/include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h
@@ -0,0 +1,68 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2017 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__
+#define __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__
+
+/* Alternate functions available in MUX controller */
+#define MODE_NITRO 0
+#define MODE_NAND 1
+#define MODE_PNOR 2
+#define MODE_GPIO 3
+
+/* Pad configuration attribute */
+#define PAD_SLEW_RATE_ENA (1 << 0)
+#define PAD_SLEW_RATE_ENA_MASK (1 << 0)
+
+#define PAD_DRIVE_STRENGTH_2_MA (0 << 1)
+#define PAD_DRIVE_STRENGTH_4_MA (1 << 1)
+#define PAD_DRIVE_STRENGTH_6_MA (2 << 1)
+#define PAD_DRIVE_STRENGTH_8_MA (3 << 1)
+#define PAD_DRIVE_STRENGTH_10_MA (4 << 1)
+#define PAD_DRIVE_STRENGTH_12_MA (5 << 1)
+#define PAD_DRIVE_STRENGTH_14_MA (6 << 1)
+#define PAD_DRIVE_STRENGTH_16_MA (7 << 1)
+#define PAD_DRIVE_STRENGTH_MASK (7 << 1)
+
+#define PAD_PULL_UP_ENA (1 << 4)
+#define PAD_PULL_UP_ENA_MASK (1 << 4)
+
+#define PAD_PULL_DOWN_ENA (1 << 5)
+#define PAD_PULL_DOWN_ENA_MASK (1 << 5)
+
+#define PAD_INPUT_PATH_DIS (1 << 6)
+#define PAD_INPUT_PATH_DIS_MASK (1 << 6)
+
+#define PAD_HYSTERESIS_ENA (1 << 7)
+#define PAD_HYSTERESIS_ENA_MASK (1 << 7)
+
+#endif
--
2.7.4
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^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 00/11] Broadcom Stingray SOC Initial Support
[not found] ` <1494934256-1350-1-git-send-email-anup.patel-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
` (4 preceding siblings ...)
2017-05-16 11:30 ` [PATCH v3 07/11] arm64: dts: Add pinctrl " Anup Patel
@ 2017-05-16 18:53 ` Olof Johansson
2017-05-17 4:24 ` Anup Patel
5 siblings, 1 reply; 16+ messages in thread
From: Olof Johansson @ 2017-05-16 18:53 UTC (permalink / raw)
To: Anup Patel
Cc: Rob Herring, Mark Rutland, Michael Turquette, Catalin Marinas,
Will Deacon, Ray Jui, Scott Branden, Jon Mason, Florian Fainelli,
Oza Pawandeep, Srinath Mannam, Pramod Kumar, Sandeep Tripathy,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Broad
Hi,
On Tue, May 16, 2017 at 4:30 AM, Anup Patel <anup.patel-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote:
> This patchset adds initial support of Broadcom Stingray SOC
> by reusing existing Broadcom iProc device drivers.
>
> Most of the patches in this patchset are DT patches except
> the Stingray clock tree support which just one patch.
>
> This patchset is based on Linux-4.12-rc1 and it is also available
> at stingray-v3 branch of https://github.com/Broadcom/arm64-linux.git
>
> Changes since v2:
> - Remove default bootargs from chosen DT node
> - Remove "linux" prefix from stdout DT attribute of chosen DT node
> - Remove use of GIC_CPU_MASK_xxx() for PPIs
>
> Changes since v1:
> - Rebased patches for Linux-4.12-rc1
> - Removed unwanted /memreserve/ from bcm958742-base.dtsi
> - Use ranges DT property to clear view of memory-layout
> - Make bcm-sr.h part of clock DT bindings patch
>
> Anup Patel (3):
> dt-bindings: bcm: Add Broadcom Stingray bindings document
> arm64: dts: Initial DTS files for Broadcom Stingray SOC
> arm64: dts: Add PL022, PL330 and SP805 DT nodes for Stingray
>
> Oza Pawandeep (1):
> arm64: dts: Add I2C DT nodes for Stingray SoC
>
> Pramod Kumar (3):
> arm64: dts: Add NAND DT nodes for Stingray SOC
> arm64: dts: Add pinctrl DT nodes for Stingray SOC
> arm64: dts: Add GPIO DT nodes for Stingray SOC
>
> Sandeep Tripathy (3):
> dt-bindings: clk: Extend binding doc for Stingray SOC
> clk: bcm: Add clocks for Stingray SOC
> arm64: dts: Add clock DT nodes for Stingray SOC
>
> Srinath Mannam (1):
> arm64: dts: Add PWM and SDHCI DT nodes for Stingray SOC
>
> .../devicetree/bindings/arm/bcm/brcm,stingray.txt | 12 +
> .../bindings/clock/brcm,iproc-clocks.txt | 76 ++++
> arch/arm64/boot/dts/broadcom/Makefile | 1 +
> arch/arm64/boot/dts/broadcom/stingray/Makefile | 6 +
> .../boot/dts/broadcom/stingray/bcm958742-base.dtsi | 131 ++++++
> .../boot/dts/broadcom/stingray/bcm958742k.dts | 78 ++++
> .../boot/dts/broadcom/stingray/bcm958742t.dts | 40 ++
> .../boot/dts/broadcom/stingray/stingray-clock.dtsi | 170 ++++++++
> .../dts/broadcom/stingray/stingray-pinctrl.dtsi | 345 ++++++++++++++++
> .../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 460 +++++++++++++++++++++
> drivers/clk/bcm/Kconfig | 8 +
> drivers/clk/bcm/Makefile | 1 +
> drivers/clk/bcm/clk-sr.c | 300 ++++++++++++++
> include/dt-bindings/clock/bcm-sr.h | 101 +++++
> .../dt-bindings/pinctrl/brcm,pinctrl-stingray.h | 68 +++
> 15 files changed, 1797 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt
> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/Makefile
> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi
> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
> create mode 100644 drivers/clk/bcm/clk-sr.c
> create mode 100644 include/dt-bindings/clock/bcm-sr.h
> create mode 100644 include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h
Grouping as one patchset for review is fine, but when you submit this
for merge you need to split it up:
- Documentation/devicetree can go with the driver pieces or with the
DT changes, your choice
- DTS/DTSI changes should go through the Broadcom maintainers to arm-soc
- clk changes should go to clk maintainers.
Also, there's usually no need to split up a DT introduction and having
separate pieces for NAND/pinctrl/GPIO/etc: They can all go in the main
DT submission patch.
-Olof
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^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v3 00/11] Broadcom Stingray SOC Initial Support
2017-05-16 18:53 ` [PATCH v3 00/11] Broadcom Stingray SOC Initial Support Olof Johansson
@ 2017-05-17 4:24 ` Anup Patel
2017-05-19 18:38 ` Florian Fainelli
0 siblings, 1 reply; 16+ messages in thread
From: Anup Patel @ 2017-05-17 4:24 UTC (permalink / raw)
To: Olof Johansson
Cc: Rob Herring, Mark Rutland, Michael Turquette, Catalin Marinas,
Will Deacon, Ray Jui, Scott Branden, Jon Mason, Florian Fainelli,
Oza Pawandeep, Srinath Mannam, Pramod Kumar, Sandeep Tripathy,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk, linux-arm-kernel@lists.infradead.org, Broad
On Wed, May 17, 2017 at 12:23 AM, Olof Johansson <olof@lixom.net> wrote:
> Hi,
>
>
>
> On Tue, May 16, 2017 at 4:30 AM, Anup Patel <anup.patel@broadcom.com> wrote:
>> This patchset adds initial support of Broadcom Stingray SOC
>> by reusing existing Broadcom iProc device drivers.
>>
>> Most of the patches in this patchset are DT patches except
>> the Stingray clock tree support which just one patch.
>>
>> This patchset is based on Linux-4.12-rc1 and it is also available
>> at stingray-v3 branch of https://github.com/Broadcom/arm64-linux.git
>>
>> Changes since v2:
>> - Remove default bootargs from chosen DT node
>> - Remove "linux" prefix from stdout DT attribute of chosen DT node
>> - Remove use of GIC_CPU_MASK_xxx() for PPIs
>>
>> Changes since v1:
>> - Rebased patches for Linux-4.12-rc1
>> - Removed unwanted /memreserve/ from bcm958742-base.dtsi
>> - Use ranges DT property to clear view of memory-layout
>> - Make bcm-sr.h part of clock DT bindings patch
>>
>> Anup Patel (3):
>> dt-bindings: bcm: Add Broadcom Stingray bindings document
>> arm64: dts: Initial DTS files for Broadcom Stingray SOC
>> arm64: dts: Add PL022, PL330 and SP805 DT nodes for Stingray
>>
>> Oza Pawandeep (1):
>> arm64: dts: Add I2C DT nodes for Stingray SoC
>>
>> Pramod Kumar (3):
>> arm64: dts: Add NAND DT nodes for Stingray SOC
>> arm64: dts: Add pinctrl DT nodes for Stingray SOC
>> arm64: dts: Add GPIO DT nodes for Stingray SOC
>>
>> Sandeep Tripathy (3):
>> dt-bindings: clk: Extend binding doc for Stingray SOC
>> clk: bcm: Add clocks for Stingray SOC
>> arm64: dts: Add clock DT nodes for Stingray SOC
>>
>> Srinath Mannam (1):
>> arm64: dts: Add PWM and SDHCI DT nodes for Stingray SOC
>>
>> .../devicetree/bindings/arm/bcm/brcm,stingray.txt | 12 +
>> .../bindings/clock/brcm,iproc-clocks.txt | 76 ++++
>> arch/arm64/boot/dts/broadcom/Makefile | 1 +
>> arch/arm64/boot/dts/broadcom/stingray/Makefile | 6 +
>> .../boot/dts/broadcom/stingray/bcm958742-base.dtsi | 131 ++++++
>> .../boot/dts/broadcom/stingray/bcm958742k.dts | 78 ++++
>> .../boot/dts/broadcom/stingray/bcm958742t.dts | 40 ++
>> .../boot/dts/broadcom/stingray/stingray-clock.dtsi | 170 ++++++++
>> .../dts/broadcom/stingray/stingray-pinctrl.dtsi | 345 ++++++++++++++++
>> .../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 460 +++++++++++++++++++++
>> drivers/clk/bcm/Kconfig | 8 +
>> drivers/clk/bcm/Makefile | 1 +
>> drivers/clk/bcm/clk-sr.c | 300 ++++++++++++++
>> include/dt-bindings/clock/bcm-sr.h | 101 +++++
>> .../dt-bindings/pinctrl/brcm,pinctrl-stingray.h | 68 +++
>> 15 files changed, 1797 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt
>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/Makefile
>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi
>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi
>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
>> create mode 100644 drivers/clk/bcm/clk-sr.c
>> create mode 100644 include/dt-bindings/clock/bcm-sr.h
>> create mode 100644 include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h
>
> Grouping as one patchset for review is fine, but when you submit this
> for merge you need to split it up:
>
> - Documentation/devicetree can go with the driver pieces or with the
> DT changes, your choice
> - DTS/DTSI changes should go through the Broadcom maintainers to arm-soc
> - clk changes should go to clk maintainers.
Only PATCH3 needs to go through clk maintainers rest all patches
are DT bindings document and DTS changes which can go through
Broadcom tree. Right ??
>
> Also, there's usually no need to split up a DT introduction and having
> separate pieces for NAND/pinctrl/GPIO/etc: They can all go in the main
> DT submission patch.
Yes, we have already squashed DTS patches from same author into
one DTS patch except NAND, PINCTRL and GPIO patches.
The NAND, PINCTRL, and GPIO patches were not squashed into
one patch for easy review but since you suggest I will squash these
three DTS patches into one DTS patch.
Regards,
Anup
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 00/11] Broadcom Stingray SOC Initial Support
2017-05-17 4:24 ` Anup Patel
@ 2017-05-19 18:38 ` Florian Fainelli
2017-05-22 11:57 ` Anup Patel
0 siblings, 1 reply; 16+ messages in thread
From: Florian Fainelli @ 2017-05-19 18:38 UTC (permalink / raw)
To: Anup Patel, Olof Johansson, Michael Turquette, sboyd
Cc: Mark Rutland, devicetree@vger.kernel.org, Florian Fainelli,
Sandeep Tripathy, Scott Branden, Jon Mason, Catalin Marinas,
Will Deacon, linux-kernel@vger.kernel.org,
Broadcom Kernel Feedback List, Pramod Kumar, Rob Herring,
Oza Pawandeep, Ray Jui, Srinath Mannam, linux-clk,
linux-arm-kernel@lists.infradead.org
On 05/16/2017 09:24 PM, Anup Patel wrote:
> On Wed, May 17, 2017 at 12:23 AM, Olof Johansson <olof@lixom.net> wrote:
>> Hi,
>>
>>
>>
>> On Tue, May 16, 2017 at 4:30 AM, Anup Patel <anup.patel@broadcom.com> wrote:
>>> This patchset adds initial support of Broadcom Stingray SOC
>>> by reusing existing Broadcom iProc device drivers.
>>>
>>> Most of the patches in this patchset are DT patches except
>>> the Stingray clock tree support which just one patch.
>>>
>>> This patchset is based on Linux-4.12-rc1 and it is also available
>>> at stingray-v3 branch of https://github.com/Broadcom/arm64-linux.git
>>>
>>> Changes since v2:
>>> - Remove default bootargs from chosen DT node
>>> - Remove "linux" prefix from stdout DT attribute of chosen DT node
>>> - Remove use of GIC_CPU_MASK_xxx() for PPIs
>>>
>>> Changes since v1:
>>> - Rebased patches for Linux-4.12-rc1
>>> - Removed unwanted /memreserve/ from bcm958742-base.dtsi
>>> - Use ranges DT property to clear view of memory-layout
>>> - Make bcm-sr.h part of clock DT bindings patch
>>>
>>> Anup Patel (3):
>>> dt-bindings: bcm: Add Broadcom Stingray bindings document
>>> arm64: dts: Initial DTS files for Broadcom Stingray SOC
>>> arm64: dts: Add PL022, PL330 and SP805 DT nodes for Stingray
>>>
>>> Oza Pawandeep (1):
>>> arm64: dts: Add I2C DT nodes for Stingray SoC
>>>
>>> Pramod Kumar (3):
>>> arm64: dts: Add NAND DT nodes for Stingray SOC
>>> arm64: dts: Add pinctrl DT nodes for Stingray SOC
>>> arm64: dts: Add GPIO DT nodes for Stingray SOC
>>>
>>> Sandeep Tripathy (3):
>>> dt-bindings: clk: Extend binding doc for Stingray SOC
>>> clk: bcm: Add clocks for Stingray SOC
>>> arm64: dts: Add clock DT nodes for Stingray SOC
>>>
>>> Srinath Mannam (1):
>>> arm64: dts: Add PWM and SDHCI DT nodes for Stingray SOC
>>>
>>> .../devicetree/bindings/arm/bcm/brcm,stingray.txt | 12 +
>>> .../bindings/clock/brcm,iproc-clocks.txt | 76 ++++
>>> arch/arm64/boot/dts/broadcom/Makefile | 1 +
>>> arch/arm64/boot/dts/broadcom/stingray/Makefile | 6 +
>>> .../boot/dts/broadcom/stingray/bcm958742-base.dtsi | 131 ++++++
>>> .../boot/dts/broadcom/stingray/bcm958742k.dts | 78 ++++
>>> .../boot/dts/broadcom/stingray/bcm958742t.dts | 40 ++
>>> .../boot/dts/broadcom/stingray/stingray-clock.dtsi | 170 ++++++++
>>> .../dts/broadcom/stingray/stingray-pinctrl.dtsi | 345 ++++++++++++++++
>>> .../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 460 +++++++++++++++++++++
>>> drivers/clk/bcm/Kconfig | 8 +
>>> drivers/clk/bcm/Makefile | 1 +
>>> drivers/clk/bcm/clk-sr.c | 300 ++++++++++++++
>>> include/dt-bindings/clock/bcm-sr.h | 101 +++++
>>> .../dt-bindings/pinctrl/brcm,pinctrl-stingray.h | 68 +++
>>> 15 files changed, 1797 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt
>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/Makefile
>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi
>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi
>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
>>> create mode 100644 drivers/clk/bcm/clk-sr.c
>>> create mode 100644 include/dt-bindings/clock/bcm-sr.h
>>> create mode 100644 include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h
>>
>> Grouping as one patchset for review is fine, but when you submit this
>> for merge you need to split it up:
>>
>> - Documentation/devicetree can go with the driver pieces or with the
>> DT changes, your choice
>> - DTS/DTSI changes should go through the Broadcom maintainers to arm-soc
>> - clk changes should go to clk maintainers.
>
> Only PATCH3 needs to go through clk maintainers rest all patches
> are DT bindings document and DTS changes which can go through
> Broadcom tree. Right ??
Patch 2 and 3 should go through the clock maintainers, and I can take
the remaining patches through the Broadcom ARM/ARM64 SoC pull requests,
no problem.
Unless there are specific changes requested which warrant a v4, I can
coordinate with Stephen and Mike to make sure that they take the
appropriate patches.
>
>>
>> Also, there's usually no need to split up a DT introduction and having
>> separate pieces for NAND/pinctrl/GPIO/etc: They can all go in the main
>> DT submission patch.
>
> Yes, we have already squashed DTS patches from same author into
> one DTS patch except NAND, PINCTRL and GPIO patches.
>
> The NAND, PINCTRL, and GPIO patches were not squashed into
> one patch for easy review but since you suggest I will squash these
> three DTS patches into one DTS patch.
>
> Regards,
> Anup
>
--
Florian
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 00/11] Broadcom Stingray SOC Initial Support
2017-05-19 18:38 ` Florian Fainelli
@ 2017-05-22 11:57 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2017-05-22 11:57 UTC (permalink / raw)
To: Florian Fainelli
Cc: Olof Johansson, Michael Turquette, sboyd, Rob Herring,
Mark Rutland, Catalin Marinas, Will Deacon, Ray Jui,
Scott Branden, Jon Mason, Oza Pawandeep, Srinath Mannam,
Pramod Kumar, Sandeep Tripathy, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk,
linux-arm-kernel@lists.infradead.org
On Sat, May 20, 2017 at 12:08 AM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> On 05/16/2017 09:24 PM, Anup Patel wrote:
>> On Wed, May 17, 2017 at 12:23 AM, Olof Johansson <olof@lixom.net> wrote:
>>> Hi,
>>>
>>>
>>>
>>> On Tue, May 16, 2017 at 4:30 AM, Anup Patel <anup.patel@broadcom.com> wrote:
>>>> This patchset adds initial support of Broadcom Stingray SOC
>>>> by reusing existing Broadcom iProc device drivers.
>>>>
>>>> Most of the patches in this patchset are DT patches except
>>>> the Stingray clock tree support which just one patch.
>>>>
>>>> This patchset is based on Linux-4.12-rc1 and it is also available
>>>> at stingray-v3 branch of https://github.com/Broadcom/arm64-linux.git
>>>>
>>>> Changes since v2:
>>>> - Remove default bootargs from chosen DT node
>>>> - Remove "linux" prefix from stdout DT attribute of chosen DT node
>>>> - Remove use of GIC_CPU_MASK_xxx() for PPIs
>>>>
>>>> Changes since v1:
>>>> - Rebased patches for Linux-4.12-rc1
>>>> - Removed unwanted /memreserve/ from bcm958742-base.dtsi
>>>> - Use ranges DT property to clear view of memory-layout
>>>> - Make bcm-sr.h part of clock DT bindings patch
>>>>
>>>> Anup Patel (3):
>>>> dt-bindings: bcm: Add Broadcom Stingray bindings document
>>>> arm64: dts: Initial DTS files for Broadcom Stingray SOC
>>>> arm64: dts: Add PL022, PL330 and SP805 DT nodes for Stingray
>>>>
>>>> Oza Pawandeep (1):
>>>> arm64: dts: Add I2C DT nodes for Stingray SoC
>>>>
>>>> Pramod Kumar (3):
>>>> arm64: dts: Add NAND DT nodes for Stingray SOC
>>>> arm64: dts: Add pinctrl DT nodes for Stingray SOC
>>>> arm64: dts: Add GPIO DT nodes for Stingray SOC
>>>>
>>>> Sandeep Tripathy (3):
>>>> dt-bindings: clk: Extend binding doc for Stingray SOC
>>>> clk: bcm: Add clocks for Stingray SOC
>>>> arm64: dts: Add clock DT nodes for Stingray SOC
>>>>
>>>> Srinath Mannam (1):
>>>> arm64: dts: Add PWM and SDHCI DT nodes for Stingray SOC
>>>>
>>>> .../devicetree/bindings/arm/bcm/brcm,stingray.txt | 12 +
>>>> .../bindings/clock/brcm,iproc-clocks.txt | 76 ++++
>>>> arch/arm64/boot/dts/broadcom/Makefile | 1 +
>>>> arch/arm64/boot/dts/broadcom/stingray/Makefile | 6 +
>>>> .../boot/dts/broadcom/stingray/bcm958742-base.dtsi | 131 ++++++
>>>> .../boot/dts/broadcom/stingray/bcm958742k.dts | 78 ++++
>>>> .../boot/dts/broadcom/stingray/bcm958742t.dts | 40 ++
>>>> .../boot/dts/broadcom/stingray/stingray-clock.dtsi | 170 ++++++++
>>>> .../dts/broadcom/stingray/stingray-pinctrl.dtsi | 345 ++++++++++++++++
>>>> .../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 460 +++++++++++++++++++++
>>>> drivers/clk/bcm/Kconfig | 8 +
>>>> drivers/clk/bcm/Makefile | 1 +
>>>> drivers/clk/bcm/clk-sr.c | 300 ++++++++++++++
>>>> include/dt-bindings/clock/bcm-sr.h | 101 +++++
>>>> .../dt-bindings/pinctrl/brcm,pinctrl-stingray.h | 68 +++
>>>> 15 files changed, 1797 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt
>>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/Makefile
>>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
>>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
>>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
>>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi
>>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi
>>>> create mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
>>>> create mode 100644 drivers/clk/bcm/clk-sr.c
>>>> create mode 100644 include/dt-bindings/clock/bcm-sr.h
>>>> create mode 100644 include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h
>>>
>>> Grouping as one patchset for review is fine, but when you submit this
>>> for merge you need to split it up:
>>>
>>> - Documentation/devicetree can go with the driver pieces or with the
>>> DT changes, your choice
>>> - DTS/DTSI changes should go through the Broadcom maintainers to arm-soc
>>> - clk changes should go to clk maintainers.
>>
>> Only PATCH3 needs to go through clk maintainers rest all patches
>> are DT bindings document and DTS changes which can go through
>> Broadcom tree. Right ??
>
> Patch 2 and 3 should go through the clock maintainers, and I can take
> the remaining patches through the Broadcom ARM/ARM64 SoC pull requests,
> no problem.
>
> Unless there are specific changes requested which warrant a v4, I can
> coordinate with Stephen and Mike to make sure that they take the
> appropriate patches.
We have minor changes in clk driver to address Stephen's comments.
I will send v4 patchset will updated clk driver.
Thanks,
Anup
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