From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Zhi Mao Subject: [PATCH 3/4] pwm: bindings: add MT2712/MT7622 information Date: Tue, 20 Jun 2017 14:54:15 +0800 Message-ID: <1497941657-23876-4-git-send-email-zhi.mao@mediatek.com> In-Reply-To: <1497941657-23876-1-git-send-email-zhi.mao@mediatek.com> References: <1497941657-23876-1-git-send-email-zhi.mao@mediatek.com> MIME-Version: 1.0 Content-Type: multipart/related; boundary="__=_Part_Boundary_005_1985091222.335773718" To: john@phrozen.org, Thierry Reding , Rob Herring , Mark Rutland , Matthias Brugger , linux-pwm@vger.kernel.org Cc: srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, zhi.mao@mediatek.com, yingjoe.chen@mediatek.com, yt.shen@mediatek.com, sean.wang@mediatek.com, zhenbao.liu@mediatek.com List-ID: --__=_Part_Boundary_005_1985091222.335773718 Content-Transfer-Encoding: base64 Content-Type: multipart/alternative; boundary="__=_Part_Boundary_006_912994621.458526291" --__=_Part_Boundary_006_912994621.458526291 Content-Type: text/html Content-Transfer-Encoding: base64 PHByZT4NCmFkZCBNVDI3MTIvTVQ3NjIyIHB3bSBpbmZvcm1hdGlvbg0KDQpTaWduZWQtb2ZmLWJ5 OiBaaGkgTWFvICZsdDt6aGkubWFvQG1lZGlhdGVrLmNvbSZndDsNCi0tLQ0KIC4uLi9kZXZpY2V0 cmVlL2JpbmRpbmdzL3B3bS9wd20tbWVkaWF0ZWsudHh0ICAgICAgIHwgICAgNiArKysrKy0NCiAx IGZpbGUgY2hhbmdlZCwgNSBpbnNlcnRpb25zKCspLCAxIGRlbGV0aW9uKC0pDQoNCmRpZmYgLS1n aXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvcHdtL3B3bS1tZWRpYXRlay50 eHQgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvcHdtL3B3bS1tZWRpYXRlay50 eHQNCmluZGV4IDU0YzU5YjAuLmVmOGJkM2MgMTAwNjQ0DQotLS0gYS9Eb2N1bWVudGF0aW9uL2Rl dmljZXRyZWUvYmluZGluZ3MvcHdtL3B3bS1tZWRpYXRlay50eHQNCisrKyBiL0RvY3VtZW50YXRp b24vZGV2aWNldHJlZS9iaW5kaW5ncy9wd20vcHdtLW1lZGlhdGVrLnR4dA0KQEAgLTIsNiArMiw4 IEBAIE1lZGlhVGVrIFBXTSBjb250cm9sbGVyDQogDQogUmVxdWlyZWQgcHJvcGVydGllczoNCiAg LSBjb21wYXRpYmxlOiBzaG91bGQgYmUgJnF1b3Q7bWVkaWF0ZWssJmx0O25hbWUmZ3Q7LXB3bSZx dW90OzoNCisgICAtICZxdW90O21lZGlhdGVrLG10MjcxMi1wd20mcXVvdDs6IGZvdW5kIG9uIG10 MjcxMiBTb0MuDQorICAgLSAmcXVvdDttZWRpYXRlayxtdDc2MjItcHdtJnF1b3Q7OiBmb3VuZCBv biBtdDc2MjIgU29DLg0KICAgIC0gJnF1b3Q7bWVkaWF0ZWssbXQ3NjIzLXB3bSZxdW90OzogZm91 bmQgb24gbXQ3NjIzIFNvQy4NCiAgLSByZWc6IHBoeXNpY2FsIGJhc2UgYWRkcmVzcyBhbmQgbGVu Z3RoIG9mIHRoZSBjb250cm9sbGVyJiMzOTtzIHJlZ2lzdGVycy4NCiAgLSAjcHdtLWNlbGxzOiBt dXN0IGJlIDIuIFNlZSBwd20udHh0IGluIHRoaXMgZGlyZWN0b3J5IGZvciBhIGRlc2NyaXB0aW9u IG9mDQpAQCAtMTAsNyArMTIsOSBAQCBSZXF1aXJlZCBwcm9wZXJ0aWVzOg0KICAtIGNsb2NrLW5h bWVzOiBtdXN0IGNvbnRhaW4gdGhlIGZvbGxvd2luZzoNCiAgICAtICZxdW90O3RvcCZxdW90Ozog dGhlIHRvcCBjbG9jayBnZW5lcmF0b3INCiAgICAtICZxdW90O21haW4mcXVvdDs6IGNsb2NrIHVz ZWQgYnkgdGhlIFBXTSBjb3JlDQotICAgLSAmcXVvdDtwd20xLTUmcXVvdDs6IHRoZSBmaXZlIHBl ciBQV00gY2xvY2tzDQorICAgLSAmcXVvdDtwd20xLTgmcXVvdDs6IHRoZSBlaWdodCBwZXIgUFdN IGNsb2NrcyBmb3IgbXQyNzEyDQorICAgLSAmcXVvdDtwd20xLTYmcXVvdDs6IHRoZSBzaXggcGVy IFBXTSBjbG9ja3MgZm9yIG10NzYyMg0KKyAgIC0gJnF1b3Q7cHdtMS01JnF1b3Q7OiB0aGUgZml2 ZSBwZXIgUFdNIGNsb2NrcyBmb3IgbXQ3NjIzDQogIC0gcGluY3RybC1uYW1lczogTXVzdCBjb250 YWluIGEgJnF1b3Q7ZGVmYXVsdCZxdW90OyBlbnRyeS4NCiAgLSBwaW5jdHJsLTA6IE9uZSBwcm9w ZXJ0eSBtdXN0IGV4aXN0IGZvciBlYWNoIGVudHJ5IGluIHBpbmN0cmwtbmFtZXMuDQogICAgU2Vl IHBpbmN0cmwvcGluY3RybC1iaW5kaW5ncy50eHQgZm9yIGRldGFpbHMgb2YgdGhlIHByb3BlcnR5 IHZhbHVlcy4NCi0tIA0KMS43LjkuNQ0KDQo8L3ByZT48IS0tdHlwZTp0ZXh0LS0+PCEtLXstLT48 cHJlPioqKioqKioqKioqKiogRW1haWwgQ29uZmlkZW50aWFsaXR5IE5vdGljZQ0KICoqKioqKioq KioqKioqKioqKioqDQpUaGUgaW5mb3JtYXRpb24gY29udGFpbmVkIGluIHRoaXMgZS1tYWlsIG1l c3NhZ2UgKGluY2x1ZGluZyBhbnkgDQphdHRhY2htZW50cykgbWF5IGJlIGNvbmZpZGVudGlhbCwg cHJvcHJpZXRhcnksIHByaXZpbGVnZWQsIG9yIG90aGVyd2lzZQ0KZXhlbXB0IGZyb20gZGlzY2xv c3VyZSB1bmRlciBhcHBsaWNhYmxlIGxhd3MuIEl0IGlzIGludGVuZGVkIHRvIGJlIA0KY29udmV5 ZWQgb25seSB0byB0aGUgZGVzaWduYXRlZCByZWNpcGllbnQocykuIEFueSB1c2UsIGRpc3NlbWlu YXRpb24sIA0KZGlzdHJpYnV0aW9uLCBwcmludGluZywgcmV0YWluaW5nIG9yIGNvcHlpbmcgb2Yg dGhpcyBlLW1haWwgKGluY2x1ZGluZyBpdHMgDQphdHRhY2htZW50cykgYnkgdW5pbnRlbmRlZCBy ZWNpcGllbnQocykgaXMgc3RyaWN0bHkgcHJvaGliaXRlZCBhbmQgbWF5IA0KYmUgdW5sYXdmdWwu IElmIHlvdSBhcmUgbm90IGFuIGludGVuZGVkIHJlY2lwaWVudCBvZiB0aGlzIGUtbWFpbCwgb3Ig YmVsaWV2ZQ0KIA0KdGhhdCB5b3UgaGF2ZSByZWNlaXZlZCB0aGlzIGUtbWFpbCBpbiBlcnJvciwg cGxlYXNlIG5vdGlmeSB0aGUgc2VuZGVyIA0KaW1tZWRpYXRlbHkgKGJ5IHJlcGx5aW5nIHRvIHRo aXMgZS1tYWlsKSwgZGVsZXRlIGFueSBhbmQgYWxsIGNvcGllcyBvZiANCnRoaXMgZS1tYWlsIChp bmNsdWRpbmcgYW55IGF0dGFjaG1lbnRzKSBmcm9tIHlvdXIgc3lzdGVtLCBhbmQgZG8gbm90DQpk aXNjbG9zZSB0aGUgY29udGVudCBvZiB0aGlzIGUtbWFpbCB0byBhbnkgb3RoZXIgcGVyc29uLiBU aGFuaw0KIHlvdSE8L3ByZT48IS0tfS0tPg== --__=_Part_Boundary_006_912994621.458526291 Content-Type: text/plain add MT2712/MT7622 pwm information Signed-off-by: Zhi Mao --- .../devicetree/bindings/pwm/pwm-mediatek.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index 54c59b0..ef8bd3c 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -2,6 +2,8 @@ MediaTek PWM controller Required properties: - compatible: should be "mediatek,-pwm": + - "mediatek,mt2712-pwm": found on mt2712 SoC. + - "mediatek,mt7622-pwm": found on mt7622 SoC. - "mediatek,mt7623-pwm": found on mt7623 SoC. - reg: physical base address and length of the controller's registers. - #pwm-cells: must be 2. See pwm.txt in this directory for a description of @@ -10,7 +12,9 @@ Required properties: - clock-names: must contain the following: - "top": the top clock generator - "main": clock used by the PWM core - - "pwm1-5": the five per PWM clocks + - "pwm1-8": the eight per PWM clocks for mt2712 + - "pwm1-6": the six per PWM clocks for mt7622 + - "pwm1-5": the five per PWM clocks for mt7623 - pinctrl-names: Must contain a "default" entry. - pinctrl-0: One property must exist for each entry in pinctrl-names. See pinctrl/pinctrl-bindings.txt for details of the property values. -- 1.7.9.5 --__=_Part_Boundary_006_912994621.458526291-- --__=_Part_Boundary_005_1985091222.335773718--