* [PATCH 1/4] pwm: kconfig: modify mediatek information
2017-06-20 6:54 [PATCH 0/4] mediatek: pwm driver add MT2712/MT7622 support Zhi Mao
@ 2017-06-20 6:54 ` Zhi Mao
2017-06-20 6:54 ` [PATCH 2/4] pwm: mediatek: fix clk issue Zhi Mao
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Zhi Mao @ 2017-06-20 6:54 UTC (permalink / raw)
To: john, Thierry Reding, Rob Herring, Mark Rutland, Matthias Brugger,
linux-pwm
Cc: srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, zhi.mao, yingjoe.chen, yt.shen, sean.wang,
zhenbao.liu
[-- Attachment #1.1: Type: text/html, Size: 1546 bytes --]
[-- Attachment #1.2: Type: text/plain, Size: 588 bytes --]
modify mediatek information
Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
---
drivers/pwm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 313c107..45cdf2a 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -300,7 +300,7 @@ config PWM_MEDIATEK
Generic PWM framework driver for Mediatek ARM SoC.
To compile this driver as a module, choose M here: the module
- will be called pwm-mxs.
+ will be called pwm-mediatek.
config PWM_MXS
tristate "Freescale MXS PWM support"
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/4] pwm: mediatek: fix clk issue
2017-06-20 6:54 [PATCH 0/4] mediatek: pwm driver add MT2712/MT7622 support Zhi Mao
2017-06-20 6:54 ` [PATCH 1/4] pwm: kconfig: modify mediatek information Zhi Mao
@ 2017-06-20 6:54 ` Zhi Mao
2017-06-20 7:00 ` John Crispin
2017-06-20 6:54 ` [PATCH 3/4] pwm: bindings: add MT2712/MT7622 information Zhi Mao
2017-06-20 6:54 ` [PATCH 4/4] pwm: mediatek: add MT2712/MT7622 support Zhi Mao
3 siblings, 1 reply; 6+ messages in thread
From: Zhi Mao @ 2017-06-20 6:54 UTC (permalink / raw)
To: john, Thierry Reding, Rob Herring, Mark Rutland, Matthias Brugger,
linux-pwm
Cc: srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, zhi.mao, yingjoe.chen, yt.shen, sean.wang,
zhenbao.liu
[-- Attachment #1.1: Type: text/html, Size: 5908 bytes --]
[-- Attachment #1.2: Type: text/plain, Size: 4629 bytes --]
1.fix clock control
- prepare top/main clk in mtk_pwm_probe() function,
it will increase power consumption
and in original code these clocks is only prepeare but never enabled
- pwm clock should be enabled before setting pwm registers
in function: mtk_pwm_config()
2.fix pwm source clock selection
- in original code, the pwm output frequency is not correct
when set bit<3>=1 to PWMCON register.
Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
---
drivers/pwm/pwm-mediatek.c | 69
+++++++++++++++++++++++++++-----------------
1 file changed, 43 insertions(+), 26 deletions(-)
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 5c11bc7..c803ff6 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -2,6 +2,7 @@
* Mediatek Pulse Width Modulator driver
*
* Copyright (C) 2015 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
@@ -61,6 +62,40 @@ static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct
pwm_chip *chip)
return container_of(chip, struct mtk_pwm_chip, chip);
}
+static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device
*pwm)
+{
+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
+ int ret = 0;
+
+ ret = clk_prepare_enable(pc->clks[MTK_CLK_TOP]);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_prepare_enable(pc->clks[MTK_CLK_MAIN]);
+ if (ret < 0) {
+ clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
+ if (ret < 0) {
+ clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
+ clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
+ return ret;
+ }
+
+ return ret;
+}
+
+static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device
*pwm)
+{
+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
+
+ clk_disable_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
+ clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
+ clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
+}
+
static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int
num,
unsigned int offset)
{
@@ -81,6 +116,8 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct
pwm_device *pwm,
struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm];
u32 resolution, clkdiv = 0;
+ mtk_pwm_clk_enable(chip, pwm);
+
resolution = NSEC_PER_SEC / clk_get_rate(clk);
while (period_ns / resolution > 8191) {
@@ -91,10 +128,12 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct
pwm_device *pwm,
if (clkdiv > 7)
return -EINVAL;
- mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
+ mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
+ mtk_pwm_clk_disable(chip, pwm);
+
return 0;
}
@@ -102,11 +141,8 @@ static int mtk_pwm_enable(struct pwm_chip *chip, struct
pwm_device *pwm)
{
struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
u32 value;
- int ret;
- ret = clk_prepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
- if (ret < 0)
- return ret;
+ mtk_pwm_clk_enable(chip, pwm);
value = readl(pc->regs);
value |= BIT(pwm->hwpwm);
@@ -124,7 +160,7 @@ static void mtk_pwm_disable(struct pwm_chip *chip,
struct pwm_device *pwm)
value &= ~BIT(pwm->hwpwm);
writel(value, pc->regs);
- clk_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
+ mtk_pwm_clk_disable(chip, pwm);
}
static const struct pwm_ops mtk_pwm_ops = {
@@ -156,14 +192,6 @@ static int mtk_pwm_probe(struct platform_device *pdev)
return PTR_ERR(pc->clks[i]);
}
- ret = clk_prepare(pc->clks[MTK_CLK_TOP]);
- if (ret < 0)
- return ret;
-
- ret = clk_prepare(pc->clks[MTK_CLK_MAIN]);
- if (ret < 0)
- goto disable_clk_top;
-
platform_set_drvdata(pdev, pc);
pc->chip.dev = &pdev->dev;
@@ -174,26 +202,15 @@ static int mtk_pwm_probe(struct platform_device *pdev)
ret = pwmchip_add(&pc->chip);
if (ret < 0) {
dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
- goto disable_clk_main;
+ return ret;
}
return 0;
-
-disable_clk_main:
- clk_unprepare(pc->clks[MTK_CLK_MAIN]);
-disable_clk_top:
- clk_unprepare(pc->clks[MTK_CLK_TOP]);
-
- return ret;
}
static int mtk_pwm_remove(struct platform_device *pdev)
{
struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
- unsigned int i;
-
- for (i = 0; i < pc->chip.npwm; i++)
- pwm_disable(&pc->chip.pwms[i]);
return pwmchip_remove(&pc->chip);
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/4] pwm: mediatek: fix clk issue
2017-06-20 6:54 ` [PATCH 2/4] pwm: mediatek: fix clk issue Zhi Mao
@ 2017-06-20 7:00 ` John Crispin
0 siblings, 0 replies; 6+ messages in thread
From: John Crispin @ 2017-06-20 7:00 UTC (permalink / raw)
To: Zhi Mao, Thierry Reding, Rob Herring, Mark Rutland,
Matthias Brugger, linux-pwm
Cc: srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, yingjoe.chen, yt.shen, sean.wang, zhenbao.liu
On 20/06/17 08:54, Zhi Mao wrote:
> 1.fix clock control
> - prepare top/main clk in mtk_pwm_probe() function,
> it will increase power consumption
> and in original code these clocks is only prepeare but never enabled
> - pwm clock should be enabled before setting pwm registers
> in function: mtk_pwm_config()
>
> 2.fix pwm source clock selection
> - in original code, the pwm output frequency is not correct
> when set bit<3>=1 to PWMCON register.
>
> Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
Hi Zhi,
it looks like you sent the series as text/html and also as text/plain
with lines getting wrapped. You might want to try and use "git send-email"
> ---
> drivers/pwm/pwm-mediatek.c | 69
> +++++++++++++++++++++++++++-----------------
> 1 file changed, 43 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
> index 5c11bc7..c803ff6 100644
> --- a/drivers/pwm/pwm-mediatek.c
> +++ b/drivers/pwm/pwm-mediatek.c
[ ... ]
> @@ -61,6 +62,40 @@ static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct
> pwm_chip *chip)
> return container_of(chip, struct mtk_pwm_chip, chip);
> }
>
> +static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device
> *pwm)
^^ here for example
John
> +{
> + struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
> + int ret = 0;
> +
> + ret = clk_prepare_enable(pc->clks[MTK_CLK_TOP]);
> + if (ret < 0)
> + return ret;
> +
> + ret = clk_prepare_enable(pc->clks[MTK_CLK_MAIN]);
> + if (ret < 0) {
> + clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
> + return ret;
> + }
> +
> + ret = clk_prepare_enable(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
> + if (ret < 0) {
> + clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
> + clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
> + return ret;
> + }
> +
> + return ret;
> +}
> +
> +static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device
> *pwm)
> +{
> + struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
> +
> + clk_disable_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
> + clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]);
> + clk_disable_unprepare(pc->clks[MTK_CLK_TOP]);
> +}
> +
> static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int
> num,
> unsigned int offset)
> {
> @@ -81,6 +116,8 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct
> pwm_device *pwm,
> struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm];
> u32 resolution, clkdiv = 0;
>
> + mtk_pwm_clk_enable(chip, pwm);
> +
> resolution = NSEC_PER_SEC / clk_get_rate(clk);
>
> while (period_ns / resolution > 8191) {
> @@ -91,10 +128,12 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct
> pwm_device *pwm,
> if (clkdiv > 7)
> return -EINVAL;
>
> - mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
> + mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
> mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
> mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
>
> + mtk_pwm_clk_disable(chip, pwm);
> +
> return 0;
> }
>
> @@ -102,11 +141,8 @@ static int mtk_pwm_enable(struct pwm_chip *chip, struct
> pwm_device *pwm)
> {
> struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
> u32 value;
> - int ret;
>
> - ret = clk_prepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
> - if (ret < 0)
> - return ret;
> + mtk_pwm_clk_enable(chip, pwm);
>
> value = readl(pc->regs);
> value |= BIT(pwm->hwpwm);
> @@ -124,7 +160,7 @@ static void mtk_pwm_disable(struct pwm_chip *chip,
> struct pwm_device *pwm)
> value &= ~BIT(pwm->hwpwm);
> writel(value, pc->regs);
>
> - clk_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
> + mtk_pwm_clk_disable(chip, pwm);
> }
>
> static const struct pwm_ops mtk_pwm_ops = {
> @@ -156,14 +192,6 @@ static int mtk_pwm_probe(struct platform_device *pdev)
> return PTR_ERR(pc->clks[i]);
> }
>
> - ret = clk_prepare(pc->clks[MTK_CLK_TOP]);
> - if (ret < 0)
> - return ret;
> -
> - ret = clk_prepare(pc->clks[MTK_CLK_MAIN]);
> - if (ret < 0)
> - goto disable_clk_top;
> -
> platform_set_drvdata(pdev, pc);
>
> pc->chip.dev = &pdev->dev;
> @@ -174,26 +202,15 @@ static int mtk_pwm_probe(struct platform_device *pdev)
> ret = pwmchip_add(&pc->chip);
> if (ret < 0) {
> dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
> - goto disable_clk_main;
> + return ret;
> }
>
> return 0;
> -
> -disable_clk_main:
> - clk_unprepare(pc->clks[MTK_CLK_MAIN]);
> -disable_clk_top:
> - clk_unprepare(pc->clks[MTK_CLK_TOP]);
> -
> - return ret;
> }
>
> static int mtk_pwm_remove(struct platform_device *pdev)
> {
> struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
> - unsigned int i;
> -
> - for (i = 0; i < pc->chip.npwm; i++)
> - pwm_disable(&pc->chip.pwms[i]);
>
> return pwmchip_remove(&pc->chip);
> }
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/4] pwm: bindings: add MT2712/MT7622 information
2017-06-20 6:54 [PATCH 0/4] mediatek: pwm driver add MT2712/MT7622 support Zhi Mao
2017-06-20 6:54 ` [PATCH 1/4] pwm: kconfig: modify mediatek information Zhi Mao
2017-06-20 6:54 ` [PATCH 2/4] pwm: mediatek: fix clk issue Zhi Mao
@ 2017-06-20 6:54 ` Zhi Mao
2017-06-20 6:54 ` [PATCH 4/4] pwm: mediatek: add MT2712/MT7622 support Zhi Mao
3 siblings, 0 replies; 6+ messages in thread
From: Zhi Mao @ 2017-06-20 6:54 UTC (permalink / raw)
To: john, Thierry Reding, Rob Herring, Mark Rutland, Matthias Brugger,
linux-pwm
Cc: srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, zhi.mao, yingjoe.chen, yt.shen, sean.wang,
zhenbao.liu
[-- Attachment #1.1: Type: text/html, Size: 2533 bytes --]
[-- Attachment #1.2: Type: text/plain, Size: 1456 bytes --]
add MT2712/MT7622 pwm information
Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
---
.../devicetree/bindings/pwm/pwm-mediatek.txt | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
index 54c59b0..ef8bd3c 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
@@ -2,6 +2,8 @@ MediaTek PWM controller
Required properties:
- compatible: should be "mediatek,<name>-pwm":
+ - "mediatek,mt2712-pwm": found on mt2712 SoC.
+ - "mediatek,mt7622-pwm": found on mt7622 SoC.
- "mediatek,mt7623-pwm": found on mt7623 SoC.
- reg: physical base address and length of the controller's registers.
- #pwm-cells: must be 2. See pwm.txt in this directory for a description
of
@@ -10,7 +12,9 @@ Required properties:
- clock-names: must contain the following:
- "top": the top clock generator
- "main": clock used by the PWM core
- - "pwm1-5": the five per PWM clocks
+ - "pwm1-8": the eight per PWM clocks for mt2712
+ - "pwm1-6": the six per PWM clocks for mt7622
+ - "pwm1-5": the five per PWM clocks for mt7623
- pinctrl-names: Must contain a "default" entry.
- pinctrl-0: One property must exist for each entry in pinctrl-names.
See pinctrl/pinctrl-bindings.txt for details of the property values.
--
1.7.9.5
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/4] pwm: mediatek: add MT2712/MT7622 support
2017-06-20 6:54 [PATCH 0/4] mediatek: pwm driver add MT2712/MT7622 support Zhi Mao
` (2 preceding siblings ...)
2017-06-20 6:54 ` [PATCH 3/4] pwm: bindings: add MT2712/MT7622 information Zhi Mao
@ 2017-06-20 6:54 ` Zhi Mao
3 siblings, 0 replies; 6+ messages in thread
From: Zhi Mao @ 2017-06-20 6:54 UTC (permalink / raw)
To: john, Thierry Reding, Rob Herring, Mark Rutland, Matthias Brugger,
linux-pwm
Cc: srv_heupstream, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, zhi.mao, yingjoe.chen, yt.shen, sean.wang,
zhenbao.liu
[-- Attachment #1.1: Type: text/html, Size: 5895 bytes --]
[-- Attachment #1.2: Type: text/plain, Size: 4391 bytes --]
support multiple chip(MT2712, MT7622, MT7623)
Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
---
drivers/pwm/pwm-mediatek.c | 63
+++++++++++++++++++++++++++++++++++---------
1 file changed, 51 insertions(+), 12 deletions(-)
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index c803ff6..d520356 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -16,6 +16,7 @@
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
@@ -30,6 +31,8 @@
#define PWMDWIDTH 0x2c
#define PWMTHRES 0x30
+#define PWM_CLK_DIV_MAX 7
+
enum {
MTK_CLK_MAIN = 0,
MTK_CLK_TOP,
@@ -38,11 +41,19 @@ enum {
MTK_CLK_PWM3,
MTK_CLK_PWM4,
MTK_CLK_PWM5,
+ MTK_CLK_PWM6,
+ MTK_CLK_PWM7,
+ MTK_CLK_PWM8,
MTK_CLK_MAX,
};
-static const char * const mtk_pwm_clk_name[] = {
- "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5"
+static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = {
+ "main", "top", "pwm1", "pwm2", "pwm3", "pwm4",
+ "pwm5", "pwm6", "pwm7", "pwm8"
+};
+
+struct mtk_com_pwm_data {
+ unsigned int pwm_nums;
};
/**
@@ -55,6 +66,11 @@ struct mtk_pwm_chip {
struct pwm_chip chip;
void __iomem *regs;
struct clk *clks[MTK_CLK_MAX];
+ const struct mtk_com_pwm_data *data;
+};
+
+static const unsigned long mtk_pwm_com_reg[] = {
+ 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
};
static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
@@ -99,14 +115,14 @@ static void mtk_pwm_clk_disable(struct pwm_chip *chip,
struct pwm_device *pwm)
static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int
num,
unsigned int offset)
{
- return readl(chip->regs + 0x10 + (num * 0x40) + offset);
+ return readl(chip->regs + mtk_pwm_com_reg[num] + offset);
}
static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
unsigned int num, unsigned int offset,
u32 value)
{
- writel(value, chip->regs + 0x10 + (num * 0x40) + offset);
+ writel(value, chip->regs + mtk_pwm_com_reg[num] + offset);
}
static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
@@ -125,8 +141,10 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct
pwm_device *pwm,
clkdiv++;
}
- if (clkdiv > 7)
+ if (clkdiv > PWM_CLK_DIV_MAX) {
+ dev_err(chip->dev, "period %d not supported\n", period_ns);
return -EINVAL;
+ }
mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
@@ -181,23 +199,28 @@ static int mtk_pwm_probe(struct platform_device *pdev)
if (!pc)
return -ENOMEM;
+ pc->data = of_device_get_match_data(&pdev->dev);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pc->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pc->regs))
return PTR_ERR(pc->regs);
- for (i = 0; i < MTK_CLK_MAX; i++) {
+ for (i = 0; i < pc->data->pwm_nums + 2; i++) {
pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]);
- if (IS_ERR(pc->clks[i]))
+ if (IS_ERR(pc->clks[i])) {
+ dev_err(&pdev->dev, "[PWM] clock: %s fail: %ld\n",
+ mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i]));
return PTR_ERR(pc->clks[i]);
+ }
}
- platform_set_drvdata(pdev, pc);
-
pc->chip.dev = &pdev->dev;
pc->chip.ops = &mtk_pwm_ops;
pc->chip.base = -1;
- pc->chip.npwm = 5;
+ pc->chip.npwm = pc->data->pwm_nums;
+
+ platform_set_drvdata(pdev, pc);
ret = pwmchip_add(&pc->chip);
if (ret < 0) {
@@ -215,9 +238,25 @@ static int mtk_pwm_remove(struct platform_device *pdev)
return pwmchip_remove(&pc->chip);
}
+/*==========================================*/
+static const struct mtk_com_pwm_data mt2712_pwm_data = {
+ .pwm_nums = 8,
+};
+
+static const struct mtk_com_pwm_data mt7622_pwm_data = {
+ .pwm_nums = 6,
+};
+
+static const struct mtk_com_pwm_data mt7623_pwm_data = {
+ .pwm_nums = 5,
+};
+/*==========================================*/
+
static const struct of_device_id mtk_pwm_of_match[] = {
- { .compatible = "mediatek,mt7623-pwm" },
- { }
+ {.compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data},
+ {.compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data},
+ {.compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data},
+ {},
};
MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
--
1.7.9.5
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