From: Varadarajan Narayanan <varada@codeaurora.org>
To: broonie@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com,
andy.gross@linaro.org, david.brown@linaro.org,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-soc@vger.kernel.org
Cc: Varadarajan Narayanan <varada@codeaurora.org>,
Matthew McClintock <mmcclint@codeaurora.org>
Subject: [PATCH v4 09/14] spi: qup: refactor spi_qup_io_config into two functions
Date: Tue, 27 Jun 2017 15:15:26 +0530 [thread overview]
Message-ID: <1498556731-13087-10-git-send-email-varada@codeaurora.org> (raw)
In-Reply-To: <1498556731-13087-1-git-send-email-varada@codeaurora.org>
This is in preparation for handling transactions larger than
64K-1 bytes in block mode, which is currently unsupported and
quietly fails.
We need to break these into two functions 1) prep is
called once per spi_message and 2) io_config is called
once per spi-qup bus transaction
This is just refactoring, there should be no functional
change
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
drivers/spi/spi-qup.c | 109 +++++++++++++++++++++++++++++++-------------------
1 file changed, 67 insertions(+), 42 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 1a83248..bfb6d27 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -543,12 +543,11 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
-/* set clock freq ... bits per word */
-static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
+/* set clock freq ... bits per word, determine mode */
+static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
{
struct spi_qup *controller = spi_master_get_devdata(spi->master);
- u32 config, iomode, control;
- int ret, n_words;
+ int ret;
if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
dev_err(controller->dev, "too big size for loopback %d > %d\n",
@@ -563,32 +562,59 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
return -EIO;
}
- if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
- dev_err(controller->dev, "cannot set RESET state\n");
- return -EIO;
- }
-
controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8);
controller->n_words = xfer->len / controller->w_size;
- n_words = controller->n_words;
-
- if (n_words <= (controller->in_fifo_sz / sizeof(u32))) {
+ if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32)))
controller->mode = QUP_IO_M_MODE_FIFO;
+ else if (spi->master->can_dma &&
+ spi->master->can_dma(spi->master, spi, xfer) &&
+ spi->master->cur_msg_mapped)
+ controller->mode = QUP_IO_M_MODE_BAM;
+ else
+ controller->mode = QUP_IO_M_MODE_BLOCK;
+
+ return 0;
+}
+
+/* prep qup for another spi transaction of specific type */
+static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
+{
+ struct spi_qup *controller = spi_master_get_devdata(spi->master);
+ u32 config, iomode, control;
+ unsigned long flags;
+
+ spin_lock_irqsave(&controller->lock, flags);
+ controller->xfer = xfer;
+ controller->error = 0;
+ controller->rx_bytes = 0;
+ controller->tx_bytes = 0;
+ spin_unlock_irqrestore(&controller->lock, flags);
+
+
+ if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
+ dev_err(controller->dev, "cannot set RESET state\n");
+ return -EIO;
+ }
- writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
- writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
+ switch (controller->mode) {
+ case QUP_IO_M_MODE_FIFO:
+ reinit_completion(&controller->done);
+ writel_relaxed(controller->n_words,
+ controller->base + QUP_MX_READ_CNT);
+ writel_relaxed(controller->n_words,
+ controller->base + QUP_MX_WRITE_CNT);
/* must be zero for FIFO */
writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
- } else if (spi->master->can_dma &&
- spi->master->can_dma(spi->master, spi, xfer) &&
- spi->master->cur_msg_mapped) {
-
- controller->mode = QUP_IO_M_MODE_BAM;
-
- writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
- writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
+ break;
+ case QUP_IO_M_MODE_BAM:
+ reinit_completion(&controller->txc);
+ reinit_completion(&controller->rxc);
+ writel_relaxed(controller->n_words,
+ controller->base + QUP_MX_INPUT_CNT);
+ writel_relaxed(controller->n_words,
+ controller->base + QUP_MX_OUTPUT_CNT);
/* must be zero for BLOCK and BAM */
writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
@@ -606,19 +632,25 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
if (xfer->tx_buf)
writel_relaxed(0, input_cnt);
else
- writel_relaxed(n_words, input_cnt);
+ writel_relaxed(controller->n_words, input_cnt);
writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
}
- } else {
-
- controller->mode = QUP_IO_M_MODE_BLOCK;
-
- writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
- writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
+ break;
+ case QUP_IO_M_MODE_BLOCK:
+ reinit_completion(&controller->done);
+ writel_relaxed(controller->n_words,
+ controller->base + QUP_MX_INPUT_CNT);
+ writel_relaxed(controller->n_words,
+ controller->base + QUP_MX_OUTPUT_CNT);
/* must be zero for BLOCK and BAM */
writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
+ break;
+ default:
+ dev_err(controller->dev, "unknown mode = %d\n",
+ controller->mode);
+ return -EIO;
}
iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
@@ -707,6 +739,10 @@ static int spi_qup_transfer_one(struct spi_master *master,
unsigned long timeout, flags;
int ret = -EIO;
+ ret = spi_qup_io_prep(spi, xfer);
+ if (ret)
+ return ret;
+
ret = spi_qup_io_config(spi, xfer);
if (ret)
return ret;
@@ -715,21 +751,10 @@ static int spi_qup_transfer_one(struct spi_master *master,
timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
timeout = 100 * msecs_to_jiffies(timeout);
- spin_lock_irqsave(&controller->lock, flags);
- controller->xfer = xfer;
- controller->error = 0;
- controller->rx_bytes = 0;
- controller->tx_bytes = 0;
- spin_unlock_irqrestore(&controller->lock, flags);
-
- if (spi_qup_is_dma_xfer(controller->mode)) {
- reinit_completion(&controller->rxc);
- reinit_completion(&controller->txc);
+ if (spi_qup_is_dma_xfer(controller->mode))
ret = spi_qup_do_dma(master, xfer, timeout);
- } else {
- reinit_completion(&controller->done);
+ else
ret = spi_qup_do_pio(master, xfer, timeout);
- }
if (ret)
goto exit;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2017-06-27 9:45 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-27 9:45 [PATCH v4 00/14] spi: qup: Fixes and add support for >64k transfers Varadarajan Narayanan
2017-06-27 9:45 ` [PATCH v4 01/14] spi: qup: Enable chip select support Varadarajan Narayanan
2017-07-17 16:01 ` Mark Brown
[not found] ` <20170717160151.teozg2ni4mqxotbd-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
2017-07-20 5:30 ` Varadarajan Narayanan
[not found] ` <1498556731-13087-2-git-send-email-varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-20 7:03 ` Geert Uytterhoeven
[not found] ` <1498556731-13087-1-git-send-email-varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-06-27 9:45 ` [PATCH v4 02/14] spi: qup: Setup DMA mode correctly Varadarajan Narayanan
2017-06-27 9:45 ` [PATCH v4 03/14] spi: qup: Add completion structures for DMA Varadarajan Narayanan
2017-07-17 16:02 ` Mark Brown
2017-06-27 9:45 ` [PATCH v4 04/14] spi: qup: Add completion timeout Varadarajan Narayanan
2017-06-27 9:45 ` [PATCH v4 06/14] spi: qup: Fix error handling in spi_qup_prep_sg Varadarajan Narayanan
2017-06-27 9:45 ` [PATCH v4 05/14] spi: qup: Place the QUP in run mode before DMA Varadarajan Narayanan
2017-06-27 9:45 ` [PATCH v4 07/14] spi: qup: Fix transaction done signaling Varadarajan Narayanan
2017-06-27 9:45 ` [PATCH v4 08/14] spi: qup: Do block sized read/write in block mode Varadarajan Narayanan
2017-06-27 9:45 ` Varadarajan Narayanan [this message]
2017-06-27 9:45 ` [PATCH v4 10/14] spi: qup: call io_config in mode specific function Varadarajan Narayanan
2017-06-27 9:45 ` [PATCH v4 11/14] spi: qup: allow block mode to generate multiple transactions Varadarajan Narayanan
2017-06-27 9:45 ` [PATCH v4 12/14] spi: qup: refactor spi_qup_prep_sg Varadarajan Narayanan
2017-06-27 9:45 ` [PATCH v4 13/14] spi: qup: allow multiple DMA transactions per spi xfer Varadarajan Narayanan
2017-06-27 9:45 ` [PATCH v4 14/14] spi: qup: Ensure done detection Varadarajan Narayanan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1498556731-13087-10-git-send-email-varada@codeaurora.org \
--to=varada@codeaurora.org \
--cc=andy.gross@linaro.org \
--cc=broonie@kernel.org \
--cc=david.brown@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-soc@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mmcclint@codeaurora.org \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).