From: Abhishek Sahu <absahu@codeaurora.org>
To: dwmw2@infradead.org, computersforpeace@gmail.com,
boris.brezillon@free-electrons.com, marek.vasut@gmail.com,
richard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org,
mark.rutland@arm.com
Cc: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
andy.gross@linaro.org, architt@codeaurora.org,
sricharan@codeaurora.org, Abhishek Sahu <absahu@codeaurora.org>
Subject: [PATCH 11/14] qcom: mtd: nand: BAM raw read and write support
Date: Thu, 29 Jun 2017 12:46:03 +0530 [thread overview]
Message-ID: <1498720566-20782-12-git-send-email-absahu@codeaurora.org> (raw)
In-Reply-To: <1498720566-20782-1-git-send-email-absahu@codeaurora.org>
1. BAM uses READ_LOCATION registers to copy data from offset
into data buffer.
2. BAM requires EOT flag should be set only for the last data
write in a codeword.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 46 ++++++++++++++++++++++++++++++++++++++-----
1 file changed, 41 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 4c6e594..6d749b6 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -1033,7 +1033,7 @@ static void config_bam_page_read(struct qcom_nand_controller *nandc)
*/
static void config_bam_cw_read(struct qcom_nand_controller *nandc)
{
- write_reg_dma(nandc, NAND_READ_LOCATION_0, 2, 0);
+ write_reg_dma(nandc, NAND_READ_LOCATION_0, 4, 0);
write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
@@ -1734,6 +1734,7 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
u8 *data_buf, *oob_buf;
struct nand_ecc_ctrl *ecc = &chip->ecc;
int i, ret;
+ int read_location;
data_buf = buf;
oob_buf = chip->oob_poi;
@@ -1743,6 +1744,9 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
clear_bam_transaction(nandc);
update_rw_regs(host, ecc->steps, true);
+ if (nandc->dma_bam_enabled)
+ config_bam_page_read(nandc);
+
for (i = 0; i < ecc->steps; i++) {
int data_size1, data_size2, oob_size1, oob_size2;
int reg_off = FLASH_BUF_ACC;
@@ -1760,7 +1764,35 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
}
- config_cw_read(nandc);
+ if (nandc->dma_bam_enabled) {
+ read_location = 0;
+ nandc_set_reg(nandc, NAND_READ_LOCATION_0,
+ (read_location << READ_LOCATION_OFFSET) |
+ (data_size1 << READ_LOCATION_SIZE) |
+ (0 << READ_LOCATION_LAST));
+ read_location += data_size1;
+
+ nandc_set_reg(nandc, NAND_READ_LOCATION_1,
+ (read_location << READ_LOCATION_OFFSET) |
+ (oob_size1 << READ_LOCATION_SIZE) |
+ (0 << READ_LOCATION_LAST));
+ read_location += oob_size1;
+
+ nandc_set_reg(nandc, NAND_READ_LOCATION_2,
+ (read_location << READ_LOCATION_OFFSET) |
+ (data_size2 << READ_LOCATION_SIZE) |
+ (0 << READ_LOCATION_LAST));
+ read_location += data_size2;
+
+ nandc_set_reg(nandc, NAND_READ_LOCATION_3,
+ (read_location << READ_LOCATION_OFFSET) |
+ (oob_size2 << READ_LOCATION_SIZE) |
+ (1 << READ_LOCATION_LAST));
+
+ config_bam_cw_read(nandc);
+ } else {
+ config_cw_read(nandc);
+ }
read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
reg_off += data_size1;
@@ -1914,15 +1946,18 @@ static int qcom_nandc_write_page_raw(struct mtd_info *mtd,
config_cw_write_pre(nandc);
- write_data_dma(nandc, reg_off, data_buf, data_size1, 0);
+ write_data_dma(nandc, reg_off, data_buf, data_size1,
+ NAND_BAM_NO_EOT);
reg_off += data_size1;
data_buf += data_size1;
- write_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
+ write_data_dma(nandc, reg_off, oob_buf, oob_size1,
+ NAND_BAM_NO_EOT);
reg_off += oob_size1;
oob_buf += oob_size1;
- write_data_dma(nandc, reg_off, data_buf, data_size2, 0);
+ write_data_dma(nandc, reg_off, data_buf, data_size2,
+ NAND_BAM_NO_EOT);
reg_off += data_size2;
data_buf += data_size2;
@@ -1968,6 +2003,7 @@ static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
return ret;
clear_read_regs(nandc);
+ clear_bam_transaction(nandc);
/* calculate the data and oob size for the last codeword/step */
data_size = ecc->size - ((ecc->steps - 1) << 2);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2017-06-29 7:16 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-29 7:15 [PATCH 00/14] Add QCOM QPIC NAND support Abhishek Sahu
[not found] ` <1498720566-20782-1-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-06-29 7:15 ` [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA Abhishek Sahu
2017-06-29 9:46 ` Marek Vasut
2017-07-03 4:38 ` Archit Taneja
2017-07-03 19:41 ` Boris Brezillon
2017-07-17 6:11 ` Abhishek Sahu
[not found] ` <bfb3d3c466e60fa08f969ea485870ba4-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-17 7:22 ` Boris Brezillon
2017-07-17 8:49 ` Abhishek Sahu
2017-07-03 6:21 ` Sricharan R
2017-06-29 7:15 ` [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources Abhishek Sahu
2017-06-29 9:48 ` Marek Vasut
[not found] ` <01e12a9a-4f3b-1bde-473a-3cbe3f72ef74-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-07-17 6:36 ` Abhishek Sahu
[not found] ` <1498720566-20782-3-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-03 5:17 ` Archit Taneja
2017-07-17 6:26 ` Abhishek Sahu
2017-07-03 6:24 ` Sricharan R
2017-07-03 6:32 ` Sricharan R
2017-06-29 7:15 ` [PATCH 06/14] qcom: mtd: nand: add bam dma descriptor handling Abhishek Sahu
[not found] ` <1498720566-20782-7-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-04 6:10 ` Archit Taneja
[not found] ` <021637c8-8ce5-c54e-0254-41caa475063c-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-17 6:47 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 09/14] qcom: mtd: nand: BAM support for read page Abhishek Sahu
2017-07-04 9:40 ` Archit Taneja
2017-07-10 14:15 ` Sricharan R
2017-07-17 7:17 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 13/14] qcom: mtd: nand: support for QPIC version 1.5.0 Abhishek Sahu
2017-07-04 9:57 ` Archit Taneja
[not found] ` <d6566f4e-c55b-18ed-611b-35bc191b2f5f-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-17 7:32 ` Abhishek Sahu
2017-06-29 7:15 ` [PATCH 03/14] qcom: mtd: nand: Fixed config error for BCH Abhishek Sahu
2017-06-29 9:49 ` Marek Vasut
2017-07-03 19:47 ` Boris Brezillon
2017-07-17 6:38 ` Abhishek Sahu
[not found] ` <1498720566-20782-4-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-03 6:25 ` Sricharan R
2017-06-29 7:15 ` [PATCH 04/14] qcom: mtd: nand: reorganize nand devices probing Abhishek Sahu
2017-06-29 7:15 ` [PATCH 05/14] qcom: mtd: nand: allocate bam transaction Abhishek Sahu
[not found] ` <1498720566-20782-6-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-06-29 9:50 ` Marek Vasut
[not found] ` <659d69fd-ae7c-b566-ccab-aca2a3efe178-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-07-17 6:42 ` Abhishek Sahu
2017-07-03 8:22 ` Sricharan R
[not found] ` <906da0d9-2ef7-583a-4008-4f444eaa340b-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-17 6:44 ` Abhishek Sahu
2017-06-29 7:15 ` [PATCH 07/14] qcom: mtd: nand: support for passing flags in transfer functions Abhishek Sahu
2017-06-29 9:52 ` Marek Vasut
[not found] ` <1498720566-20782-8-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-04 6:49 ` Archit Taneja
2017-07-10 14:10 ` Sricharan R
[not found] ` <70776f79-6d51-5544-8be8-38e62b7c073e-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-17 6:59 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 08/14] qcom: mtd: nand: Add support for additional CSRs Abhishek Sahu
2017-07-04 6:54 ` Archit Taneja
2017-07-17 7:10 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 10/14] qcom: mtd: nand: support for QPIC Page read/write Abhishek Sahu
[not found] ` <1498720566-20782-11-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-04 9:44 ` Archit Taneja
2017-07-17 7:25 ` Abhishek Sahu
2017-07-10 14:18 ` Sricharan R
2017-07-17 7:36 ` Abhishek Sahu
2017-06-29 7:16 ` Abhishek Sahu [this message]
2017-06-29 7:16 ` [PATCH 12/14] qcom: mtd: nand: change register offset defines with enums Abhishek Sahu
2017-07-04 9:55 ` Archit Taneja
[not found] ` <a8961294-c72b-035c-0924-f0f901821ea4-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-07-17 7:31 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 14/14] qcom: mtd: nand: programmed NAND_DEV_CMD_VLD register Abhishek Sahu
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