[PATCH 1/3] dts: ls2088a: add pcie support

[PATCH 1/3] dts: ls2088a: add pcie support

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org>

The physical memory map address and CCSR registers map address are
different between LS2088A and other LS2080A series SoCs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org>
---
 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index 5c695c6..7d26531 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -134,6 +134,7 @@
 };
 
 &pcie1 {
+	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
 	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 	       0x20 0x00000000 0x0 0x00002000>; /* configuration space */
 
@@ -142,6 +143,7 @@
 };
 
 &pcie2 {
+	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
 	reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 	       0x28 0x00000000 0x0 0x00002000>; /* configuration space */
 
@@ -150,6 +152,7 @@
 };
 
 &pcie3 {
+	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
 	reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 	       0x30 0x00000000 0x0 0x00002000>; /* configuration space */
 
@@ -158,6 +161,7 @@
 };
 
 &pcie4 {
+	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
 	reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
 	       0x38 0x00000000 0x0 0x00002000>; /* configuration space */
 
-- 
2.1.0.27.g96db324

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[PATCH 2/3] dts: ls1088a: add gicv3 ITS DT node

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org>

Add ITS device tree node, which will be used by PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org>
---
 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index c144d06..5f35797 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -126,6 +126,15 @@
 		      <0x0 0x0c0d0000 0 0x1000>, /* GICH */
 		      <0x0 0x0c0e0000 0 0x20000>; /* GICV */
 		interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		its: gic-its@6020000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0x6020000 0 0x20000>;
+		};
 	};
 
 	timer {
-- 
2.1.0.27.g96db324

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[PATCH 3/3] dts: ls1088a: add PCIe controller DT nodes

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org>

The LS1088a implements 3 PCIe 3.0 controllers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org>
---
 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 75 ++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 5f35797..b13b677 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -378,6 +378,81 @@
 			dma-coherent;
 			status = "disabled";
 		};
+		pcie@3400000 {
+			compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
+				     "snps,dw-pcie";
+			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+			       0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			num-lanes = <4>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pcie@3500000 {
+			compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
+				     "snps,dw-pcie";
+			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+			       0x28 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			num-lanes = <4>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pcie@3600000 {
+			compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
+				     "snps,dw-pcie";
+			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
+			       0x30 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+			interrupt-names = "aer";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			num-lanes = <8>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&its>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
+					<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 	};
 
 };
-- 
2.1.0.27.g96db324

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Re: [PATCH 1/3] dts: ls2088a: add pcie support

[Shawn Guo]

On Thu, Jul 06, 2017 at 04:55:28PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org>
> 
> The physical memory map address and CCSR registers map address are
> different between LS2088A and other LS2080A series SoCs.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org>
> ---
>  arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> index 5c695c6..7d26531 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> @@ -134,6 +134,7 @@
>  };
>  
>  &pcie1 {
> +	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";

I do not see "fsl,ls2088a-pcie" in either bindings doc or kernel driver.

Shawn

>  	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
>  	       0x20 0x00000000 0x0 0x00002000>; /* configuration space */
>  
> @@ -142,6 +143,7 @@
>  };
>  
>  &pcie2 {
> +	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
>  	reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
>  	       0x28 0x00000000 0x0 0x00002000>; /* configuration space */
>  
> @@ -150,6 +152,7 @@
>  };
>  
>  &pcie3 {
> +	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
>  	reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
>  	       0x30 0x00000000 0x0 0x00002000>; /* configuration space */
>  
> @@ -158,6 +161,7 @@
>  };
>  
>  &pcie4 {
> +	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
>  	reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
>  	       0x38 0x00000000 0x0 0x00002000>; /* configuration space */
>  
> -- 
> 2.1.0.27.g96db324
> 
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RE: [PATCH 1/3] dts: ls2088a: add pcie support

[Z.q. Hou]

Hi Shawn,

Thanks for your comments!

> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: 2017年7月13日 16:18
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> robh+dt@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> Subject: Re: [PATCH 1/3] dts: ls2088a: add pcie support
> 
> On Thu, Jul 06, 2017 at 04:55:28PM +0800, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > The physical memory map address and CCSR registers map address are
> > different between LS2088A and other LS2080A series SoCs.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > index 5c695c6..7d26531 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > @@ -134,6 +134,7 @@
> >  };
> >
> >  &pcie1 {
> > +	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
> 
> I do not see "fsl,ls2088a-pcie" in either bindings doc or kernel driver.
> 

I submitted the DT node patch and driver code patch separately, see the driver patch:
https://patchwork.kernel.org/patch/9827915/

Thanks,
Zhiqiang

Re: [PATCH 1/3] dts: ls2088a: add pcie support

[Shawn Guo]

On Thu, Jul 13, 2017 at 08:27:47AM +0000, Z.q. Hou wrote:
> Hi Shawn,
> 
> Thanks for your comments!
> 
> > -----Original Message-----
> > From: Shawn Guo [mailto:shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> > Sent: 2017年7月13日 16:18
> > To: Z.q. Hou <zhiqiang.hou-3arQi8VN3Tc@public.gmane.org>
> > Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org;
> > robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org; catalin.marinas-5wv7dgnIgG8@public.gmane.org;
> > will.deacon-5wv7dgnIgG8@public.gmane.org; Prabhakar Kushwaha <prabhakar.kushwaha-3arQi8VN3Tc@public.gmane.org>
> > Subject: Re: [PATCH 1/3] dts: ls2088a: add pcie support
> > 
> > On Thu, Jul 06, 2017 at 04:55:28PM +0800, Zhiqiang Hou wrote:
> > > From: Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org>
> > >
> > > The physical memory map address and CCSR registers map address are
> > > different between LS2088A and other LS2080A series SoCs.
> > >
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org>
> > > ---
> > >  arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++
> > >  1 file changed, 4 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > > b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > > index 5c695c6..7d26531 100644
> > > --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > > @@ -134,6 +134,7 @@
> > >  };
> > >
> > >  &pcie1 {
> > > +	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
> > 
> > I do not see "fsl,ls2088a-pcie" in either bindings doc or kernel driver.
> > 
> 
> I submitted the DT node patch and driver code patch separately, see the driver patch:
> https://patchwork.kernel.org/patch/9827915/

Send me the dts changes after bindings and driver patch land on
mainline.

Shawn
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RE: [PATCH 1/3] dts: ls2088a: add pcie support

[Z.q. Hou]

> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: 2017年7月13日 16:31
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: mark.rutland@arm.com; devicetree@vger.kernel.org;
> catalin.marinas@arm.com; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; will.deacon@arm.com;
> robh+dt@kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH 1/3] dts: ls2088a: add pcie support
> 
> On Thu, Jul 13, 2017 at 08:27:47AM +0000, Z.q. Hou wrote:
> > Hi Shawn,
> >
> > Thanks for your comments!
> >
> > > -----Original Message-----
> > > From: Shawn Guo [mailto:shawnguo@kernel.org]
> > > Sent: 2017年7月13日 16:18
> > > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > > Cc: linux-arm-kernel@lists.infradead.org;
> > > devicetree@vger.kernel.org;
> > > robh+dt@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> > > will.deacon@arm.com; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>
> > > Subject: Re: [PATCH 1/3] dts: ls2088a: add pcie support
> > >
> > > On Thu, Jul 06, 2017 at 04:55:28PM +0800, Zhiqiang Hou wrote:
> > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > >
> > > > The physical memory map address and CCSR registers map address are
> > > > different between LS2088A and other LS2080A series SoCs.
> > > >
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > ---
> > > >  arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++
> > > >  1 file changed, 4 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > > > b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > > > index 5c695c6..7d26531 100644
> > > > --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> > > > @@ -134,6 +134,7 @@
> > > >  };
> > > >
> > > >  &pcie1 {
> > > > +	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
> > >
> > > I do not see "fsl,ls2088a-pcie" in either bindings doc or kernel driver.
> > >
> >
> > I submitted the DT node patch and driver code patch separately, see the
> driver patch:
> > https://patchwork.kernel.org/patch/9827915/
> 
> Send me the dts changes after bindings and driver patch land on mainline.

Sure, thanks a lot!

- Zhiqiang