* [PATCH 1/4] arm64: dts: msm8996: Add device node for qcom qusb2 phy
2017-07-31 6:44 [PATCH 0/4] arm64: dt: msm8996: Enable support for qmp and qusb2 phy, and USB Vivek Gautam
@ 2017-07-31 6:44 ` Vivek Gautam
2017-07-31 6:44 ` [PATCH 2/4] arm64: dts: msm8996: Add device node for qcom qmp-phy for usb Vivek Gautam
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Vivek Gautam @ 2017-07-31 6:44 UTC (permalink / raw)
To: andy.gross, linux-arm-msm, devicetree
Cc: bjorn.andersson, robh+dt, mark.rutland, sboyd, linux-kernel,
linux-arm-kernel, Vivek Gautam
Adding device node for QUSB2 phy and the required infrastructure
to enable support for the same. This phy is used by dwc3 controller
present on msm8996.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 8 +++++
arch/arm64/boot/dts/qcom/msm8996.dtsi | 51 ++++++++++++++++++++++++++++
2 files changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 5366708ee78f..4476e9238150 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -88,6 +88,14 @@
cd-gpios = <&msmgpio 38 0x1>;
status = "okay";
};
+
+ phy@7411000 {
+ status = "okay";
+ };
+
+ phy@7412000 {
+ status = "okay";
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index d6a30fe81b77..019ec9345dbc 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -621,6 +621,57 @@
<960000000>,
<825000000>;
};
+
+ qfprom@74000 {
+ compatible = "qcom,qfprom";
+ reg = <0x74000 0x8ff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qusb2p_hstx_trim: hstx_trim@24e {
+ reg = <0x24e 0x2>;
+ bits = <5 4>;
+ };
+
+ qusb2s_hstx_trim: hstx_trim@24f {
+ reg = <0x24f 0x1>;
+ bits = <1 4>;
+ };
+ };
+
+ hsusb_phy1: phy@7411000 {
+ compatible = "qcom,msm8996-qusb2-phy";
+ reg = <0x7411000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_RX1_USB2_CLKREF_CLK>;
+ clock-names = "cfg_ahb", "ref";
+
+ vdda-pll-supply = <&pm8994_l12>;
+ vdda-phy-dpdm-supply = <&pm8994_l24>;
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ nvmem-cells = <&qusb2p_hstx_trim>;
+ status = "disabled";
+ };
+
+ hsusb_phy2: phy@7412000 {
+ compatible = "qcom,msm8996-qusb2-phy";
+ reg = <0x7412000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_RX2_USB2_CLKREF_CLK>;
+ clock-names = "cfg_ahb", "ref";
+
+ vdda-pll-supply = <&pm8994_l12>;
+ vdda-phy-dpdm-supply = <&pm8994_l24>;
+
+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+ nvmem-cells = <&qusb2s_hstx_trim>;
+ status = "disabled";
+ };
};
adsp-pil {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/4] arm64: dts: msm8996: Add device node for qcom qmp-phy for usb
2017-07-31 6:44 [PATCH 0/4] arm64: dt: msm8996: Enable support for qmp and qusb2 phy, and USB Vivek Gautam
2017-07-31 6:44 ` [PATCH 1/4] arm64: dts: msm8996: Add device node for qcom qusb2 phy Vivek Gautam
@ 2017-07-31 6:44 ` Vivek Gautam
2017-07-31 6:44 ` [PATCH 3/4] arm64: dts: msm8996: Add device node for qcom qmp-phy for pcie Vivek Gautam
2017-07-31 6:44 ` [PATCH 4/4] arm64: dts: msm8996: Add device node for qcom,dwc3 Vivek Gautam
3 siblings, 0 replies; 5+ messages in thread
From: Vivek Gautam @ 2017-07-31 6:44 UTC (permalink / raw)
To: andy.gross, linux-arm-msm, devicetree
Cc: bjorn.andersson, robh+dt, mark.rutland, sboyd, linux-kernel,
linux-arm-kernel, Vivek Gautam
Adding required device node for USB3 QMP phy present on
msm8996 chipset to enable support for the same. This phy
provides super speed usb functionality for dwc3 controller
on msm8996.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 4 ++++
arch/arm64/boot/dts/qcom/msm8996.dtsi | 33 ++++++++++++++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 4476e9238150..2bab37594b5d 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -89,6 +89,10 @@
status = "okay";
};
+ phy@7410000 {
+ status = "okay";
+ };
+
phy@7411000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 019ec9345dbc..c0cdbdf49410 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -639,6 +639,39 @@
};
};
+ phy@7410000 {
+ compatible = "qcom,msm8996-qmp-usb3-phy";
+ reg = <0x7410000 0x1c4>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_CLKREF_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ vdda-phy-supply = <&pm8994_l28>;
+ vdda-pll-supply = <&pm8994_l12>;
+
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy", "common";
+ status = "disabled";
+
+ ssusb_phy_0: lane@7410200 {
+ reg = <0x7410200 0x200>,
+ <0x7410400 0x130>,
+ <0x7410600 0x1a8>;
+ #phy-cells = <0>;
+
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ };
+ };
+
hsusb_phy1: phy@7411000 {
compatible = "qcom,msm8996-qusb2-phy";
reg = <0x7411000 0x180>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/4] arm64: dts: msm8996: Add device node for qcom qmp-phy for pcie
2017-07-31 6:44 [PATCH 0/4] arm64: dt: msm8996: Enable support for qmp and qusb2 phy, and USB Vivek Gautam
2017-07-31 6:44 ` [PATCH 1/4] arm64: dts: msm8996: Add device node for qcom qusb2 phy Vivek Gautam
2017-07-31 6:44 ` [PATCH 2/4] arm64: dts: msm8996: Add device node for qcom qmp-phy for usb Vivek Gautam
@ 2017-07-31 6:44 ` Vivek Gautam
2017-07-31 6:44 ` [PATCH 4/4] arm64: dts: msm8996: Add device node for qcom,dwc3 Vivek Gautam
3 siblings, 0 replies; 5+ messages in thread
From: Vivek Gautam @ 2017-07-31 6:44 UTC (permalink / raw)
To: andy.gross, linux-arm-msm, devicetree
Cc: bjorn.andersson, robh+dt, mark.rutland, sboyd, linux-kernel,
linux-arm-kernel, Vivek Gautam
Add required device node for QMP phy based 3-lane PCIe phy
present on msm8996 chipset to enable support for the same.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 4 ++
arch/arm64/boot/dts/qcom/msm8996.dtsi | 62 ++++++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 2bab37594b5d..a493f797f9f1 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -89,6 +89,10 @@
status = "okay";
};
+ phy@34000 {
+ status = "okay";
+ };
+
phy@7410000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index c0cdbdf49410..670af2b8d244 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -639,6 +639,68 @@
};
};
+ phy@34000 {
+ compatible = "qcom,msm8996-qmp-pcie-phy";
+ reg = <0x34000 0x488>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ vdda-phy-supply = <&pm8994_l28>;
+ vdda-pll-supply = <&pm8994_l12>;
+
+ resets = <&gcc GCC_PCIE_PHY_BCR>,
+ <&gcc GCC_PCIE_PHY_COM_BCR>,
+ <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
+ reset-names = "phy", "common", "cfg";
+ status = "disabled";
+
+ pciephy_0: lane@35000 {
+ reg = <0x035000 0x130>,
+ <0x035200 0x200>,
+ <0x035400 0x1dc>;
+ #phy-cells = <0>;
+
+ clock-output-names = "pcie_0_pipe_clk_src";
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "pipe0";
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "lane0";
+ };
+
+ pciephy_1: lane@36000 {
+ reg = <0x036000 0x130>,
+ <0x036200 0x200>,
+ <0x036400 0x1dc>;
+ #phy-cells = <0>;
+
+ clock-output-names = "pcie_1_pipe_clk_src";
+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "pipe1";
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "lane1";
+ };
+
+ pciephy_2: lane@37000 {
+ reg = <0x037000 0x130>,
+ <0x037200 0x200>,
+ <0x037400 0x1dc>;
+ #phy-cells = <0>;
+
+ clock-output-names = "pcie_2_pipe_clk_src";
+ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
+ clock-names = "pipe2";
+ resets = <&gcc GCC_PCIE_2_PHY_BCR>;
+ reset-names = "lane2";
+ };
+ };
+
phy@7410000 {
compatible = "qcom,msm8996-qmp-usb3-phy";
reg = <0x7410000 0x1c4>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 4/4] arm64: dts: msm8996: Add device node for qcom,dwc3
2017-07-31 6:44 [PATCH 0/4] arm64: dt: msm8996: Enable support for qmp and qusb2 phy, and USB Vivek Gautam
` (2 preceding siblings ...)
2017-07-31 6:44 ` [PATCH 3/4] arm64: dts: msm8996: Add device node for qcom qmp-phy for pcie Vivek Gautam
@ 2017-07-31 6:44 ` Vivek Gautam
3 siblings, 0 replies; 5+ messages in thread
From: Vivek Gautam @ 2017-07-31 6:44 UTC (permalink / raw)
To: andy.gross, linux-arm-msm, devicetree
Cc: bjorn.andersson, robh+dt, mark.rutland, sboyd, linux-kernel,
linux-arm-kernel, Vivek Gautam
Adding required device node for couple of DWC3 controllers
present on msm8996 chipset to enable High speed and Super
speed USB support.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
---
.../boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi | 24 +++++++++
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 34 +++++++++++++
arch/arm64/boot/dts/qcom/msm8996.dtsi | 57 ++++++++++++++++++++++
3 files changed, 115 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
index b1142c45fdc9..8e379782597a 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
@@ -24,4 +24,28 @@
power-source = <PM8994_GPIO_S4>; // 1.8V
};
};
+
+ usb3_vbus_det_gpio: pm8996_gpio22 {
+ pinconf {
+ pins = "gpio22";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ input-enable;
+ bias-pull-down;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ power-source = <PM8994_GPIO_S4>; // 1.8V
+ };
+ };
+};
+
+&pmi8994_gpios {
+ usb2_vbus_det_gpio: pmi8996_gpio6 {
+ pinconf {
+ pins = "gpio6";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ input-enable;
+ bias-pull-down;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ power-source = <PM8994_GPIO_S4>; // 1.8V
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index a493f797f9f1..271624f567be 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -13,6 +13,7 @@
#include "msm8996.dtsi"
#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
#include "apq8096-db820c-pins.dtsi"
#include "apq8096-db820c-pmic-pins.dtsi"
#include <dt-bindings/input/input.h>
@@ -104,6 +105,39 @@
phy@7412000 {
status = "okay";
};
+
+ usb@6a00000 {
+ status = "okay";
+
+ dwc3@6a00000 {
+ extcon = <&usb3_id>;
+ dr_mode = "otg";
+ };
+ };
+
+ usb3_id: usb3-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_vbus_det_gpio>;
+ };
+
+ usb@7600000 {
+ status = "okay";
+
+ dwc3@7600000 {
+ extcon = <&usb2_id>;
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+ };
+ };
+
+ usb2_id: usb2-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_vbus_det_gpio>;
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 670af2b8d244..bfe7b9723247 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -767,6 +767,63 @@
nvmem-cells = <&qusb2s_hstx_trim>;
status = "disabled";
};
+
+ usb2: usb@7600000 {
+ compatible = "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>,
+ <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB20_SLEEP_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+
+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <60000000>;
+
+ power-domains = <&gcc USB30_GDSC>;
+ status = "disabled";
+
+ dwc3@7600000 {
+ compatible = "snps,dwc3";
+ reg = <0x7600000 0xcc00>;
+ interrupts = <0 138 0>;
+ phys = <&hsusb_phy2>;
+ phy-names = "usb2-phy";
+ };
+ };
+
+ usb3: usb@6a00000 {
+ compatible = "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>,
+ <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
+ <&gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_SLEEP_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+
+ assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <120000000>;
+
+ power-domains = <&gcc USB30_GDSC>;
+ status = "disabled";
+
+ dwc3@6a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x6a00000 0xcc00>;
+ interrupts = <0 131 0>;
+ phys = <&hsusb_phy1>, <&ssusb_phy_0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
};
adsp-pil {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 5+ messages in thread