From: Abhishek Sahu <absahu@codeaurora.org>
To: boris.brezillon@free-electrons.com
Cc: dwmw2@infradead.org, computersforpeace@gmail.com,
marek.vasut@gmail.com, richard@nod.at,
cyrille.pitchen@wedev4u.fr, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org,
devicetree@vger.kernel.org, andy.gross@linaro.org,
architt@codeaurora.org, sricharan@codeaurora.org,
Abhishek Sahu <absahu@codeaurora.org>
Subject: [PATCH v4 14/20] mtd: nand: qcom: add command elements in BAM transaction
Date: Fri, 11 Aug 2017 17:09:29 +0530 [thread overview]
Message-ID: <1502451575-15712-15-git-send-email-absahu@codeaurora.org> (raw)
In-Reply-To: <1502451575-15712-1-git-send-email-absahu@codeaurora.org>
All the QPIC register read/write through BAM DMA requires
command descriptor which contains the array of command elements.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index c0c140b..d17c466 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -22,6 +22,7 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/delay.h>
+#include <linux/dma/qcom_bam_dma.h>
/* NANDc reg offsets */
#define NAND_FLASH_CMD 0x00
@@ -196,6 +197,7 @@
/* Returns the actual register address for NAND_FLASH_DEV_* */
#define nandc_dev_addr(nandc, reg) ((nandc)->props->flash_dev_offset + (reg))
+#define QPIC_PER_CW_CMD_ELEMENTS 32
#define QPIC_PER_CW_CMD_SGL 32
#define QPIC_PER_CW_DATA_SGL 8
@@ -215,8 +217,13 @@
/*
* This data type corresponds to the BAM transaction which will be used for all
* NAND transfers.
+ * @bam_ce - the array of BAM command elements
* @cmd_sgl - sgl for NAND BAM command pipe
* @data_sgl - sgl for NAND BAM consumer/producer pipe
+ * @bam_ce_pos - the index in bam_ce which is available for next sgl
+ * @bam_ce_start - the index in bam_ce which marks the start position ce
+ * for current sgl. It will be used for size calculation
+ * for current sgl
* @cmd_sgl_pos - current index in command sgl.
* @cmd_sgl_start - start index in command sgl.
* @tx_sgl_pos - current index in data sgl for tx.
@@ -225,8 +232,11 @@
* @rx_sgl_start - start index in data sgl for rx.
*/
struct bam_transaction {
+ struct bam_cmd_element *bam_ce;
struct scatterlist *cmd_sgl;
struct scatterlist *data_sgl;
+ u32 bam_ce_pos;
+ u32 bam_ce_start;
u32 cmd_sgl_pos;
u32 cmd_sgl_start;
u32 tx_sgl_pos;
@@ -456,7 +466,8 @@ static void free_bam_transaction(struct qcom_nand_controller *nandc)
bam_txn_size =
sizeof(*bam_txn) + num_cw *
- ((sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
+ ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
+ (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
(sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
@@ -466,6 +477,10 @@ static void free_bam_transaction(struct qcom_nand_controller *nandc)
bam_txn = bam_txn_buf;
bam_txn_buf += sizeof(*bam_txn);
+ bam_txn->bam_ce = bam_txn_buf;
+ bam_txn_buf +=
+ sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
+
bam_txn->cmd_sgl = bam_txn_buf;
bam_txn_buf +=
sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
@@ -483,6 +498,8 @@ static void clear_bam_transaction(struct qcom_nand_controller *nandc)
if (!nandc->props->is_bam)
return;
+ bam_txn->bam_ce_pos = 0;
+ bam_txn->bam_ce_start = 0;
bam_txn->cmd_sgl_pos = 0;
bam_txn->cmd_sgl_start = 0;
bam_txn->tx_sgl_pos = 0;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2017-08-11 11:39 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-11 11:39 [PATCH v4 00/20] Add QCOM QPIC NAND support Abhishek Sahu
2017-08-11 11:39 ` [PATCH v4 01/20] mtd: nand: qcom: fix read failure without complete bootchain Abhishek Sahu
2017-08-11 11:39 ` [PATCH v4 02/20] mtd: nand: qcom: support for NAND controller properties Abhishek Sahu
2017-08-11 11:39 ` [PATCH v4 03/20] mtd: nand: qcom: add bam property for QPIC NAND controller Abhishek Sahu
2017-08-11 11:39 ` [PATCH v4 04/20] mtd: nand: qcom: add and initialize QPIC DMA resources Abhishek Sahu
2017-08-11 11:39 ` [PATCH v4 05/20] mtd: nand: qcom: DMA mapping support for register read buffer Abhishek Sahu
2017-08-16 3:35 ` Archit Taneja
2017-08-11 11:39 ` [PATCH v4 06/20] mtd: nand: qcom: allocate BAM transaction Abhishek Sahu
2017-08-16 3:40 ` Archit Taneja
2017-08-11 11:39 ` [PATCH v4 07/20] mtd: nand: qcom: add BAM DMA descriptor handling Abhishek Sahu
2017-08-11 11:39 ` [PATCH v4 08/20] mtd: nand: qcom: support for passing flags in transfer functions Abhishek Sahu
[not found] ` <1502451575-15712-9-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-08-16 4:18 ` Archit Taneja
2017-08-16 7:23 ` Abhishek Sahu
2017-08-11 11:39 ` [PATCH v4 09/20] mtd: nand: qcom: support for read location registers Abhishek Sahu
[not found] ` <1502451575-15712-10-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-08-16 4:34 ` Archit Taneja
2017-08-16 7:34 ` Abhishek Sahu
2017-08-11 11:39 ` [PATCH v4 10/20] mtd: nand: qcom: erased codeword detection configuration Abhishek Sahu
[not found] ` <1502451575-15712-11-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-08-16 4:44 ` Archit Taneja
2017-08-11 11:39 ` [PATCH v4 11/20] mtd: nand: qcom: enable BAM or ADM mode Abhishek Sahu
2017-08-16 4:50 ` Archit Taneja
[not found] ` <db662967-2f73-bcfe-aef1-8b9cc860c743-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-08-16 8:49 ` Abhishek Sahu
2017-08-11 11:39 ` [PATCH v4 12/20] mtd: nand: qcom: QPIC data descriptors handling Abhishek Sahu
2017-08-16 5:41 ` Archit Taneja
2017-08-11 11:39 ` [PATCH v4 13/20] mtd: nand: qcom: support for different DEV_CMD register offsets Abhishek Sahu
2017-08-16 5:52 ` Archit Taneja
[not found] ` <d419a60c-3a00-36c2-6c6d-6f9edb396d53-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-08-16 8:57 ` Abhishek Sahu
2017-08-11 11:39 ` Abhishek Sahu [this message]
2017-08-16 5:53 ` [PATCH v4 14/20] mtd: nand: qcom: add command elements in BAM transaction Archit Taneja
2017-08-11 11:39 ` [PATCH v4 15/20] mtd: nand: qcom: support for command descriptor formation Abhishek Sahu
2017-08-16 6:00 ` Archit Taneja
2017-08-11 11:39 ` [PATCH v4 16/20] dt-bindings: qcom_nandc: fix the ipq806x device tree example Abhishek Sahu
2017-08-11 11:39 ` [PATCH v4 17/20] dt-bindings: qcom_nandc: IPQ4019 QPIC NAND documentation Abhishek Sahu
2017-08-11 11:39 ` [PATCH v4 18/20] dt-bindings: qcom_nandc: IPQ8074 " Abhishek Sahu
2017-08-11 11:39 ` [PATCH v4 19/20] mtd: nand: qcom: support for IPQ4019 QPIC NAND controller Abhishek Sahu
[not found] ` <1502451575-15712-20-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-08-16 6:02 ` Archit Taneja
2017-08-11 11:39 ` [PATCH v4 20/20] mtd: nand: qcom: support for IPQ8074 " Abhishek Sahu
2017-08-16 6:02 ` Archit Taneja
[not found] ` <1502451575-15712-1-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-08-13 7:47 ` [PATCH v4 00/20] Add QCOM QPIC NAND support Boris Brezillon
2017-08-14 12:28 ` Abhishek Sahu
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