* [PATCH v2 1/8] dt-bindings: mediatek: Add binding for mt2712 IOMMU and SMI
[not found] ` <1503313221-26453-1-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
@ 2017-08-21 11:00 ` Yong Wu
[not found] ` <1503313221-26453-2-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-08-21 11:00 ` [PATCH v2 2/8] iommu/mediatek: Move MTK_M4U_TO_LARB/PORT into mtk_iommu.c Yong Wu
` (5 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Yong Wu @ 2017-08-21 11:00 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: k.zhang-NuS5LvNUpcJWk0Htik3J/w, devicetree-u79uwXL29TY76Z2rM5mHXA,
arnd-r2nGTMty4D4, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
Catalin Marinas, Will Deacon, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Tomasz Figa, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
Daniel Kurtz, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
cloud.zhou-NuS5LvNUpcJWk0Htik3J/w
This patch adds decriptions for mt2712 IOMMU and SMI.
In order to balance the bandwidth, mt2712 has two M4Us, two
smi-commons, 10 smi-larbs. and mt2712 is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt2712 M4U-SMI HW diagram is as below:
EMI
|
------------------------------------
| |
M4U0 M4U1
| |
smi-common0 smi-common1
| |
------------------------- --------------------------------
| | | | | | | | | |
| | | | | | | | | |
larb0 larb1 larb2 larb3 larb6 larb4 larb5 larb7 larb8 larb9
disp0 vdec cam venc jpg mdp1/disp1 mdp2/disp2 mdp3 vdo/nr tvd
All the connections are HW fixed, SW can NOT adjust it.
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
Hi Rob,
Comparing with the v1, I add larb8 and larb9 in this version.
So I don't add your ACK here.
---
.../devicetree/bindings/iommu/mediatek,iommu.txt | 6 +-
.../memory-controllers/mediatek,smi-common.txt | 6 +-
.../memory-controllers/mediatek,smi-larb.txt | 5 +-
include/dt-bindings/memory/mt2712-larb-port.h | 102 +++++++++++++++++++++
4 files changed, 113 insertions(+), 6 deletions(-)
create mode 100644 include/dt-bindings/memory/mt2712-larb-port.h
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
index 53c20ca..df5db73 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
@@ -40,6 +40,7 @@ video decode local arbiter, all these ports are according to the video HW.
Required properties:
- compatible : must be one of the following string:
"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
+ "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
- reg : m4u register base and size.
- interrupts : the interrupt of m4u.
@@ -50,8 +51,9 @@ Required properties:
according to the local arbiter index, like larb0, larb1, larb2...
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
Specifies the mtk_m4u_id as defined in
- dt-binding/memory/mt2701-larb-port.h for mt2701 and
- dt-binding/memory/mt8173-larb-port.h for mt8173
+ dt-binding/memory/mt2701-larb-port.h for mt2701,
+ dt-binding/memory/mt2712-larb-port.h for mt2712, and
+ dt-binding/memory/mt8173-larb-port.h for mt8173.
Example:
iommu: iommu@10205000 {
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
index aa614b2..615abdd 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -2,8 +2,9 @@ SMI (Smart Multimedia Interface) Common
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
-Mediatek SMI have two generations of HW architecture, mt8173 uses the second
-generation of SMI HW while mt2701 uses the first generation HW of SMI.
+Mediatek SMI have two generations of HW architecture, mt2712 and mt8173 use
+the second generation of SMI HW while mt2701 uses the first generation HW of
+SMI.
There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But
@@ -15,6 +16,7 @@ not needed for SMI generation 2.
Required properties:
- compatible : must be one of :
"mediatek,mt2701-smi-common"
+ "mediatek,mt2712-smi-common"
"mediatek,mt8173-smi-common"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
index ddf46b8..083155c 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
@@ -4,8 +4,9 @@ The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
Required properties:
- compatible : must be one of :
- "mediatek,mt8173-smi-larb"
"mediatek,mt2701-smi-larb"
+ "mediatek,mt2712-smi-larb"
+ "mediatek,mt8173-smi-larb"
- reg : the register and size of this local arbiter.
- mediatek,smi : a phandle to the smi_common node.
- power-domains : a phandle to the power domain of this local arbiter.
@@ -15,7 +16,7 @@ Required properties:
the register.
- "smi" : It's the clock for transfer data and command.
-Required property for mt2701:
+Required property for mt2701 and mt2712:
- mediatek,larb-id :the hardware id of this larb.
Example:
diff --git a/include/dt-bindings/memory/mt2712-larb-port.h b/include/dt-bindings/memory/mt2712-larb-port.h
new file mode 100644
index 0000000..6b3a9e3
--- /dev/null
+++ b/include/dt-bindings/memory/mt2712-larb-port.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DTS_IOMMU_PORT_MT2712_H
+#define __DTS_IOMMU_PORT_MT2712_H
+
+#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+
+#define M4U_LARB0_ID 0
+#define M4U_LARB1_ID 1
+#define M4U_LARB2_ID 2
+#define M4U_LARB3_ID 3
+#define M4U_LARB4_ID 4
+#define M4U_LARB5_ID 5
+#define M4U_LARB6_ID 6
+#define M4U_LARB7_ID 7
+#define M4U_LARB8_ID 8
+#define M4U_LARB9_ID 9
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6)
+
+/* larb1 */
+#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8)
+#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9)
+#define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10)
+
+/* larb2 */
+#define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2)
+
+/* larb3 */
+#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4)
+#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5)
+#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6)
+#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7)
+#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8)
+
+/* larb4 */
+#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0)
+#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1)
+#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2)
+#define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3)
+#define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4)
+#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5)
+#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6)
+
+/* larb5 */
+#define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0)
+#define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1)
+#define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2)
+#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3)
+
+/* larb6 */
+#define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0)
+#define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1)
+#define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2)
+#define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3)
+
+/* larb7 */
+#define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0)
+#define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1)
+
+/* larb8 */
+#define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0)
+#define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1)
+#define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2)
+
+/* larb9 */
+#define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0)
+#define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1)
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 2/8] iommu/mediatek: Move MTK_M4U_TO_LARB/PORT into mtk_iommu.c
[not found] ` <1503313221-26453-1-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-08-21 11:00 ` [PATCH v2 1/8] dt-bindings: mediatek: Add binding for mt2712 IOMMU and SMI Yong Wu
@ 2017-08-21 11:00 ` Yong Wu
2017-08-21 11:00 ` [PATCH v2 4/8] iommu/mediatek: Merge 2 M4U HWs into one iommu domain Yong Wu
` (4 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Yong Wu @ 2017-08-21 11:00 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: k.zhang-NuS5LvNUpcJWk0Htik3J/w, devicetree-u79uwXL29TY76Z2rM5mHXA,
arnd-r2nGTMty4D4, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
Catalin Marinas, Will Deacon, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Tomasz Figa, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
Daniel Kurtz, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
cloud.zhou-NuS5LvNUpcJWk0Htik3J/w
The definition of MTK_M4U_TO_LARB and MTK_M4U_TO_PORT are shared by
all the gen2 M4U HWs. Thus, Move them out from mt8173-larb-port.h,
and put them into the c file.
Suggested-by: Honghui Zhang <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
This patch only moves the position of the MACRO MTK_M4U_TO_LARB/PORT.
---
drivers/iommu/mtk_iommu.c | 8 +++++++-
include/dt-bindings/memory/mt8173-larb-port.h | 4 ----
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 91c6d36..4db6c8f 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -31,7 +31,6 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <asm/barrier.h>
-#include <dt-bindings/memory/mt8173-larb-port.h>
#include <soc/mediatek/smi.h>
#include "mtk_iommu.h"
@@ -93,6 +92,13 @@
#define MTK_PROTECT_PA_ALIGN 128
+/*
+ * Get the local arbiter ID and the portid within the larb arbiter
+ * from mtk_m4u_id which is defined by MTK_M4U_ID.
+ */
+#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x7)
+#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
+
struct mtk_iommu_domain {
spinlock_t pgtlock; /* lock for page table */
diff --git a/include/dt-bindings/memory/mt8173-larb-port.h b/include/dt-bindings/memory/mt8173-larb-port.h
index 5fef5d1..111b4b0 100644
--- a/include/dt-bindings/memory/mt8173-larb-port.h
+++ b/include/dt-bindings/memory/mt8173-larb-port.h
@@ -15,10 +15,6 @@
#define __DTS_IOMMU_PORT_MT8173_H
#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
-/* Local arbiter ID */
-#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x7)
-/* PortID within the local arbiter */
-#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
#define M4U_LARB0_ID 0
#define M4U_LARB1_ID 1
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 4/8] iommu/mediatek: Merge 2 M4U HWs into one iommu domain
[not found] ` <1503313221-26453-1-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-08-21 11:00 ` [PATCH v2 1/8] dt-bindings: mediatek: Add binding for mt2712 IOMMU and SMI Yong Wu
2017-08-21 11:00 ` [PATCH v2 2/8] iommu/mediatek: Move MTK_M4U_TO_LARB/PORT into mtk_iommu.c Yong Wu
@ 2017-08-21 11:00 ` Yong Wu
2017-08-21 11:00 ` [PATCH v2 5/8] iommu/mediatek: Move pgtable allocation into domain_alloc Yong Wu
` (3 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Yong Wu @ 2017-08-21 11:00 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: k.zhang-NuS5LvNUpcJWk0Htik3J/w, devicetree-u79uwXL29TY76Z2rM5mHXA,
arnd-r2nGTMty4D4, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
Catalin Marinas, Will Deacon, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Tomasz Figa, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
Daniel Kurtz, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
cloud.zhou-NuS5LvNUpcJWk0Htik3J/w
In theory, If there are 2 M4U HWs, there should be 2 IOMMU domains.
But one IOMMU domain(4GB iova range) is enough for us currently,
It's unnecessary to maintain 2 pagetables.
Besides, This patch can simplify our consumer code largely. They don't
need map a iova range from one domain into another, They can share the
iova address easily.
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/iommu/mtk_iommu.c | 92 ++++++++++++++++++++++++++++++++++-------------
drivers/iommu/mtk_iommu.h | 2 ++
2 files changed, 70 insertions(+), 24 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index df23e02..1503dfa 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -114,6 +114,27 @@ struct mtk_iommu_domain {
static struct iommu_ops mtk_iommu_ops;
+static LIST_HEAD(m4ulist); /* List all the M4U HWs */
+
+#define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list)
+
+/*
+ * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
+ * for the performance.
+ *
+ * Here always return the mtk_iommu_data of the first probed M4U where the
+ * iommu domain information is recorded.
+ */
+static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void)
+{
+ struct mtk_iommu_data *data;
+
+ for_each_m4u(data)
+ return data;
+
+ return NULL;
+}
+
static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
{
return container_of(dom, struct mtk_iommu_domain, domain);
@@ -123,9 +144,12 @@ static void mtk_iommu_tlb_flush_all(void *cookie)
{
struct mtk_iommu_data *data = cookie;
- writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, data->base + REG_MMU_INV_SEL);
- writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
- wmb(); /* Make sure the tlb flush all done */
+ for_each_m4u(data) {
+ writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
+ data->base + REG_MMU_INV_SEL);
+ writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
+ wmb(); /* Make sure the tlb flush all done */
+ }
}
static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size,
@@ -134,12 +158,17 @@ static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size,
{
struct mtk_iommu_data *data = cookie;
- writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, data->base + REG_MMU_INV_SEL);
+ for_each_m4u(data) {
+ writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
+ data->base + REG_MMU_INV_SEL);
- writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
- writel_relaxed(iova + size - 1, data->base + REG_MMU_INVLD_END_A);
- writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
- data->tlb_flush_active = true;
+ writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
+ writel_relaxed(iova + size - 1,
+ data->base + REG_MMU_INVLD_END_A);
+ writel_relaxed(F_MMU_INV_RANGE,
+ data->base + REG_MMU_INVALIDATE);
+ data->tlb_flush_active = true;
+ }
}
static void mtk_iommu_tlb_sync(void *cookie)
@@ -148,20 +177,22 @@ static void mtk_iommu_tlb_sync(void *cookie)
int ret;
u32 tmp;
- /* Avoid timing out if there's nothing to wait for */
- if (!data->tlb_flush_active)
- return;
+ for_each_m4u(data) {
+ /* Avoid timing out if there's nothing to wait for */
+ if (!data->tlb_flush_active)
+ return;
- ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, tmp,
- tmp != 0, 10, 100000);
- if (ret) {
- dev_warn(data->dev,
- "Partial TLB flush timed out, falling back to full flush\n");
- mtk_iommu_tlb_flush_all(cookie);
+ ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
+ tmp, tmp != 0, 10, 100000);
+ if (ret) {
+ dev_warn(data->dev,
+ "Partial TLB flush timed out, falling back to full flush\n");
+ mtk_iommu_tlb_flush_all(cookie);
+ }
+ /* Clear the CPE status */
+ writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
+ data->tlb_flush_active = false;
}
- /* Clear the CPE status */
- writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
- data->tlb_flush_active = false;
}
static const struct iommu_gather_ops mtk_iommu_gather_ops = {
@@ -298,10 +329,11 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
struct device *dev)
{
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
- struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
+ struct mtk_iommu_data *curdata = dev->iommu_fwspec->iommu_priv;
+ struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
int ret;
- if (!data)
+ if (!data || !curdata)
return -ENODEV;
if (!data->m4u_dom) {
@@ -313,7 +345,17 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
}
}
- mtk_iommu_config(data, dev, true);
+ /*
+ * Update the pgtable base address register of another M4U HW with the
+ * existed pgtable if there are more than one M4U HW.
+ */
+ if (!curdata->m4u_dom) {
+ curdata->m4u_dom = data->m4u_dom;
+ writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
+ curdata->base + REG_MMU_PT_BASE_ADDR);
+ }
+
+ mtk_iommu_config(curdata, dev, true);
return 0;
}
@@ -405,7 +447,7 @@ static void mtk_iommu_remove_device(struct device *dev)
static struct iommu_group *mtk_iommu_device_group(struct device *dev)
{
- struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
+ struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
if (!data)
return ERR_PTR(-ENODEV);
@@ -604,6 +646,8 @@ static int mtk_iommu_probe(struct platform_device *pdev)
if (ret)
return ret;
+ list_add_tail(&data->list, &m4ulist);
+
if (!iommu_present(&platform_bus_type))
bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 462e593..b4451a1 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -57,6 +57,8 @@ struct mtk_iommu_data {
struct iommu_device iommu;
enum mtk_iommu_plat m4u_plat;
+
+ struct list_head list;
};
static inline int compare_of(struct device *dev, void *data)
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 5/8] iommu/mediatek: Move pgtable allocation into domain_alloc
[not found] ` <1503313221-26453-1-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
` (2 preceding siblings ...)
2017-08-21 11:00 ` [PATCH v2 4/8] iommu/mediatek: Merge 2 M4U HWs into one iommu domain Yong Wu
@ 2017-08-21 11:00 ` Yong Wu
2017-08-21 11:00 ` [PATCH v2 6/8] iommu/mediatek: Disable iommu clock when system suspend Yong Wu
` (2 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Yong Wu @ 2017-08-21 11:00 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: k.zhang-NuS5LvNUpcJWk0Htik3J/w, devicetree-u79uwXL29TY76Z2rM5mHXA,
arnd-r2nGTMty4D4, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
Catalin Marinas, Will Deacon, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Tomasz Figa, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
Daniel Kurtz, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
cloud.zhou-NuS5LvNUpcJWk0Htik3J/w
After adding the global list for M4U HW, We get a chance to
move the pagetable allocation into the mtk_iommu_domain_alloc.
Let the domain_alloc do the right thing.
This patch is for fixing this problem[1].
[1]: https://patchwork.codeaurora.org/patch/53987/
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/iommu/mtk_iommu.c | 52 ++++++++++++++++++++---------------------------
1 file changed, 22 insertions(+), 30 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 1503dfa..a82196c 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -262,9 +262,9 @@ static void mtk_iommu_config(struct mtk_iommu_data *data,
}
}
-static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
+static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom)
{
- struct mtk_iommu_domain *dom = data->m4u_dom;
+ struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
spin_lock_init(&dom->pgtlock);
@@ -290,9 +290,6 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
/* Update our support page sizes bitmap */
dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
-
- writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
- data->base + REG_MMU_PT_BASE_ADDR);
return 0;
}
@@ -307,20 +304,30 @@ static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
if (!dom)
return NULL;
- if (iommu_get_dma_cookie(&dom->domain)) {
- kfree(dom);
- return NULL;
- }
+ if (iommu_get_dma_cookie(&dom->domain))
+ goto free_dom;
+
+ if (mtk_iommu_domain_finalise(dom))
+ goto put_dma_cookie;
dom->domain.geometry.aperture_start = 0;
dom->domain.geometry.aperture_end = DMA_BIT_MASK(32);
dom->domain.geometry.force_aperture = true;
return &dom->domain;
+
+put_dma_cookie:
+ iommu_put_dma_cookie(&dom->domain);
+free_dom:
+ kfree(dom);
+ return NULL;
}
static void mtk_iommu_domain_free(struct iommu_domain *domain)
{
+ struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+
+ free_io_pgtable_ops(dom->iop);
iommu_put_dma_cookie(domain);
kfree(to_mtk_domain(domain));
}
@@ -329,33 +336,19 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
struct device *dev)
{
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
- struct mtk_iommu_data *curdata = dev->iommu_fwspec->iommu_priv;
- struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
- int ret;
+ struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv;
- if (!data || !curdata)
+ if (!data)
return -ENODEV;
+ /* Update the pgtable base address register of the M4U HW */
if (!data->m4u_dom) {
data->m4u_dom = dom;
- ret = mtk_iommu_domain_finalise(data);
- if (ret) {
- data->m4u_dom = NULL;
- return ret;
- }
- }
-
- /*
- * Update the pgtable base address register of another M4U HW with the
- * existed pgtable if there are more than one M4U HW.
- */
- if (!curdata->m4u_dom) {
- curdata->m4u_dom = data->m4u_dom;
- writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
- curdata->base + REG_MMU_PT_BASE_ADDR);
+ writel(dom->cfg.arm_v7s_cfg.ttbr[0],
+ data->base + REG_MMU_PT_BASE_ADDR);
}
- mtk_iommu_config(curdata, dev, true);
+ mtk_iommu_config(data, dev, true);
return 0;
}
@@ -664,7 +657,6 @@ static int mtk_iommu_remove(struct platform_device *pdev)
if (iommu_present(&platform_bus_type))
bus_set_iommu(&platform_bus_type, NULL);
- free_io_pgtable_ops(data->m4u_dom->iop);
clk_disable_unprepare(data->bclk);
devm_free_irq(&pdev->dev, data->irq, data);
component_master_del(&pdev->dev, &mtk_iommu_com_ops);
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 6/8] iommu/mediatek: Disable iommu clock when system suspend
[not found] ` <1503313221-26453-1-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
` (3 preceding siblings ...)
2017-08-21 11:00 ` [PATCH v2 5/8] iommu/mediatek: Move pgtable allocation into domain_alloc Yong Wu
@ 2017-08-21 11:00 ` Yong Wu
2017-08-21 11:00 ` [PATCH v2 7/8] iommu/mediatek: Enlarge the validate PA range for 4GB mode Yong Wu
2017-08-21 11:00 ` [PATCH v2 8/8] memory: mtk-smi: Degrade SMI init to module_init Yong Wu
6 siblings, 0 replies; 15+ messages in thread
From: Yong Wu @ 2017-08-21 11:00 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: k.zhang-NuS5LvNUpcJWk0Htik3J/w, devicetree-u79uwXL29TY76Z2rM5mHXA,
arnd-r2nGTMty4D4, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
Catalin Marinas, Will Deacon, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Tomasz Figa, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
Daniel Kurtz, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
cloud.zhou-NuS5LvNUpcJWk0Htik3J/w
When system suspend, infra power domain may be off, and the iommu's
clock must be disabled when system off, or the iommu's bclk clock maybe
disabled after system resume.
Signed-off-by: Honghui Zhang <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/iommu/mtk_iommu.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index a82196c..e21de86 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -675,6 +675,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device *dev)
reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
+ clk_disable_unprepare(data->bclk);
return 0;
}
@@ -683,7 +684,13 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
struct mtk_iommu_data *data = dev_get_drvdata(dev);
struct mtk_iommu_suspend_reg *reg = &data->reg;
void __iomem *base = data->base;
+ int ret;
+ ret = clk_prepare_enable(data->bclk);
+ if (ret) {
+ dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
+ return ret;
+ }
writel_relaxed(reg->standard_axi_mode,
base + REG_MMU_STANDARD_AXI_MODE);
writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
@@ -699,7 +706,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
}
static const struct dev_pm_ops mtk_iommu_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
};
static const struct of_device_id mtk_iommu_of_ids[] = {
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 7/8] iommu/mediatek: Enlarge the validate PA range for 4GB mode
[not found] ` <1503313221-26453-1-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
` (4 preceding siblings ...)
2017-08-21 11:00 ` [PATCH v2 6/8] iommu/mediatek: Disable iommu clock when system suspend Yong Wu
@ 2017-08-21 11:00 ` Yong Wu
[not found] ` <1503313221-26453-8-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-08-24 6:15 ` kbuild test robot
2017-08-21 11:00 ` [PATCH v2 8/8] memory: mtk-smi: Degrade SMI init to module_init Yong Wu
6 siblings, 2 replies; 15+ messages in thread
From: Yong Wu @ 2017-08-21 11:00 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: k.zhang-NuS5LvNUpcJWk0Htik3J/w, devicetree-u79uwXL29TY76Z2rM5mHXA,
arnd-r2nGTMty4D4, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
Catalin Marinas, Will Deacon, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Tomasz Figa, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
Daniel Kurtz, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
cloud.zhou-NuS5LvNUpcJWk0Htik3J/w
This patch is for 4GB mode, mainly for 4 issues:
1) Fix a 4GB bug:
if the dram base is 0x4000_0000, the dram size is 0xc000_0000.
then the code just meet a corner case because max_pfn is
0x10_0000.
data->enable_4GB = !!(max_pfn > (0xffffffffUL >> PAGE_SHIFT));
It's true at the case above. That is unexpected.
2) In mt2712, there is a new register for the 4GB PA range(0x118)
we should enlarge the max PA range, or the HW will report
error.
The dram range is from 0x1_0000_0000 to 0x1_ffff_ffff in the 4GB
mode, we cut out the bit[32:30] of the SA(Start address) and
EA(End address) into this REG_MMU_VLD_PA_RNG(0x118).
3) In mt2712, the register(0x13c) is extended for 4GB mode.
bit[7:6] indicate the valid PA[32:33]. Thus, we don't mask the
value and print it directly for debug.
4) if 4GB is enabled, the dram PA range is from 0x1_0000_0000 to
0x1_ffff_ffff. Thus, the PA from iova_to_pa should also '|' BIT(32)
Signed-off-by: Honghui Zhang <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/iommu/mtk_iommu.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index e21de86..4f233e1 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -61,6 +61,8 @@
#define REG_MMU_IVRP_PADDR 0x114
#define F_MMU_IVRP_PA_SET(pa, ext) (((pa) >> 1) | ((!!(ext)) << 31))
+#define REG_MMU_VLD_PA_RNG 0x118
+#define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA))
#define REG_MMU_INT_CONTROL0 0x120
#define F_L2_MULIT_HIT_EN BIT(0)
@@ -85,7 +87,6 @@
#define REG_MMU_FAULT_ST1 0x134
#define REG_MMU_FAULT_VA 0x13c
-#define F_MMU_FAULT_VA_MSK 0xfffff000
#define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
#define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
@@ -214,7 +215,6 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
- fault_iova &= F_MMU_FAULT_VA_MSK;
fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
regval = readl_relaxed(data->base + REG_MMU_INT_ID);
fault_larb = F_MMU0_INT_ID_LARB_ID(regval);
@@ -395,6 +395,7 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
dma_addr_t iova)
{
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
+ struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
unsigned long flags;
phys_addr_t pa;
@@ -402,6 +403,9 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
pa = dom->iop->iova_to_phys(dom->iop, iova);
spin_unlock_irqrestore(&dom->pgtlock, flags);
+ if (data->enable_4GB)
+ pa |= BIT(32);
+
return pa;
}
@@ -529,6 +533,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
data->base + REG_MMU_IVRP_PADDR);
+ if (data->enable_4GB && data->m4u_type != M4U_MT8173) {
+ /*
+ * If 4GB mode is enabled, the validate PA range is from
+ * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
+ */
+ regval = F_MMU_VLD_PA_RNG(7, 4);
+ writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG);
+ }
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
/* It's MISC control register whose default value is ok except mt8173.*/
@@ -574,7 +586,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
/* Whether the current dram is over 4GB */
- data->enable_4GB = !!(max_pfn > (0xffffffffUL >> PAGE_SHIFT));
+ data->enable_4GB = !!(max_pfn > (BIT(32) >> PAGE_SHIFT));
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
data->base = devm_ioremap_resource(dev, res);
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread[parent not found: <1503313221-26453-8-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH v2 7/8] iommu/mediatek: Enlarge the validate PA range for 4GB mode
[not found] ` <1503313221-26453-8-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
@ 2017-08-23 17:55 ` kbuild test robot
0 siblings, 0 replies; 15+ messages in thread
From: kbuild test robot @ 2017-08-23 17:55 UTC (permalink / raw)
Cc: kbuild-all-JC7UmRfGjtg, Joerg Roedel, Rob Herring,
Matthias Brugger, Robin Murphy, Will Deacon, Daniel Kurtz,
Tomasz Figa, Catalin Marinas,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
arnd-r2nGTMty4D4, honghui.zhang-NuS5LvNUpcJWk0Htik3J/w,
k.zhang-NuS5LvNUpcJWk0Htik3J/w, cloud.zhou-NuS5LvNUpcJWk0Htik3J/w,
yong.wu-NuS5LvNUpcJWk0Htik3J/w
[-- Attachment #1: Type: text/plain, Size: 3556 bytes --]
Hi Yong,
[auto build test ERROR on iommu/next]
[also build test ERROR on next-20170823]
[cannot apply to v4.13-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Yong-Wu/MT2712-IOMMU-SUPPORT/20170824-074750
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
config: arm64-allmodconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All errors (new ones prefixed by >>):
drivers/iommu/mtk_iommu.c: In function 'mtk_iommu_hw_init':
>> drivers/iommu/mtk_iommu.c:536:30: error: 'const struct mtk_iommu_data' has no member named 'm4u_type'; did you mean 'm4u_dom'?
if (data->enable_4GB && data->m4u_type != M4U_MT8173) {
^~
vim +536 drivers/iommu/mtk_iommu.c
500
501 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
502 {
503 u32 regval;
504 int ret;
505
506 ret = clk_prepare_enable(data->bclk);
507 if (ret) {
508 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
509 return ret;
510 }
511
512 regval = F_MMU_TF_PROTECT_SEL(2, data);
513 if (data->m4u_plat == M4U_MT8173)
514 regval |= F_MMU_PREFETCH_RT_REPLACE_MOD;
515 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
516
517 regval = F_L2_MULIT_HIT_EN |
518 F_TABLE_WALK_FAULT_INT_EN |
519 F_PREETCH_FIFO_OVERFLOW_INT_EN |
520 F_MISS_FIFO_OVERFLOW_INT_EN |
521 F_PREFETCH_FIFO_ERR_INT_EN |
522 F_MISS_FIFO_ERR_INT_EN;
523 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
524
525 regval = F_INT_TRANSLATION_FAULT |
526 F_INT_MAIN_MULTI_HIT_FAULT |
527 F_INT_INVALID_PA_FAULT |
528 F_INT_ENTRY_REPLACEMENT_FAULT |
529 F_INT_TLB_MISS_FAULT |
530 F_INT_MISS_TRANSACTION_FIFO_FAULT |
531 F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
532 writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
533
534 writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
535 data->base + REG_MMU_IVRP_PADDR);
> 536 if (data->enable_4GB && data->m4u_type != M4U_MT8173) {
537 /*
538 * If 4GB mode is enabled, the validate PA range is from
539 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
540 */
541 regval = F_MMU_VLD_PA_RNG(7, 4);
542 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG);
543 }
544 writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
545
546 /* It's MISC control register whose default value is ok except mt8173.*/
547 if (data->m4u_plat == M4U_MT8173)
548 writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
549
550 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
551 dev_name(data->dev), (void *)data)) {
552 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
553 clk_disable_unprepare(data->bclk);
554 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
555 return -ENODEV;
556 }
557
558 return 0;
559 }
560
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 56235 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 7/8] iommu/mediatek: Enlarge the validate PA range for 4GB mode
2017-08-21 11:00 ` [PATCH v2 7/8] iommu/mediatek: Enlarge the validate PA range for 4GB mode Yong Wu
[not found] ` <1503313221-26453-8-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
@ 2017-08-24 6:15 ` kbuild test robot
1 sibling, 0 replies; 15+ messages in thread
From: kbuild test robot @ 2017-08-24 6:15 UTC (permalink / raw)
Cc: kbuild-all, Joerg Roedel, Rob Herring, Matthias Brugger,
Robin Murphy, Will Deacon, Daniel Kurtz, Tomasz Figa,
Catalin Marinas, linux-mediatek, srv_heupstream, devicetree,
linux-kernel, linux-arm-kernel, iommu, arnd, honghui.zhang,
k.zhang, cloud.zhou, yong.wu
[-- Attachment #1: Type: text/plain, Size: 3327 bytes --]
Hi Yong,
[auto build test WARNING on iommu/next]
[also build test WARNING on next-20170823]
[cannot apply to v4.13-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Yong-Wu/MT2712-IOMMU-SUPPORT/20170824-074750
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All warnings (new ones prefixed by >>):
In file included from include/linux/kernel.h:10:0,
from include/linux/list.h:8,
from include/linux/preempt.h:10,
from include/linux/spinlock.h:50,
from include/linux/mmzone.h:7,
from include/linux/bootmem.h:7,
from drivers/iommu/mtk_iommu.c:14:
drivers/iommu/mtk_iommu.c: In function 'mtk_iommu_iova_to_phys':
include/linux/bitops.h:6:24: warning: left shift count >= width of type [-Wshift-count-overflow]
#define BIT(nr) (1UL << (nr))
^
>> drivers/iommu/mtk_iommu.c:407:9: note: in expansion of macro 'BIT'
pa |= BIT(32);
^~~
drivers/iommu/mtk_iommu.c: In function 'mtk_iommu_hw_init':
drivers/iommu/mtk_iommu.c:536:30: error: 'const struct mtk_iommu_data' has no member named 'm4u_type'; did you mean 'm4u_dom'?
if (data->enable_4GB && data->m4u_type != M4U_MT8173) {
^~
In file included from include/linux/kernel.h:10:0,
from include/linux/list.h:8,
from include/linux/preempt.h:10,
from include/linux/spinlock.h:50,
from include/linux/mmzone.h:7,
from include/linux/bootmem.h:7,
from drivers/iommu/mtk_iommu.c:14:
drivers/iommu/mtk_iommu.c: In function 'mtk_iommu_probe':
include/linux/bitops.h:6:24: warning: left shift count >= width of type [-Wshift-count-overflow]
#define BIT(nr) (1UL << (nr))
^
drivers/iommu/mtk_iommu.c:589:35: note: in expansion of macro 'BIT'
data->enable_4GB = !!(max_pfn > (BIT(32) >> PAGE_SHIFT));
^~~
vim +/BIT +407 drivers/iommu/mtk_iommu.c
393
394 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
395 dma_addr_t iova)
396 {
397 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
398 struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
399 unsigned long flags;
400 phys_addr_t pa;
401
402 spin_lock_irqsave(&dom->pgtlock, flags);
403 pa = dom->iop->iova_to_phys(dom->iop, iova);
404 spin_unlock_irqrestore(&dom->pgtlock, flags);
405
406 if (data->enable_4GB)
> 407 pa |= BIT(32);
408
409 return pa;
410 }
411
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 62774 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 8/8] memory: mtk-smi: Degrade SMI init to module_init
[not found] ` <1503313221-26453-1-git-send-email-yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
` (5 preceding siblings ...)
2017-08-21 11:00 ` [PATCH v2 7/8] iommu/mediatek: Enlarge the validate PA range for 4GB mode Yong Wu
@ 2017-08-21 11:00 ` Yong Wu
6 siblings, 0 replies; 15+ messages in thread
From: Yong Wu @ 2017-08-21 11:00 UTC (permalink / raw)
To: Joerg Roedel, Rob Herring, Matthias Brugger, Robin Murphy
Cc: k.zhang-NuS5LvNUpcJWk0Htik3J/w, devicetree-u79uwXL29TY76Z2rM5mHXA,
arnd-r2nGTMty4D4, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
Catalin Marinas, Will Deacon, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Tomasz Figa, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA,
Daniel Kurtz, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
cloud.zhou-NuS5LvNUpcJWk0Htik3J/w
The initialization of MediaTek power manager(SCPSYS) is
builtin_platform_driver, and SMI must depend on power-domain.
Thus, currently subsys_initcall for SMI is unnecessary, SMI will be
always probe defered by power-domain. Degrade it to module_init.
In addition, there are two small changes about the probe sequence:
1) Delete this two lines.
if (!dev->pm_domain)
return -EPROBE_DEFER;
This is not helpful. the platform driver framework guarantee this.
The "dev_pm_domain_attach" in the "platform_drv_probe" will return
EPROBE_DEFER if its powerdomain is not ready.
2) Add the probe-defer for the smi-larb device should waiting for
smi-common.
In mt2712, there are 2 smi-commons, 10 smi-larbs. All will be
probe-defered by the power-domain, there is seldom case that
smi-larb probe done before smi-common. then it will hang like
this:
Unable to handle kernel NULL pointer dereference at virtual address
00000000 pgd = ffffff800a4e0000
[00000000] *pgd=00000000beffe003[ 17.610026] , *pud=00000000beffe003
...
[<ffffff800897fe04>] mtk_smi_enable+0x1c/0xd0
[<ffffff800897fee8>] mtk_smi_larb_get+0x30/0x98
[<ffffff80088edfa8>] mtk_mipicsi0_resume+0x38/0x1b8
[<ffffff8008634f44>] pm_generic_runtime_resume+0x3c/0x58
[<ffffff8008644ff8>] __genpd_runtime_resume+0x38/0x98
[<ffffff8008647434>] genpd_runtime_resume+0x164/0x220
[<ffffff80086372f8>] __rpm_callback+0x78/0xa0
[<ffffff8008637358>] rpm_callback+0x38/0xa0
[<ffffff8008638a4c>] rpm_resume+0x4a4/0x6f8
[<ffffff8008638d04>] __pm_runtime_resume+0x64/0xa0
[<ffffff80088ed05c>] mtk_mipicsi0_probe+0x40c/0xb70
[<ffffff800862cdc0>] platform_drv_probe+0x58/0xc0
[<ffffff800862a514>] driver_probe_device+0x284/0x438
[<ffffff800862a8ac>] __device_attach_driver+0xb4/0x160
[<ffffff8008627d58>] bus_for_each_drv+0x68/0xa8
[<ffffff800862a0a4>] __device_attach+0xd4/0x168
[<ffffff800862a9d4>] device_initial_probe+0x24/0x30
[<ffffff80086291d8>] bus_probe_device+0xa0/0xa8
[<ffffff8008629784>] deferred_probe_work_func+0x94/0xf0
[<ffffff80080f03a8>] process_one_work+0x1d8/0x6e0
Signed-off-by: Yong Wu <yong.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
drivers/memory/mtk-smi.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 8ffe321..8f2d152 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -16,6 +16,7 @@
#include <linux/device.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
@@ -288,9 +289,6 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
struct platform_device *smi_pdev;
int err;
- if (!dev->pm_domain)
- return -EPROBE_DEFER;
-
larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
if (!larb)
return -ENOMEM;
@@ -326,6 +324,8 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
smi_pdev = of_find_device_by_node(smi_node);
of_node_put(smi_node);
if (smi_pdev) {
+ if (!platform_get_drvdata(smi_pdev))
+ return -EPROBE_DEFER;
larb->smi_common_dev = &smi_pdev->dev;
} else {
dev_err(dev, "Failed to get the smi_common device\n");
@@ -377,9 +377,6 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
enum mtk_smi_gen smi_gen;
int ret;
- if (!dev->pm_domain)
- return -EPROBE_DEFER;
-
common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
if (!common)
return -ENOMEM;
@@ -456,4 +453,4 @@ static int __init mtk_smi_init(void)
return ret;
}
-subsys_initcall(mtk_smi_init);
+module_init(mtk_smi_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread