* [PATCH] arm64: tegra: Add SMMU node for Tegra186
@ 2017-09-13 23:01 Krishna Reddy
[not found] ` <1505343714-22359-1-git-send-email-vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
0 siblings, 1 reply; 2+ messages in thread
From: Krishna Reddy @ 2017-09-13 23:01 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, vdumpa-DDmLM1+adcrQT0dZR+AlfA,
josephl-DDmLM1+adcrQT0dZR+AlfA, acourbot-DDmLM1+adcrQT0dZR+AlfA,
mperttunen-DDmLM1+adcrQT0dZR+AlfA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Add the DT node for ARM SMMU on Tegra186.
Signed-off-by: Krishna Reddy <vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 73 ++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 0b0552c9f7dd..e2c3ad203c93 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -355,6 +355,79 @@
nvidia,bpmp = <&bpmp>;
};
+ smmu: iommu@12000000 {
+ compatible = "arm,mmu-500";
+ reg = <0 0x12000000 0 0x800000>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ stream-match-mask = <0x7F80>;
+ };
+
gpu@17000000 {
compatible = "nvidia,gp10b";
reg = <0x0 0x17000000 0x0 0x1000000>,
--
2.1.4
^ permalink raw reply related [flat|nested] 2+ messages in thread[parent not found: <1505343714-22359-1-git-send-email-vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH] arm64: tegra: Add SMMU node for Tegra186 [not found] ` <1505343714-22359-1-git-send-email-vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2017-09-20 12:46 ` Mikko Perttunen 0 siblings, 0 replies; 2+ messages in thread From: Mikko Perttunen @ 2017-09-20 12:46 UTC (permalink / raw) To: Krishna Reddy, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8, catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w, jonathanh-DDmLM1+adcrQT0dZR+AlfA, josephl-DDmLM1+adcrQT0dZR+AlfA, acourbot-DDmLM1+adcrQT0dZR+AlfA, mperttunen-DDmLM1+adcrQT0dZR+AlfA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA Reviewed-by: Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Tested-by: Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Tested to work with Host1x :) I noticed a slight difference with downstream where downstream has global interrupts 170 and 171 - but looks like the latter is for secure faults which we should never get so this way seems more correct. Thanks, Mikko On 14.09.2017 02:01, Krishna Reddy wrote: > Add the DT node for ARM SMMU on Tegra186. > > Signed-off-by: Krishna Reddy <vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > --- > arch/arm64/boot/dts/nvidia/tegra186.dtsi | 73 ++++++++++++++++++++++++++++++++ > 1 file changed, 73 insertions(+) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi > index 0b0552c9f7dd..e2c3ad203c93 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi > @@ -355,6 +355,79 @@ > nvidia,bpmp = <&bpmp>; > }; > > + smmu: iommu@12000000 { > + compatible = "arm,mmu-500"; > + reg = <0 0x12000000 0 0x800000>; > + #global-interrupts = <1>; > + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; > + #iommu-cells = <1>; > + stream-match-mask = <0x7F80>; > + }; > + > gpu@17000000 { > compatible = "nvidia,gp10b"; > reg = <0x0 0x17000000 0x0 0x1000000>, > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 2+ messages in thread
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2017-09-13 23:01 [PATCH] arm64: tegra: Add SMMU node for Tegra186 Krishna Reddy
[not found] ` <1505343714-22359-1-git-send-email-vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-09-20 12:46 ` Mikko Perttunen
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