Subject: PCI: brcmstb: Add Broadcom Settopbox PCIe support (V2)

Subject: PCI: brcmstb: Add Broadcom Settopbox PCIe support (V2)

[Jim Quinlan]

This patch series adds support for the Broadcom Settopbox PCIe host
controller.  It is targeted to Broadcom Settopbox chips running on
ARM, ARM64, and MIPS platforms.

Changes from V1:

* Patch brcmstb-add-memory-API:
  - fix DT_PROP_DATA_TO_U32 macro.
  - dropped one EXPORT_SYMBOL, changed the other to GPL.
* Patch DT-docs-for-Brcmstb-PCIe:
  - change 'brcm,gen' prop to standard 'max-link-speed'. 
  - rewrite bindings commit to omit standard prop defs.
  - change props "supplies", "supply-names" to "xyz-supply"
* Patch removed: export-symbol-arch_setup_dma_ops [4/9] 
* Patch brcmstb-add-dma-ranges:
  - use get_dma_ops(); also use a const dma_map_ops structure.
  - rewrite map_sg(), unmap_sg(), other calls like syng_sg_*()
  - omit brcm_mapping_error(), but added code in brcm_dma_supported()
  - put all of the notifier code in one compilation unit.

[PATCH 1/8] SOC: brcmstb: add memory API

[Jim Quinlan]

From: Florian Fainelli <f.fainelli@gmail.com>

This commit adds a memory API suitable for ascertaining the sizes of
each of the N memory controllers in a Broadcom STB chip.  Its first
user will be the Broadcom STB PCIe root complex driver, which needs
to know these sizes to properly set up DMA mappings for inbound
regions.

We cannot use memblock here or anything like what Linux provides
because it collapses adjacent regions within a larger block, and here
we actually need per-memory controller addresses and sizes, which is
why we resort to manual DT parsing.

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 drivers/soc/bcm/brcmstb/Makefile |   2 +-
 drivers/soc/bcm/brcmstb/memory.c | 172 +++++++++++++++++++++++++++++++++++++++
 include/soc/brcmstb/memory_api.h |  25 ++++++
 3 files changed, 198 insertions(+), 1 deletion(-)
 create mode 100644 drivers/soc/bcm/brcmstb/memory.c
 create mode 100644 include/soc/brcmstb/memory_api.h

diff --git a/drivers/soc/bcm/brcmstb/Makefile b/drivers/soc/bcm/brcmstb/Makefile
index 9120b27..4cea7b6 100644
--- a/drivers/soc/bcm/brcmstb/Makefile
+++ b/drivers/soc/bcm/brcmstb/Makefile
@@ -1 +1 @@
-obj-y				+= common.o biuctrl.o
+obj-y				+= common.o biuctrl.o memory.o
diff --git a/drivers/soc/bcm/brcmstb/memory.c b/drivers/soc/bcm/brcmstb/memory.c
new file mode 100644
index 0000000..eb647ad9
--- /dev/null
+++ b/drivers/soc/bcm/brcmstb/memory.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright © 2015-2017 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * A copy of the GPL is available at
+ * http://www.broadcom.com/licenses/GPLv2.php or from the Free Software
+ * Foundation at https://www.gnu.org/licenses/ .
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/libfdt.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/sizes.h>
+#include <soc/brcmstb/memory_api.h>
+
+/* Macro to help extract property data */
+#define DT_PROP_DATA_TO_U32(b, offs) (fdt32_to_cpu(*(u32*)(b + offs)))
+
+/* Constants used when retrieving memc info */
+#define NUM_BUS_RANGES 10
+#define BUS_RANGE_ULIMIT_SHIFT 4
+#define BUS_RANGE_LLIMIT_SHIFT 4
+#define BUS_RANGE_PA_SHIFT 12
+
+enum {
+	BUSNUM_MCP0 = 0x4,
+	BUSNUM_MCP1 = 0x5,
+	BUSNUM_MCP2 = 0x6,
+};
+
+/*
+ * If the DT nodes are handy, determine which MEMC holds the specified
+ * physical address.
+ */
+#ifdef CONFIG_ARCH_BRCMSTB
+int __brcmstb_memory_phys_addr_to_memc(phys_addr_t pa, void __iomem *base)
+{
+	int memc = -1;
+	int i;
+
+	for (i = 0; i < NUM_BUS_RANGES; i++, base += 8) {
+		const u64 ulimit_raw = readl(base);
+		const u64 llimit_raw = readl(base + 4);
+		const u64 ulimit =
+			((ulimit_raw >> BUS_RANGE_ULIMIT_SHIFT)
+			 << BUS_RANGE_PA_SHIFT) | 0xfff;
+		const u64 llimit = (llimit_raw >> BUS_RANGE_LLIMIT_SHIFT)
+				   << BUS_RANGE_PA_SHIFT;
+		const u32 busnum = (u32)(ulimit_raw & 0xf);
+
+		if (pa >= llimit && pa <= ulimit) {
+			if (busnum >= BUSNUM_MCP0 && busnum <= BUSNUM_MCP2) {
+				memc = busnum - BUSNUM_MCP0;
+				break;
+			}
+		}
+	}
+
+	return memc;
+}
+
+int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa)
+{
+	int memc = -1;
+	struct device_node *np;
+	void __iomem *cpubiuctrl;
+
+	np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
+	if (!np)
+		return memc;
+
+	cpubiuctrl = of_iomap(np, 0);
+	if (!cpubiuctrl)
+		goto cleanup;
+
+	memc = __brcmstb_memory_phys_addr_to_memc(pa, cpubiuctrl);
+	iounmap(cpubiuctrl);
+
+cleanup:
+	of_node_put(np);
+
+	return memc;
+}
+
+#elif defined(CONFIG_MIPS)
+int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa)
+{
+	/* The logic here is fairly simple and hardcoded: if pa <= 0x5000_0000,
+	 * then this is MEMC0, else MEMC1.
+	 *
+	 * For systems with 2GB on MEMC0, MEMC1 starts at 9000_0000, with 1GB
+	 * on MEMC0, MEMC1 starts at 6000_0000.
+	 */
+	if (pa >= 0x50000000ULL)
+		return 1;
+	else
+		return 0;
+}
+#endif
+
+u64 brcmstb_memory_memc_size(int memc)
+{
+	const void *fdt = initial_boot_params;
+	const int mem_offset = fdt_path_offset(fdt, "/memory");
+	int addr_cells = 1, size_cells = 1;
+	const struct fdt_property *prop;
+	int proplen, cellslen;
+	u64 memc_size = 0;
+	int i;
+
+	/* Get root size and address cells if specified */
+	prop = fdt_get_property(fdt, 0, "#size-cells", &proplen);
+	if (prop)
+		size_cells = DT_PROP_DATA_TO_U32(prop->data, 0);
+
+	prop = fdt_get_property(fdt, 0, "#address-cells", &proplen);
+	if (prop)
+		addr_cells = DT_PROP_DATA_TO_U32(prop->data, 0);
+
+	if (mem_offset < 0)
+		return -1;
+
+	prop = fdt_get_property(fdt, mem_offset, "reg", &proplen);
+	cellslen = (int)sizeof(u32) * (addr_cells + size_cells);
+	if ((proplen % cellslen) != 0)
+		return -1;
+
+	for (i = 0; i < proplen / cellslen; ++i) {
+		u64 addr = 0;
+		u64 size = 0;
+		int memc_idx;
+		int j;
+
+		for (j = 0; j < addr_cells; ++j) {
+			int offset = (cellslen * i) + (sizeof(u32) * j);
+
+			addr |= (u64)DT_PROP_DATA_TO_U32(prop->data, offset) <<
+				((addr_cells - j - 1) * 32);
+		}
+		for (j = 0; j < size_cells; ++j) {
+			int offset = (cellslen * i) +
+				(sizeof(u32) * (j + addr_cells));
+
+			size |= (u64)DT_PROP_DATA_TO_U32(prop->data, offset) <<
+				((size_cells - j - 1) * 32);
+		}
+
+		if ((phys_addr_t)addr != addr) {
+			pr_err("phys_addr_t is smaller than provided address 0x%llx!\n",
+			       addr);
+			return -1;
+		}
+
+		memc_idx = brcmstb_memory_phys_addr_to_memc((phys_addr_t)addr);
+		if (memc_idx == memc)
+			memc_size += size;
+	}
+
+	return memc_size;
+}
+EXPORT_SYMBOL_GPL(brcmstb_memory_memc_size);
+
diff --git a/include/soc/brcmstb/memory_api.h b/include/soc/brcmstb/memory_api.h
new file mode 100644
index 0000000..d922906
--- /dev/null
+++ b/include/soc/brcmstb/memory_api.h
@@ -0,0 +1,25 @@
+#ifndef __MEMORY_API_H
+#define __MEMORY_API_H
+
+/*
+ * Bus Interface Unit control register setup, must happen early during boot,
+ * before SMP is brought up, called by machine entry point.
+ */
+void brcmstb_biuctrl_init(void);
+
+#ifdef CONFIG_SOC_BRCMSTB
+int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa);
+u64 brcmstb_memory_memc_size(int memc);
+#else
+static inline int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa)
+{
+	return -EINVAL;
+}
+
+static inline u64 brcmstb_memory_memc_size(int memc)
+{
+	return -1;
+}
+#endif
+
+#endif /* __MEMORY_API_H */
-- 
1.9.0.138.g2de3478


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Re: [PATCH 1/8] SOC: brcmstb: add memory API

[Florian Fainelli]

Hi Jim,

On 10/24/2017 11:15 AM, Jim Quinlan wrote:
> +#elif defined(CONFIG_MIPS)
> +int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa)
> +{
> +	/* The logic here is fairly simple and hardcoded: if pa <= 0x5000_0000,
> +	 * then this is MEMC0, else MEMC1.
> +	 *
> +	 * For systems with 2GB on MEMC0, MEMC1 starts at 9000_0000, with 1GB
> +	 * on MEMC0, MEMC1 starts at 6000_0000.
> +	 */
> +	if (pa >= 0x50000000ULL)
> +		return 1;
> +	else
> +		return 0;
> +}
> +#endif

We may be missing an EXPORT_SYMBOL_GPL(brcmstb_memory_phys_to_addr_memc)
here?

Thanks!
-- 
Florian

Re: [PATCH 1/8] SOC: brcmstb: add memory API

[Jim Quinlan]

On Tue, Oct 24, 2017 at 8:23 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> Hi Jim,
>
> On 10/24/2017 11:15 AM, Jim Quinlan wrote:
>> +#elif defined(CONFIG_MIPS)
>> +int brcmstb_memory_phys_addr_to_memc(phys_addr_t pa)
>> +{
>> +     /* The logic here is fairly simple and hardcoded: if pa <= 0x5000_0000,
>> +      * then this is MEMC0, else MEMC1.
>> +      *
>> +      * For systems with 2GB on MEMC0, MEMC1 starts at 9000_0000, with 1GB
>> +      * on MEMC0, MEMC1 starts at 6000_0000.
>> +      */
>> +     if (pa >= 0x50000000ULL)
>> +             return 1;
>> +     else
>> +             return 0;
>> +}
>> +#endif
>
> We may be missing an EXPORT_SYMBOL_GPL(brcmstb_memory_phys_to_addr_memc)
> here?
>
> Thanks!
> --
> Florian

Hi Florian,

I removed that EXPORT_SYMBOL_GPL() because this particular call is not
directly invoked PCIe RC driver.  It is indirectly invoked by
brcmstb_memory_memc_size(), which is exported.

Thanks, Jim

[PATCH 2/8] PCI: host: brcmstb: add DT docs for Brcmstb PCIe device

[Jim Quinlan]

The DT bindings description of the Brcmstb PCIe device is described.  This
node can be used by almost all Broadcom settop box chips, using
ARM, ARM64, or MIPS CPU architectures.

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 .../devicetree/bindings/pci/brcmstb-pci.txt        | 63 ++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pci.txt

diff --git a/Documentation/devicetree/bindings/pci/brcmstb-pci.txt b/Documentation/devicetree/bindings/pci/brcmstb-pci.txt
new file mode 100644
index 0000000..49f9852
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/brcmstb-pci.txt
@@ -0,0 +1,63 @@
+Brcmstb PCIe Host Controller Device Tree Bindings
+
+Required Properties:
+- compatible
+  "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs.
+  "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs.
+  "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including
+      the 7278).
+  "brcm,bcm7278-pcie"  -- for 7278 family ARM-based SOCs.
+
+- reg -- the register start address and length for the PCIe reg block.
+- interrupts -- two interrupts are specified; the first interrupt is for
+     the PCI host controller and the second is for MSI if the built-in
+     MSI controller is to be used.
+- interrupt-names -- names of the interrupts (above): "pcie" and "msi".
+- #address-cells -- set to <3>.
+- #size-cells -- set to <2>.
+- #interrupt-cells: set to <1>.
+- interrupt-map-mask and interrupt-map, standard PCI properties to define the
+     mapping of the PCIe interface to interrupt numbers.
+- ranges: ranges for the PCI memory and I/O regions.
+- linux,pci-domain -- should be unique per host controller.
+
+Optional Properties:
+- clocks -- phandle of pcie clock.
+- clock-names -- set to "sw_pcie" if clocks is used.
+- dma-ranges -- Specifies the inbound memory mapping regions when
+     an "identity map" is not possible.
+- msi-controller -- this property is typically specified to have the
+     PCIe controller use its internal MSI controller.
+- msi-parent -- set to use an external MSI interrupt controller.
+- brcm,ssc -- (boolean) indicates usage of spread-spectrum clocking.
+- max-link-speed --  (integer) indicates desired generation of link:
+     1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3).
+- xyz-supply -- set to a voltage regulator phandle  that the root
+     complex should turn off/on/on on suspend/resume/boot.  Any property
+     matching '-supply' will be added to an internal list of phandles.
+
+
+Example Node:
+
+pcie0: pcie@f0460000 {
+		reg = <0x0 0xf0460000 0x0 0x9310>;
+		interrupts = <0x0 0x0 0x4>;
+		compatible = "brcm,pci-plat-dev";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000
+			  0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &intc 0 47 3
+				 0 0 0 2 &intc 0 48 3
+				 0 0 0 3 &intc 0 49 3
+				 0 0 0 4 &intc 0 50 3>;
+		clocks = <&sw_pcie0>;
+		clock-names = "sw_pcie";
+		msi-parent = <&pcie0>;  /* use PCIe's internal MSI controller */
+		msi-controller;         /* use PCIe's internal MSI controller */
+		brcm,ssc;
+		max-link-speed = <1>;
+		linux,pci-domain = <0>;
+	};
-- 
1.9.0.138.g2de3478

Re: [PATCH 2/8] PCI: host: brcmstb: add DT docs for Brcmstb PCIe device

[Rob Herring]

On Tue, Oct 24, 2017 at 02:15:43PM -0400, Jim Quinlan wrote:
> The DT bindings description of the Brcmstb PCIe device is described.  This
> node can be used by almost all Broadcom settop box chips, using
> ARM, ARM64, or MIPS CPU architectures.

"dt-bindings: pci: ..." for the subject please.

> 
> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> ---
>  .../devicetree/bindings/pci/brcmstb-pci.txt        | 63 ++++++++++++++++++++++
>  1 file changed, 63 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pci.txt
> 
> diff --git a/Documentation/devicetree/bindings/pci/brcmstb-pci.txt b/Documentation/devicetree/bindings/pci/brcmstb-pci.txt
> new file mode 100644
> index 0000000..49f9852
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/brcmstb-pci.txt
> @@ -0,0 +1,63 @@
> +Brcmstb PCIe Host Controller Device Tree Bindings
> +
> +Required Properties:
> +- compatible
> +  "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs.
> +  "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs.
> +  "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including
> +      the 7278).
> +  "brcm,bcm7278-pcie"  -- for 7278 family ARM-based SOCs.
> +
> +- reg -- the register start address and length for the PCIe reg block.
> +- interrupts -- two interrupts are specified; the first interrupt is for
> +     the PCI host controller and the second is for MSI if the built-in
> +     MSI controller is to be used.
> +- interrupt-names -- names of the interrupts (above): "pcie" and "msi".
> +- #address-cells -- set to <3>.
> +- #size-cells -- set to <2>.
> +- #interrupt-cells: set to <1>.
> +- interrupt-map-mask and interrupt-map, standard PCI properties to define the
> +     mapping of the PCIe interface to interrupt numbers.
> +- ranges: ranges for the PCI memory and I/O regions.
> +- linux,pci-domain -- should be unique per host controller.
> +
> +Optional Properties:
> +- clocks -- phandle of pcie clock.
> +- clock-names -- set to "sw_pcie" if clocks is used.
> +- dma-ranges -- Specifies the inbound memory mapping regions when
> +     an "identity map" is not possible.
> +- msi-controller -- this property is typically specified to have the
> +     PCIe controller use its internal MSI controller.
> +- msi-parent -- set to use an external MSI interrupt controller.
> +- brcm,ssc -- (boolean) indicates usage of spread-spectrum clocking.

Use the same one already defined for Broadcom SATA phy.

> +- max-link-speed --  (integer) indicates desired generation of link:
> +     1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3).
> +- xyz-supply -- set to a voltage regulator phandle  that the root
> +     complex should turn off/on/on on suspend/resume/boot.  Any property
> +     matching '-supply' will be added to an internal list of phandles.

Still not really liking this...

> +
> +
> +Example Node:
> +
> +pcie0: pcie@f0460000 {
> +		reg = <0x0 0xf0460000 0x0 0x9310>;
> +		interrupts = <0x0 0x0 0x4>;
> +		compatible = "brcm,pci-plat-dev";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000
> +			  0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>;
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 7>;
> +		interrupt-map = <0 0 0 1 &intc 0 47 3
> +				 0 0 0 2 &intc 0 48 3
> +				 0 0 0 3 &intc 0 49 3
> +				 0 0 0 4 &intc 0 50 3>;
> +		clocks = <&sw_pcie0>;
> +		clock-names = "sw_pcie";
> +		msi-parent = <&pcie0>;  /* use PCIe's internal MSI controller */
> +		msi-controller;         /* use PCIe's internal MSI controller */
> +		brcm,ssc;
> +		max-link-speed = <1>;
> +		linux,pci-domain = <0>;
> +	};
> -- 
> 1.9.0.138.g2de3478
> 

Re: [PATCH 2/8] PCI: host: brcmstb: add DT docs for Brcmstb PCIe device

[Jonas Gorski]

Hi,

On 24 October 2017 at 20:15, Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> The DT bindings description of the Brcmstb PCIe device is described.  This
> node can be used by almost all Broadcom settop box chips, using
> ARM, ARM64, or MIPS CPU architectures.
>
> Signed-off-by: Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  .../devicetree/bindings/pci/brcmstb-pci.txt        | 63 ++++++++++++++++++++++
>  1 file changed, 63 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pci.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/brcmstb-pci.txt b/Documentation/devicetree/bindings/pci/brcmstb-pci.txt
> new file mode 100644
> index 0000000..49f9852
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/brcmstb-pci.txt
> @@ -0,0 +1,63 @@
> +Brcmstb PCIe Host Controller Device Tree Bindings
> +
> +Required Properties:
> +- compatible
> +  "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs.
> +  "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs.
> +  "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including
> +      the 7278).
> +  "brcm,bcm7278-pcie"  -- for 7278 family ARM-based SOCs.
> +

(snip)

> +
> +Example Node:
> +
> +pcie0: pcie@f0460000 {
> +               reg = <0x0 0xf0460000 0x0 0x9310>;
> +               interrupts = <0x0 0x0 0x4>;
> +               compatible = "brcm,pci-plat-dev";

This is not one of the valid compatibles mentioned above.


Regards
Jonas
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[PATCH 3/8] PCI: host: brcmstb: Broadcom PCIe Host Controller

[Jim Quinlan]

This commit adds the basic Broadcom STB PCIe controller.  Missing is
the ability to process MSI and also handle dma-ranges for inbound
memory accesses.  These two functionalities are added in subsequent
commits.

The PCIe block contains an MDIO interface.  This is a local interface
only accessible by the PCIe controller.  It cannot be used or shared
by any other HW.  As such, the small amount of code for this
controller is included in this driver as there is little upside to put
it elsewhere.

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 drivers/pci/host/Kconfig       |    8 +
 drivers/pci/host/Makefile      |    1 +
 drivers/pci/host/pci-brcmstb.c | 1195 ++++++++++++++++++++++++++++++++++++++++
 drivers/pci/host/pci-brcmstb.h |   33 ++
 4 files changed, 1237 insertions(+)
 create mode 100644 drivers/pci/host/pci-brcmstb.c
 create mode 100644 drivers/pci/host/pci-brcmstb.h

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index b868803..b9b4f11 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -220,4 +220,12 @@ config VMD
 	  To compile this driver as a module, choose M here: the
 	  module will be called vmd.
 
+config PCI_BRCMSTB
+	tristate "Broadcom Brcmstb PCIe platform host driver"
+	depends on ARCH_BRCMSTB || BMIPS_GENERIC
+	depends on OF
+	depends on SOC_BRCMSTB
+	default ARCH_BRCMSTB || BMIPS_GENERIC
+	help
+	  Adds support for Broadcom Settop Box PCIe host controller.
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 1238278..4398d2c 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
+obj-$(CONFIG_PCI_BRCMSTB) += pci-brcmstb.o
 
 # The following drivers are for devices that use the generic ACPI
 # pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/host/pci-brcmstb.c b/drivers/pci/host/pci-brcmstb.c
new file mode 100644
index 0000000..883b435
--- /dev/null
+++ b/drivers/pci/host/pci-brcmstb.c
@@ -0,0 +1,1195 @@
+/*
+ * Copyright (C) 2009 - 2017 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/clk.h>
+#include <linux/compiler.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/log2.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/printk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+#include <soc/brcmstb/memory_api.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include "pci-brcmstb.h"
+
+/* Broadcom Settop Box PCIE Register Offsets.  */
+#define PCIE_RC_CFG_PCIE_LINK_CAPABILITY		0x00b8
+#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL		0x00bc
+#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL		0x00c8
+#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2		0x00dc
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1		0x0188
+#define PCIE_RC_CFG_PRIV1_ID_VAL3			0x043c
+#define PCIE_RC_DL_MDIO_ADDR				0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA				0x1104
+#define PCIE_RC_DL_MDIO_RD_DATA				0x1108
+#define PCIE_MISC_MISC_CTRL				0x4008
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO		0x400c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI		0x4010
+#define PCIE_MISC_RC_BAR1_CONFIG_LO			0x402c
+#define PCIE_MISC_RC_BAR1_CONFIG_HI			0x4030
+#define PCIE_MISC_RC_BAR2_CONFIG_LO			0x4034
+#define PCIE_MISC_RC_BAR2_CONFIG_HI			0x4038
+#define PCIE_MISC_RC_BAR3_CONFIG_LO			0x403c
+#define PCIE_MISC_RC_BAR3_CONFIG_HI			0x4040
+#define PCIE_MISC_PCIE_CTRL				0x4064
+#define PCIE_MISC_PCIE_STATUS				0x4068
+#define PCIE_MISC_REVISION				0x406c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT	0x4070
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI		0x4080
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI		0x4084
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG			0x4204
+
+/* Broadcom Settop Box PCIE Register Field Shift, Mask Info.  */
+#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_MASK  0x3f00000
+#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_SHIFT	0x14
+#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_MASK	0xf0000
+#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_SHIFT	0x10
+#define PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_MASK		0xf
+#define PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_SHIFT		0x0
+#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK		0x10
+#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_SHIFT		0x4
+#define	PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_MASK	0xf
+#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_SHIFT	0x0
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_MASK	0x3
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_SHIFT	0x0
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK	0xc
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT	0x2
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_MASK	0x30
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_SHIFT	0x4
+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK		0xffffff
+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT		0x0
+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK			0x1000
+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT			0xc
+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK		0x2000
+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT		0xd
+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK			0x300000
+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT		0x14
+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK			0xf8000000
+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT			0x1b
+#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK			0x7c00000
+#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT			0x16
+#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK			0x1f
+#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT			0x0
+#define PCIE_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_MASK		0xfffff000
+#define PCIE_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_SHIFT		0xc
+#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK			0x1f
+#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT			0x0
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_MASK		0xfffff000
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_SHIFT		0xc
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK			0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT			0x0
+#define PCIE_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_MASK		0xfffff000
+#define PCIE_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_SHIFT		0xc
+#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK			0x1f
+#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT			0x0
+#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK			0x4
+#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT			0x2
+#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK		0x1
+#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT		0x0
+#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK			0x80
+#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT			0x7
+#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK		0x20
+#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT		0x5
+#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK		0x10
+#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT		0x4
+#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK		0x40
+#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT		0x6
+#define PCIE_MISC_REVISION_MAJMIN_MASK				0xffff
+#define PCIE_MISC_REVISION_MAJMIN_SHIFT				0
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK	0xfff00000
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT	0x14
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK	0xfff0
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT	0x4
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS	0xc
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK		0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT	0x0
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK	0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT	0x0
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK	0x2
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK		0x08000000
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT	0x1b
+#define PCIE_RGR1_SW_INIT_1_PERST_MASK				0x1
+#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT				0x0
+
+#define BRCM_NUM_PCI_OUT_WINS		0x4
+#define BRCM_MAX_SCB			0x4
+
+#define BRCM_MSI_TARGET_ADDR_LT_4GB	0x0fffffffcULL
+#define BRCM_MSI_TARGET_ADDR_GT_4GB	0xffffffffcULL
+
+#define BURST_SIZE_128			0
+#define BURST_SIZE_256			1
+#define BURST_SIZE_512			2
+
+/* Offsets from PCIE_INTR2_CPU_BASE */
+#define STATUS				0x0
+#define SET				0x4
+#define CLR				0x8
+#define MASK_STATUS			0xc
+#define MASK_SET			0x10
+#define MASK_CLR			0x14
+
+#define PCI_BUSNUM_SHIFT		20
+#define PCI_SLOT_SHIFT			15
+#define PCI_FUNC_SHIFT			12
+
+#if defined(__BIG_ENDIAN)
+#define	DATA_ENDIAN		2	/* PCI->DDR inbound accesses */
+#define MMIO_ENDIAN		2	/* CPU->PCI outbound accesses */
+#else
+#define	DATA_ENDIAN		0
+#define MMIO_ENDIAN		0
+#endif
+
+#define MDIO_PORT0		0x0
+#define MDIO_DATA_MASK		0x7fffffff
+#define MDIO_DATA_SHIFT		0x0
+#define MDIO_PORT_MASK		0xf0000
+#define MDIO_PORT_SHIFT		0x16
+#define MDIO_REGAD_MASK		0xffff
+#define MDIO_REGAD_SHIFT	0x0
+#define MDIO_CMD_MASK		0xfff00000
+#define MDIO_CMD_SHIFT		0x14
+#define MDIO_CMD_READ		0x1
+#define MDIO_CMD_WRITE		0x0
+#define MDIO_DATA_DONE_MASK	0x80000000
+#define MDIO_RD_DONE(x)		(((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
+#define MDIO_WT_DONE(x)		(((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
+#define SSC_REGS_ADDR		0x1100
+#define SET_ADDR_OFFSET		0x1f
+#define SSC_CNTL_OFFSET		0x2
+#define SSC_CNTL_OVRD_EN_MASK	0x8000
+#define SSC_CNTL_OVRD_EN_SHIFT	0xf
+#define SSC_CNTL_OVRD_VAL_MASK	0x4000
+#define SSC_CNTL_OVRD_VAL_SHIFT	0xe
+#define SSC_STATUS_OFFSET	0x1
+#define SSC_STATUS_SSC_MASK	0x400
+#define SSC_STATUS_SSC_SHIFT	0xa
+#define SSC_STATUS_PLL_LOCK_MASK	0x800
+#define SSC_STATUS_PLL_LOCK_SHIFT	0xb
+
+#define IDX_ADDR(pcie)	\
+	((pcie)->reg_offsets[EXT_CFG_INDEX])
+#define DATA_ADDR(pcie)	\
+	((pcie)->reg_offsets[EXT_CFG_DATA])
+#define PCIE_RGR1_SW_INIT_1(pcie) \
+	((pcie)->reg_offsets[RGR1_SW_INIT_1])
+
+enum {
+	RGR1_SW_INIT_1,
+	EXT_CFG_INDEX,
+	EXT_CFG_DATA,
+};
+
+enum {
+	RGR1_SW_INIT_1_INIT_MASK,
+	RGR1_SW_INIT_1_INIT_SHIFT,
+	RGR1_SW_INIT_1_PERST_MASK,
+	RGR1_SW_INIT_1_PERST_SHIFT,
+};
+
+enum pcie_type {
+	BCM7425,
+	BCM7435,
+	GENERIC,
+	BCM7278,
+};
+
+#define RD_FLD(base, reg, field) \
+	rd_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
+#define WR_FLD(base, reg, field, val) \
+	wr_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
+#define WR_FLD_RB(base, reg, field, val) \
+	wr_fld_rb(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
+#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
+	wr_fld(base + reg + off, reg##_##field##_MASK, \
+	       reg##_##field##_SHIFT, val)
+#define EXTRACT_FIELD(val, reg, field) \
+	((val & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
+#define INSERT_FIELD(val, reg, field, field_val) \
+	((val & ~reg##_##field##_MASK) | \
+	 (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
+
+struct pcie_cfg_data {
+	const int *reg_field_info;
+	const int *offsets;
+	const enum pcie_type type;
+};
+
+static const int pcie_reg_field_info[] = {
+	[RGR1_SW_INIT_1_INIT_MASK] = 0x2,
+	[RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
+};
+
+static const int pcie_reg_field_info_bcm7278[] = {
+	[RGR1_SW_INIT_1_INIT_MASK] = 0x1,
+	[RGR1_SW_INIT_1_INIT_SHIFT] = 0x0,
+};
+
+static const int pcie_offset_bcm7425[] = {
+	[RGR1_SW_INIT_1] = 0x8010,
+	[EXT_CFG_INDEX]  = 0x8300,
+	[EXT_CFG_DATA]   = 0x8304,
+};
+
+static const struct pcie_cfg_data bcm7425_cfg = {
+	.reg_field_info	= pcie_reg_field_info,
+	.offsets	= pcie_offset_bcm7425,
+	.type		= BCM7425,
+};
+
+static const int pcie_offsets[] = {
+	[RGR1_SW_INIT_1] = 0x9210,
+	[EXT_CFG_INDEX]  = 0x9000,
+	[EXT_CFG_DATA]   = 0x9004,
+};
+
+static const struct pcie_cfg_data bcm7435_cfg = {
+	.reg_field_info	= pcie_reg_field_info,
+	.offsets	= pcie_offsets,
+	.type		= BCM7435,
+};
+
+static const struct pcie_cfg_data generic_cfg = {
+	.reg_field_info	= pcie_reg_field_info,
+	.offsets	= pcie_offsets,
+	.type		= GENERIC,
+};
+
+static const int pcie_offset_bcm7278[] = {
+	[RGR1_SW_INIT_1] = 0xc010,
+	[EXT_CFG_INDEX] = 0x9000,
+	[EXT_CFG_DATA] = 0x9004,
+};
+
+static const struct pcie_cfg_data bcm7278_cfg = {
+	.reg_field_info = pcie_reg_field_info_bcm7278,
+	.offsets	= pcie_offset_bcm7278,
+	.type		= BCM7278,
+};
+
+static void __iomem *brcm_pci_map_cfg(struct pci_bus *bus, unsigned int devfn,
+				      int where);
+
+static struct pci_ops brcm_pci_ops = {
+	.map_bus = brcm_pci_map_cfg,
+	.read = pci_generic_config_read32,
+	.write = pci_generic_config_write32,
+};
+
+struct brcm_dev_pwr_supply {
+	struct list_head node;
+	char name[32];
+	struct regulator *regulator;
+};
+
+struct brcm_window {
+	dma_addr_t pci_addr;
+	phys_addr_t cpu_addr;
+	dma_addr_t size;
+};
+
+/* Internal Bus Controller Information.*/
+struct brcm_pcie {
+	struct list_head	list;
+	void __iomem		*base;
+	char			name[BRCM_PCIE_NAME_SIZE];
+	bool			suspended;
+	struct clk		*clk;
+	struct device_node	*dn;
+	int			irq;
+	int			num_out_wins;
+	bool			ssc;
+	int			gen;
+	struct brcm_window	out_wins[BRCM_NUM_PCI_OUT_WINS];
+	struct list_head	resources;
+	struct device		*dev;
+	struct list_head	pwr_supplies;
+	unsigned int		rev;
+	unsigned int		num;
+	bool			bridge_setup_done;
+	const int		*reg_offsets;
+	const int		*reg_field_info;
+	enum pcie_type		type;
+	struct pci_bus		*root_bus;
+	int			id;
+};
+
+static struct list_head brcm_pcie = LIST_HEAD_INIT(brcm_pcie);
+static phys_addr_t scb_size[BRCM_MAX_SCB];
+static int num_memc;
+static DEFINE_MUTEX(brcm_pcie_lock);
+
+/*
+ * The roundup_pow_of_two() from log2.h invokes
+ * __roundup_pow_of_two(unsigned long), but we really need a
+ * such a function to take a native u64 since unsigned long
+ * is 32 bits on some configurations.  So we provide this helper
+ * function below.
+ */
+static u64 roundup_pow_of_two_64(u64 n)
+{
+	return 1ULL << fls64(n - 1);
+}
+
+static int brcm_pcie_add_controller(struct brcm_pcie *pcie)
+{
+	mutex_lock(&brcm_pcie_lock);
+	snprintf(pcie->name, sizeof(pcie->name) - 1, "PCIe%d", pcie->id);
+	list_add_tail(&pcie->list, &brcm_pcie);
+	mutex_unlock(&brcm_pcie_lock);
+
+	return 0;
+}
+
+static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
+{
+	struct list_head *pos, *q;
+	struct brcm_pcie *tmp;
+
+	mutex_lock(&brcm_pcie_lock);
+	list_for_each_safe(pos, q, &brcm_pcie) {
+		tmp = list_entry(pos, struct brcm_pcie, list);
+		if (tmp == pcie) {
+			list_del(pos);
+			if (list_empty(&brcm_pcie))
+				num_memc = 0;
+			break;
+		}
+	}
+	mutex_unlock(&brcm_pcie_lock);
+}
+
+/* This is to convert the size of the inbound bar region to the
+ * non-liniear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
+ */
+int encode_ibar_size(u64 size)
+{
+	int log2_in = ilog2(size);
+
+	if (log2_in >= 12 && log2_in <= 15)
+		/* Covers 4KB to 32KB (inclusive) */
+		return (log2_in - 12) + 0x1c;
+	else if (log2_in >= 16 && log2_in <= 37)
+		/* Covers 64KB to 32GB, (inclusive) */
+		return log2_in - 15;
+	/* Something is awry so disable */
+	return 0;
+}
+
+static u32 mdio_form_pkt(int port, int regad, int cmd)
+{
+	u32 pkt = 0;
+
+	pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
+	pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
+	pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
+
+	return pkt;
+}
+
+/* negative return value indicates error */
+static int mdio_read(void __iomem *base, u8 port, u8 regad)
+{
+	int tries;
+	u32 data;
+
+	bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
+		   base + PCIE_RC_DL_MDIO_ADDR);
+	bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
+
+	data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
+	for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
+		udelay(10);
+		data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
+	}
+
+	return MDIO_RD_DONE(data)
+		? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
+		: -EIO;
+}
+
+/* negative return value indicates error */
+static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
+{
+	int tries;
+	u32 data;
+
+	bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
+		   base + PCIE_RC_DL_MDIO_ADDR);
+	bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
+	bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
+		   base + PCIE_RC_DL_MDIO_WR_DATA);
+
+	data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
+	for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
+		udelay(10);
+		data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
+	}
+
+	return MDIO_WT_DONE(data) ? 0 : -EIO;
+}
+
+static u32 rd_fld(void __iomem *p, u32 mask, int shift)
+{
+	return (bcm_readl(p) & mask) >> shift;
+}
+
+static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
+{
+	u32 reg = bcm_readl(p);
+
+	reg = (reg & ~mask) | ((val << shift) & mask);
+	bcm_writel(reg, p);
+}
+
+static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
+{
+	wr_fld(p, mask, shift, val);
+	(void)bcm_readl(p);
+}
+
+/* configures device for ssc mode; negative return value indicates error */
+static int set_ssc(void __iomem *base)
+{
+	int tmp;
+	u16 wrdata;
+	int pll, ssc;
+
+	tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
+	if (tmp < 0)
+		return tmp;
+
+	tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
+	if (tmp < 0)
+		return tmp;
+
+	wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
+	wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
+	tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
+	if (tmp < 0)
+		return tmp;
+
+	usleep_range(1000, 2000);
+	tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
+	if (tmp < 0)
+		return tmp;
+
+	ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
+	pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
+
+	return (ssc && pll) ? 0 : -EIO;
+}
+
+/* limits operation to a specific generation (1, 2, or 3) */
+static void set_gen(void __iomem *base, int gen)
+{
+	WR_FLD(base, PCIE_RC_CFG_PCIE_LINK_CAPABILITY, MAX_LINK_SPEED, gen);
+	WR_FLD(base, PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2,
+	       TARGET_LINK_SPEED, gen);
+}
+
+static void set_pcie_outbound_win(struct brcm_pcie *pcie, unsigned int win,
+				  phys_addr_t cpu_addr, dma_addr_t  pci_addr,
+				  dma_addr_t size)
+{
+	void __iomem *base = pcie->base;
+	phys_addr_t cpu_addr_mb, limit_addr_mb;
+	u32 tmp;
+
+	/* Set the base of the pci_addr window */
+	bcm_writel(lower_32_bits(pci_addr) + MMIO_ENDIAN,
+		   base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
+	bcm_writel(upper_32_bits(pci_addr),
+		   base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
+
+	cpu_addr_mb = cpu_addr >> 20;
+	limit_addr_mb = (cpu_addr + size - 1) >> 20;
+
+	/* Write the addr base low register */
+	WR_FLD_WITH_OFFSET(base, (win * 4),
+			   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
+			   BASE, cpu_addr_mb);
+	/* Write the addr limit low register */
+	WR_FLD_WITH_OFFSET(base, (win * 4),
+			   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
+			   LIMIT, limit_addr_mb);
+
+	if (pcie->type != BCM7435 && pcie->type != BCM7425) {
+		/* Write the cpu addr high register */
+		tmp = (u32)(cpu_addr_mb >>
+			PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
+		WR_FLD_WITH_OFFSET(base, (win * 8),
+				   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
+				   BASE, tmp);
+		/* Write the cpu limit high register */
+		tmp = (u32)(limit_addr_mb >>
+			PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
+		WR_FLD_WITH_OFFSET(base, (win * 8),
+				   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
+				   LIMIT, tmp);
+	}
+}
+
+static int is_pcie_link_up(struct brcm_pcie *pcie, bool silent)
+{
+	void __iomem *base = pcie->base;
+	u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
+	u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
+	u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
+	u32 rc = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
+
+	if (!rc && !silent)
+		dev_err(pcie->dev, "controller configured in EP mode\n");
+
+	return  (rc && dla && plu) ? 1 : 0;
+}
+
+static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
+						unsigned int val)
+{
+	unsigned int offset;
+	unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
+	u32 mask =  pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
+
+	if (pcie->type != BCM7278) {
+		wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
+			  val);
+	} else if (of_machine_is_compatible("brcm,bcm7278a0")) {
+		/* The two PCIE instance on 7278a0 are not even consistent with
+		 * respect to each other for internal offsets, here we offset
+		 * by 0x14000 + RGR1_SW_INIT_1's relative offset to account for
+		 * that.
+		 */
+		offset = pcie->id ? 0x14010 : pcie->reg_offsets[RGR1_SW_INIT_1];
+		wr_fld_rb(pcie->base + offset, mask, shift, val);
+	} else {
+		wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
+			  val);
+	}
+}
+
+static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
+				       unsigned int val)
+{
+	if (pcie->type != BCM7278)
+		wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
+			  PCIE_RGR1_SW_INIT_1_PERST_MASK,
+			  PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
+	else
+		/* Assert = 0, de-assert = 1 on 7278 */
+		WR_FLD_RB(pcie->base, PCIE_MISC_PCIE_CTRL, PCIE_PERSTB, !val);
+}
+
+static int brcm_parse_ranges(struct brcm_pcie *pcie)
+{
+	struct resource_entry *win;
+	int ret;
+
+	ret = of_pci_get_host_bridge_resources(pcie->dn, 0, 0xff,
+					       &pcie->resources, NULL);
+	if (ret) {
+		dev_err(pcie->dev, "failed to get host resources\n");
+		return ret;
+	}
+
+	resource_list_for_each_entry(win, &pcie->resources) {
+		struct resource *parent, *res = win->res;
+		dma_addr_t offset = (dma_addr_t)win->offset;
+
+		if (resource_type(res) == IORESOURCE_IO) {
+			parent = &ioport_resource;
+		} else if (resource_type(res) == IORESOURCE_MEM) {
+			if (pcie->num_out_wins >= BRCM_NUM_PCI_OUT_WINS) {
+				dev_err(pcie->dev, "too many outbound wins\n");
+				return -EINVAL;
+			}
+			pcie->out_wins[pcie->num_out_wins].cpu_addr
+				= (phys_addr_t)res->start;
+			pcie->out_wins[pcie->num_out_wins].pci_addr
+				= (dma_addr_t)(res->start
+					       - (phys_addr_t)offset);
+			pcie->out_wins[pcie->num_out_wins].size
+				= (dma_addr_t)(res->end - res->start + 1);
+			pcie->num_out_wins++;
+			parent = &iomem_resource;
+		} else {
+			continue;
+		}
+
+		ret = devm_request_resource(pcie->dev, parent, res);
+		if (ret) {
+			dev_err(pcie->dev, "failed to get res %pR\n", res);
+			return ret;
+		}
+	}
+	return 0;
+}
+
+static void set_regulators(struct brcm_pcie *pcie, bool on)
+{
+	struct list_head *pos;
+
+	list_for_each(pos, &pcie->pwr_supplies) {
+		struct brcm_dev_pwr_supply *supply
+			= list_entry(pos, struct brcm_dev_pwr_supply, node);
+
+		if (on && regulator_enable(supply->regulator))
+			pr_debug("Unable to turn on %s supply.\n",
+				 supply->name);
+		else if (!on && regulator_disable(supply->regulator))
+			pr_debug("Unable to turn off %s supply.\n",
+				 supply->name);
+	}
+}
+
+static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
+{
+	void __iomem *base = pcie->base;
+	unsigned int scb_size_val;
+	u64 rc_bar2_size = 0, rc_bar2_offset = 0, total_mem_size = 0;
+	u32 tmp, burst;
+	int i;
+
+	/* reset the bridge and the endpoint device */
+	/* field: PCIE_BRIDGE_SW_INIT = 1 */
+	brcm_pcie_bridge_sw_init_set(pcie, 1);
+
+	/* field: PCIE_SW_PERST = 1, on 7278, we start de-asserted already */
+	if (pcie->type != BCM7278)
+		brcm_pcie_perst_set(pcie, 1);
+
+	usleep_range(100, 200);
+
+	/* take the bridge out of reset */
+	/* field: PCIE_BRIDGE_SW_INIT = 0 */
+	brcm_pcie_bridge_sw_init_set(pcie, 0);
+
+	WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
+	/* wait for serdes to be stable */
+	usleep_range(100, 200);
+
+	/* Grab the PCIe hw revision number */
+	tmp = bcm_readl(base + PCIE_MISC_REVISION);
+	pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
+
+	/* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
+	tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
+	tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
+	burst = (pcie->type == GENERIC || pcie->type == BCM7278)
+		? BURST_SIZE_512 : BURST_SIZE_256;
+	tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE, burst);
+	bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
+
+	/* Set up inbound memory view for the EP (called RC_BAR2,
+	 * not to be confused with the BARs that are advertised by
+	 * the EP).
+	 */
+	for (i = 0; i < num_memc; i++)
+		total_mem_size += scb_size[i];
+
+	/* The PCI host controller by design must set the inbound
+	 * viewport to be a contiguous arrangement of all of the
+	 * system's memory.  In addition, its size mut be a power of
+	 * two.  To further complicate matters, the viewport must
+	 * start on a pci-address that is aligned on a multiple of its
+	 * size.  If a portion of the viewport does not represent
+	 * system memory -- e.g. 3GB of memory requires a 4GB viewport
+	 * -- we can map the outbound memory in or after 3GB and even
+	 * though the viewport will overlap the outbound memory the
+	 * controller will know to send outbound memory downstream and
+	 * everything else upstream.
+	 */
+	rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
+
+	/* Set simple configuration based on memory sizes
+	 * only.  We always start the viewport at address 0.
+	 */
+	rc_bar2_offset = 0;
+
+	tmp = lower_32_bits(rc_bar2_offset);
+	tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
+			   encode_ibar_size(rc_bar2_size));
+	bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
+	bcm_writel(upper_32_bits(rc_bar2_offset),
+		   base + PCIE_MISC_RC_BAR2_CONFIG_HI);
+
+	/* field: SCB0_SIZE, default = 0xf (1 GB) */
+	scb_size_val = scb_size[0]
+		? ilog2(scb_size[0]) - 15 : 0xf;
+	WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
+
+	/* field: SCB1_SIZE, default = 0xf (1 GB) */
+	if (num_memc > 1) {
+		scb_size_val = scb_size[1]
+			? ilog2(scb_size[1]) - 15 : 0xf;
+		WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB1_SIZE, scb_size_val);
+	}
+
+	/* field: SCB2_SIZE, default = 0xf (1 GB) */
+	if (num_memc > 2) {
+		scb_size_val = scb_size[2]
+			? ilog2(scb_size[2]) - 15 : 0xf;
+		WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB2_SIZE, scb_size_val);
+	}
+
+	/* disable the PCIE->GISB memory window (RC_BAR1) */
+	WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
+
+	/* disable the PCIE->SCB memory window (RC_BAR3) */
+	WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
+
+	if (!pcie->suspended) {
+		/* clear any interrupts we find on boot */
+		bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
+		(void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
+	}
+
+	/* Mask all interrupts since we are not handling any yet */
+	bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
+	(void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
+
+	if (pcie->gen)
+		set_gen(base, pcie->gen);
+
+	/* take the EP device out of reset */
+	/* field: PCIE_SW_PERST = 0 */
+	brcm_pcie_perst_set(pcie, 0);
+}
+
+static const char *link_speed_to_str(int s)
+{
+	switch (s) {
+	case 1:
+		return "2.5";
+	case 2:
+		return "5.0";
+	case 3:
+		return "8.0";
+	default:
+		break;
+	}
+	return "???";
+}
+
+static int brcm_pcie_setup_bridge(struct brcm_pcie *pcie)
+{
+	void __iomem *base = pcie->base;
+	const int limit = pcie->suspended ? 1000 : 100;
+	unsigned int status;
+	int i, j, ret;
+	u32 neg_width, neg_speed;
+	bool ssc_good = false;
+
+	/* Give the RC/EP time to wake up, before trying to configure RC.
+	 * Intermittently check status for link-up, up to a total of 100ms
+	 * when we don't know if the device is there, and up to 1000ms if
+	 * we do know the device is there.
+	 */
+	for (i = 1, j = 0; j < limit && !is_pcie_link_up(pcie, true);
+	     j += i, i = i * 2)
+		msleep(i + j > limit ? limit - j : i);
+
+	if (!is_pcie_link_up(pcie, false)) {
+		dev_info(pcie->dev, "link down\n");
+		return -ENODEV;
+	}
+
+	for (i = 0; i < pcie->num_out_wins; i++)
+		set_pcie_outbound_win(pcie, i, pcie->out_wins[i].cpu_addr,
+				      pcie->out_wins[i].pci_addr,
+				      pcie->out_wins[i].size);
+
+	/* For config space accesses on the RC, show the right class for
+	 * a PCI-PCI bridge
+	 */
+	WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
+
+	if (pcie->ssc) {
+		ret = set_ssc(base);
+		if (ret == 0)
+			ssc_good = true;
+		else
+			dev_err(pcie->dev,
+				"failed attempt to enter ssc mode\n");
+	}
+
+	status = bcm_readl(base + PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL);
+	neg_width = EXTRACT_FIELD(status, PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL,
+				  NEG_LINK_WIDTH);
+	neg_speed = EXTRACT_FIELD(status, PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL,
+				  NEG_LINK_SPEED);
+	dev_info(pcie->dev, "link up, %s Gbps x%u %s\n",
+		 link_speed_to_str(neg_speed), neg_width,
+		 ssc_good ? "(SSC)" : "(!SSC)");
+
+	/* Enable configuration request retry (see pci_scan_device()) */
+	/* field RC_CRS_EN = 1 */
+	WR_FLD(base, PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL, RC_CRS_EN, 1);
+
+	/* PCIE->SCB endian mode for BAR */
+	/* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
+	WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
+		  ENDIAN_MODE_BAR2, DATA_ENDIAN);
+
+	/* Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
+	 * is enabled =>  setting the CLKREQ_DEBUG_ENABLE field to 1.
+	 */
+	WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
+
+	pcie->bridge_setup_done = true;
+
+	return 0;
+}
+
+static void enter_l23(struct brcm_pcie *pcie)
+{
+	void __iomem *base = pcie->base;
+	int tries, l23;
+
+	/* assert request for L23 */
+	WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
+	/* poll L23 status */
+	for (tries = 0, l23 = 0; tries < 1000 && !l23; tries++)
+		l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
+	if (!l23)
+		dev_err(pcie->dev, "failed to enter L23\n");
+}
+
+static void turn_off(struct brcm_pcie *pcie)
+{
+	void __iomem *base = pcie->base;
+
+	if (is_pcie_link_up(pcie, true))
+		enter_l23(pcie);
+	/* Reset endpoint device */
+	brcm_pcie_perst_set(pcie, 1);
+	/* deassert request for L23 in case it was asserted */
+	WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
+	/* SERDES_IDDQ = 1 */
+	WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
+	/* Shutdown PCIe bridge */
+	brcm_pcie_bridge_sw_init_set(pcie, 1);
+}
+
+static int brcm_pcie_suspend(struct device *dev)
+{
+	struct brcm_pcie *pcie = dev_get_drvdata(dev);
+
+	if (!pcie->bridge_setup_done)
+		return 0;
+
+	turn_off(pcie);
+	clk_disable_unprepare(pcie->clk);
+	set_regulators(pcie, false);
+	pcie->suspended = true;
+
+	return 0;
+}
+
+static int brcm_pcie_resume(struct device *dev)
+{
+	struct brcm_pcie *pcie = dev_get_drvdata(dev);
+	void __iomem *base;
+	int ret;
+
+	if (!pcie->bridge_setup_done)
+		return 0;
+
+	base = pcie->base;
+	set_regulators(pcie, true);
+	clk_prepare_enable(pcie->clk);
+
+	/* Take bridge out of reset so we can access the SERDES reg */
+	brcm_pcie_bridge_sw_init_set(pcie, 0);
+
+	/* SERDES_IDDQ = 0 */
+	WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
+	/* wait for serdes to be stable */
+	usleep_range(100, 200);
+
+	brcm_pcie_setup_prep(pcie);
+
+	ret = brcm_pcie_setup_bridge(pcie);
+	if (ret)
+		return ret;
+
+	pcie->suspended = false;
+
+	return 0;
+}
+
+/* Configuration space read/write support */
+static int cfg_index(int busnr, int devfn, int reg)
+{
+	return ((PCI_SLOT(devfn) & 0x1f) << PCI_SLOT_SHIFT)
+		| ((PCI_FUNC(devfn) & 0x07) << PCI_FUNC_SHIFT)
+		| (busnr << PCI_BUSNUM_SHIFT)
+		| (reg & ~3);
+}
+
+static void __iomem *brcm_pci_map_cfg(struct pci_bus *bus, unsigned int devfn,
+				      int where)
+{
+	struct brcm_pcie *pcie = bus->sysdata;
+	void __iomem *base = pcie->base;
+	bool rc_access = pci_is_root_bus(bus);
+	int idx;
+
+	if (!is_pcie_link_up(pcie, true))
+		return NULL;
+
+	base = pcie->base;
+	idx = cfg_index(bus->number, devfn, where);
+
+	bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
+
+	if (rc_access) {
+		if (PCI_SLOT(devfn))
+			return NULL;
+		return base + (where & ~3);
+	}
+
+	return pcie->base + DATA_ADDR(pcie);
+}
+
+static void __attribute__((__section__("pci_fixup_early")))
+brcm_pcibios_fixup(struct pci_dev *dev)
+{
+	struct brcm_pcie *pcie = dev->bus->sysdata;
+	u8 slot = PCI_SLOT(dev->devfn);
+
+	dev_info(pcie->dev,
+		 "found device %04x:%04x on bus %d (%s), slot %d (irq %d)\n",
+		 dev->vendor, dev->device, dev->bus->number, pcie->name,
+		 slot, of_irq_parse_and_map_pci(dev, slot, 1));
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, brcm_pcibios_fixup);
+
+static const struct of_device_id brcm_pci_match[] = {
+	{ .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
+	{ .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
+	{ .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
+	{ .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
+	{},
+};
+MODULE_DEVICE_TABLE(of, brcm_pci_match);
+
+static void _brcm_pcie_remove(struct brcm_pcie *pcie)
+{
+	turn_off(pcie);
+	clk_disable_unprepare(pcie->clk);
+	clk_put(pcie->clk);
+	set_regulators(pcie, false);
+	brcm_pcie_remove_controller(pcie);
+}
+
+static int brcm_pcie_probe(struct platform_device *pdev)
+{
+	struct device_node *dn = pdev->dev.of_node;
+	struct property *pp;
+	const struct of_device_id *of_id;
+	const struct pcie_cfg_data *data;
+	int ret;
+	struct brcm_pcie *pcie;
+	struct resource *res;
+	void __iomem *base;
+	u32 tmp;
+	struct brcm_dev_pwr_supply *supply;
+	struct pci_host_bridge *bridge;
+	struct pci_bus *child;
+	u32 domain;
+
+	bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
+	if (!bridge)
+		return -ENOMEM;
+
+	pcie = pci_host_bridge_priv(bridge);
+	INIT_LIST_HEAD(&pcie->resources);
+
+	of_id = of_match_node(brcm_pci_match, dn);
+	if (!of_id) {
+		pr_err("failed to look up compatible string\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32(dn, "dma-ranges", &tmp) == 0) {
+		pr_err("cannot yet handle dma-ranges\n");
+		return -EINVAL;
+	}
+
+	data = of_id->data;
+	pcie->reg_offsets = data->offsets;
+	pcie->reg_field_info = data->reg_field_info;
+	pcie->type = data->type;
+	pcie->dn = dn;
+	pcie->dev = &pdev->dev;
+
+	if (of_property_read_u32(dn, "linux,pci-domain", &domain) == 0) {
+		pcie->id = (int)domain;
+	} else {
+		dev_err(pcie->dev, "linux,pci-domain prop missing\n");
+		return -EINVAL;
+	}
+
+	INIT_LIST_HEAD(&pcie->pwr_supplies);
+	for_each_property_of_node(dn, pp) {
+		const int n = strlen(pp->name);
+
+		if (n < 7)
+			continue;
+		if (strncmp(pp->name + n - 7, "-supply", 7))
+			continue;
+		if (n > sizeof(supply->name) - 1) {
+			dev_err(&pdev->dev, "prop supply name %s too long\n",
+				pp->name);
+			continue;
+		}
+		supply = devm_kzalloc(&pdev->dev, sizeof(*supply), GFP_KERNEL);
+		if (!supply)
+			return -ENOMEM;
+		strcpy(supply->name, pp->name);
+		supply->name[n - 7] = 0; /* remove "-supply" */
+		supply->regulator = devm_regulator_get(&pdev->dev, supply->name);
+
+		if (IS_ERR(supply->regulator)) {
+			dev_err(&pdev->dev, "Unable to get %s, err=%d\n",
+				pp->name, (int)PTR_ERR(supply->regulator));
+			continue;
+		}
+		list_add_tail(&supply->node, &pcie->pwr_supplies);
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -EINVAL;
+
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
+	if (IS_ERR(pcie->clk)) {
+		dev_err(&pdev->dev, "could not get clock\n");
+		pcie->clk = NULL;
+	}
+	pcie->base = base;
+
+	ret = of_pci_get_max_link_speed(dn);
+	pcie->gen = (ret < 0) ? 0 : ret;
+
+	pcie->ssc = of_property_read_bool(dn, "brcm,ssc");
+
+	ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
+	if (ret == 0)
+		/* keep going, as we don't use this intr yet */
+		dev_warn(pcie->dev, "cannot get pcie interrupt\n");
+	else
+		pcie->irq = ret;
+
+	ret = brcm_parse_ranges(pcie);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(pcie->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "could not enable clock\n");
+		return ret;
+	}
+
+	ret = brcm_pcie_add_controller(pcie);
+	if (ret)
+		return ret;
+
+	set_regulators(pcie, true);
+	brcm_pcie_setup_prep(pcie);
+	ret = brcm_pcie_setup_bridge(pcie);
+	if (ret)
+		goto fail;
+
+	list_splice_init(&pcie->resources, &bridge->windows);
+	bridge->dev.parent = &pdev->dev;
+	bridge->busnr = 0;
+	bridge->ops = &brcm_pci_ops;
+	bridge->sysdata = pcie;
+	bridge->map_irq = of_irq_parse_and_map_pci;
+	bridge->swizzle_irq = pci_common_swizzle;
+
+	ret = pci_scan_root_bus_bridge(bridge);
+	if (ret < 0) {
+		dev_err(pcie->dev, "Scanning root bridge failed");
+		goto fail;
+	}
+
+	pci_assign_unassigned_bus_resources(bridge->bus);
+	list_for_each_entry(child, &bridge->bus->children, node)
+		pcie_bus_configure_settings(child);
+	pci_bus_add_devices(bridge->bus);
+	platform_set_drvdata(pdev, pcie);
+	pcie->root_bus = bridge->bus;
+
+	return 0;
+
+fail:
+	_brcm_pcie_remove(pcie);
+	return ret;
+}
+
+static int brcm_pcie_remove(struct platform_device *pdev)
+{
+	struct brcm_pcie *pcie = platform_get_drvdata(pdev);
+
+	pci_stop_root_bus(pcie->root_bus);
+	pci_remove_root_bus(pcie->root_bus);
+	_brcm_pcie_remove(pcie);
+
+	return 0;
+}
+
+static const struct dev_pm_ops brcm_pcie_pm_ops = {
+	.suspend_noirq = brcm_pcie_suspend,
+	.resume_noirq = brcm_pcie_resume,
+};
+
+static struct platform_driver __refdata brcm_pci_driver = {
+	.probe = brcm_pcie_probe,
+	.remove = brcm_pcie_remove,
+	.driver = {
+		.name = "brcm-pci",
+		.owner = THIS_MODULE,
+		.of_match_table = brcm_pci_match,
+		.pm = &brcm_pcie_pm_ops,
+	},
+};
+
+module_platform_driver(brcm_pci_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Broadcom STB PCIE RC driver");
+MODULE_AUTHOR("Broadcom");
diff --git a/drivers/pci/host/pci-brcmstb.h b/drivers/pci/host/pci-brcmstb.h
new file mode 100644
index 0000000..86f9cd1
--- /dev/null
+++ b/drivers/pci/host/pci-brcmstb.h
@@ -0,0 +1,33 @@
+#ifndef __BRCMSTB_PCI_H
+#define __BRCMSTB_PCI_H
+
+/*
+ * Copyright (C) 2015 - 2017 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define BRCM_PCIE_NAME_SIZE		8
+#define BRCM_INT_PCI_MSI_NR		32
+#define BRCM_PCIE_HW_REV_33		0x0303
+
+/* Broadcom PCIE Offsets */
+#define PCIE_INTR2_CPU_BASE		0x4300
+
+#if defined(CONFIG_MIPS)
+/* Broadcom MIPs HW implicitly does the swapping if necessary */
+#define bcm_readl(a)		__raw_readl(a)
+#define bcm_writel(d, a)	__raw_writel(d, a)
+#else
+#define bcm_readl(a)		readl(a)
+#define bcm_writel(d, a)	writel(d, a)
+#endif
+
+#endif /* __BRCMSTB_PCI_H */
-- 
1.9.0.138.g2de3478

Re: [PATCH 3/8] PCI: host: brcmstb: Broadcom PCIe Host Controller

[Bjorn Helgaas]

Run "git log --oneline drivers/pci/host" and make yours match, e.g.,

s/PCI: host: brcmstb: Broadcom PCIe Host Controller/
  PCI: brcmstb: Add Broadcom STB PCIe host controller driver/

On Tue, Oct 24, 2017 at 02:15:44PM -0400, Jim Quinlan wrote:
> This commit adds the basic Broadcom STB PCIe controller.  Missing is
> the ability to process MSI and also handle dma-ranges for inbound
> memory accesses.  These two functionalities are added in subsequent
> commits.
> 
> The PCIe block contains an MDIO interface.  This is a local interface
> only accessible by the PCIe controller.  It cannot be used or shared
> by any other HW.  As such, the small amount of code for this
> controller is included in this driver as there is little upside to put
> it elsewhere.
> 
> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> ---
>  drivers/pci/host/Kconfig       |    8 +
>  drivers/pci/host/Makefile      |    1 +
>  drivers/pci/host/pci-brcmstb.c | 1195 ++++++++++++++++++++++++++++++++++++++++

Name this pcie-brcmstb.c.  I used to have the idea we should name
things "pci-" unless they explicitly used some PCIe interfaces or
something, but I think that just made it confusing for PCIe
controllers like yours.

>  drivers/pci/host/pci-brcmstb.h |   33 ++

Unless you need this include file elsewhere, just fold its contents
into the .c file.

>  4 files changed, 1237 insertions(+)
>  create mode 100644 drivers/pci/host/pci-brcmstb.c
>  create mode 100644 drivers/pci/host/pci-brcmstb.h
> 
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index b868803..b9b4f11 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -220,4 +220,12 @@ config VMD
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called vmd.
>  
> +config PCI_BRCMSTB

PCIE_BRCMSTB

> +	tristate "Broadcom Brcmstb PCIe platform host driver"
> +	depends on ARCH_BRCMSTB || BMIPS_GENERIC
> +	depends on OF
> +	depends on SOC_BRCMSTB
> +	default ARCH_BRCMSTB || BMIPS_GENERIC
> +	help
> +	  Adds support for Broadcom Settop Box PCIe host controller.
>  endmenu
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index 1238278..4398d2c 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -21,6 +21,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
>  obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
>  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>  obj-$(CONFIG_VMD) += vmd.o
> +obj-$(CONFIG_PCI_BRCMSTB) += pci-brcmstb.o
>  
>  # The following drivers are for devices that use the generic ACPI
>  # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/host/pci-brcmstb.c b/drivers/pci/host/pci-brcmstb.c
> new file mode 100644
> index 0000000..883b435
> --- /dev/null
> +++ b/drivers/pci/host/pci-brcmstb.c
> @@ -0,0 +1,1195 @@
> +/*
> + * Copyright (C) 2009 - 2017 Broadcom
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +#include <linux/clk.h>
> +#include <linux/compiler.h>
> +#include <linux/delay.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> +#include <linux/irqdomain.h>
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/log2.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_platform.h>
> +#include <linux/pci.h>
> +#include <linux/printk.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/sizes.h>
> +#include <linux/slab.h>
> +#include <soc/brcmstb/memory_api.h>
> +#include <linux/string.h>
> +#include <linux/types.h>
> +#include "pci-brcmstb.h"
> +
> +/* Broadcom Settop Box PCIE Register Offsets.  */

s/PCIE/PCIe/ in comments and other English text throughout.

> +#define PCIE_RC_CFG_PCIE_LINK_CAPABILITY		0x00b8
> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL		0x00bc
> +#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL		0x00c8
> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2		0x00dc

Many of these look like they are describing the PCIe capability.  If
so, please define a Broadcom-specific base and use the already-defined
constants from include/uapi/linux/pci_regs.h, e.g., PCI_EXP_LNKCAP,
etc.

> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1		0x0188
> +#define PCIE_RC_CFG_PRIV1_ID_VAL3			0x043c
> +#define PCIE_RC_DL_MDIO_ADDR				0x1100
> +#define PCIE_RC_DL_MDIO_WR_DATA				0x1104
> +#define PCIE_RC_DL_MDIO_RD_DATA				0x1108
> +#define PCIE_MISC_MISC_CTRL				0x4008
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO		0x400c
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI		0x4010
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO			0x402c
> +#define PCIE_MISC_RC_BAR1_CONFIG_HI			0x4030
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO			0x4034
> +#define PCIE_MISC_RC_BAR2_CONFIG_HI			0x4038
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO			0x403c
> +#define PCIE_MISC_RC_BAR3_CONFIG_HI			0x4040
> +#define PCIE_MISC_PCIE_CTRL				0x4064
> +#define PCIE_MISC_PCIE_STATUS				0x4068
> +#define PCIE_MISC_REVISION				0x406c
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT	0x4070
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI		0x4080
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI		0x4084
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG			0x4204
> +
> +/* Broadcom Settop Box PCIE Register Field Shift, Mask Info.  */
> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_MASK  0x3f00000

Looks suspiciously like PCI_EXP_LNKSTA_NLW.

> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_SHIFT	0x14
> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_MASK	0xf0000
> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_SHIFT	0x10
> +#define PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_MASK		0xf
> +#define PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_SHIFT		0x0
> +#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK		0x10
> +#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_SHIFT		0x4
> +#define	PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_MASK	0xf
> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_SHIFT	0x0
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_MASK	0x3
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_SHIFT	0x0
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK	0xc
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT	0x2
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_MASK	0x30
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_SHIFT	0x4
> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK		0xffffff
> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT		0x0
> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK			0x1000
> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT			0xc
> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK		0x2000
> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT		0xd
> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK			0x300000
> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT		0x14
> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK			0xf8000000
> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT			0x1b
> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK			0x7c00000
> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT			0x16
> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK			0x1f
> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT			0x0
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_MASK		0xfffff000
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_SHIFT		0xc
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK			0x1f
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT			0x0
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_MASK		0xfffff000
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_SHIFT		0xc
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK			0x1f
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT			0x0
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_MASK		0xfffff000
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_SHIFT		0xc
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK			0x1f
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT			0x0
> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK			0x4
> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT			0x2
> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK		0x1
> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT		0x0
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK			0x80
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT			0x7
> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK		0x20
> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT		0x5
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK		0x10
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT		0x4
> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK		0x40
> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT		0x6
> +#define PCIE_MISC_REVISION_MAJMIN_MASK				0xffff
> +#define PCIE_MISC_REVISION_MAJMIN_SHIFT				0
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK	0xfff00000
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT	0x14
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK	0xfff0
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT	0x4
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS	0xc
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK		0xff
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT	0x0
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK	0xff
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT	0x0
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK	0x2
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK		0x08000000
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT	0x1b
> +#define PCIE_RGR1_SW_INIT_1_PERST_MASK				0x1
> +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT				0x0

Many of these definitions aren't used, and I'm dubious about the value
of including them all.

> +#define BRCM_NUM_PCI_OUT_WINS		0x4
> +#define BRCM_MAX_SCB			0x4
> +
> +#define BRCM_MSI_TARGET_ADDR_LT_4GB	0x0fffffffcULL
> +#define BRCM_MSI_TARGET_ADDR_GT_4GB	0xffffffffcULL
> +
> +#define BURST_SIZE_128			0
> +#define BURST_SIZE_256			1
> +#define BURST_SIZE_512			2
> +
> +/* Offsets from PCIE_INTR2_CPU_BASE */
> +#define STATUS				0x0
> +#define SET				0x4
> +#define CLR				0x8
> +#define MASK_STATUS			0xc
> +#define MASK_SET			0x10
> +#define MASK_CLR			0x14
> +
> +#define PCI_BUSNUM_SHIFT		20
> +#define PCI_SLOT_SHIFT			15
> +#define PCI_FUNC_SHIFT			12
> +
> +#if defined(__BIG_ENDIAN)
> +#define	DATA_ENDIAN		2	/* PCI->DDR inbound accesses */
> +#define MMIO_ENDIAN		2	/* CPU->PCI outbound accesses */
> +#else
> +#define	DATA_ENDIAN		0
> +#define MMIO_ENDIAN		0
> +#endif
> +
> +#define MDIO_PORT0		0x0
> +#define MDIO_DATA_MASK		0x7fffffff
> +#define MDIO_DATA_SHIFT		0x0
> +#define MDIO_PORT_MASK		0xf0000
> +#define MDIO_PORT_SHIFT		0x16
> +#define MDIO_REGAD_MASK		0xffff
> +#define MDIO_REGAD_SHIFT	0x0
> +#define MDIO_CMD_MASK		0xfff00000
> +#define MDIO_CMD_SHIFT		0x14
> +#define MDIO_CMD_READ		0x1
> +#define MDIO_CMD_WRITE		0x0
> +#define MDIO_DATA_DONE_MASK	0x80000000
> +#define MDIO_RD_DONE(x)		(((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
> +#define MDIO_WT_DONE(x)		(((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
> +#define SSC_REGS_ADDR		0x1100
> +#define SET_ADDR_OFFSET		0x1f
> +#define SSC_CNTL_OFFSET		0x2
> +#define SSC_CNTL_OVRD_EN_MASK	0x8000
> +#define SSC_CNTL_OVRD_EN_SHIFT	0xf
> +#define SSC_CNTL_OVRD_VAL_MASK	0x4000
> +#define SSC_CNTL_OVRD_VAL_SHIFT	0xe
> +#define SSC_STATUS_OFFSET	0x1
> +#define SSC_STATUS_SSC_MASK	0x400
> +#define SSC_STATUS_SSC_SHIFT	0xa
> +#define SSC_STATUS_PLL_LOCK_MASK	0x800
> +#define SSC_STATUS_PLL_LOCK_SHIFT	0xb
> +
> +#define IDX_ADDR(pcie)	\
> +	((pcie)->reg_offsets[EXT_CFG_INDEX])
> +#define DATA_ADDR(pcie)	\
> +	((pcie)->reg_offsets[EXT_CFG_DATA])
> +#define PCIE_RGR1_SW_INIT_1(pcie) \
> +	((pcie)->reg_offsets[RGR1_SW_INIT_1])
> +
> +enum {
> +	RGR1_SW_INIT_1,
> +	EXT_CFG_INDEX,
> +	EXT_CFG_DATA,
> +};
> +
> +enum {
> +	RGR1_SW_INIT_1_INIT_MASK,
> +	RGR1_SW_INIT_1_INIT_SHIFT,
> +	RGR1_SW_INIT_1_PERST_MASK,
> +	RGR1_SW_INIT_1_PERST_SHIFT,
> +};
> +
> +enum pcie_type {
> +	BCM7425,
> +	BCM7435,
> +	GENERIC,
> +	BCM7278,
> +};
> +
> +#define RD_FLD(base, reg, field) \
> +	rd_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
> +#define WR_FLD(base, reg, field, val) \
> +	wr_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
> +#define WR_FLD_RB(base, reg, field, val) \
> +	wr_fld_rb(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
> +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
> +	wr_fld(base + reg + off, reg##_##field##_MASK, \
> +	       reg##_##field##_SHIFT, val)
> +#define EXTRACT_FIELD(val, reg, field) \
> +	((val & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
> +#define INSERT_FIELD(val, reg, field, field_val) \
> +	((val & ~reg##_##field##_MASK) | \
> +	 (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
> +
> +struct pcie_cfg_data {
> +	const int *reg_field_info;
> +	const int *offsets;
> +	const enum pcie_type type;
> +};
> +
> +static const int pcie_reg_field_info[] = {
> +	[RGR1_SW_INIT_1_INIT_MASK] = 0x2,
> +	[RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
> +};
> +
> +static const int pcie_reg_field_info_bcm7278[] = {
> +	[RGR1_SW_INIT_1_INIT_MASK] = 0x1,
> +	[RGR1_SW_INIT_1_INIT_SHIFT] = 0x0,
> +};
> +
> +static const int pcie_offset_bcm7425[] = {
> +	[RGR1_SW_INIT_1] = 0x8010,
> +	[EXT_CFG_INDEX]  = 0x8300,
> +	[EXT_CFG_DATA]   = 0x8304,
> +};
> +
> +static const struct pcie_cfg_data bcm7425_cfg = {
> +	.reg_field_info	= pcie_reg_field_info,
> +	.offsets	= pcie_offset_bcm7425,
> +	.type		= BCM7425,
> +};
> +
> +static const int pcie_offsets[] = {
> +	[RGR1_SW_INIT_1] = 0x9210,
> +	[EXT_CFG_INDEX]  = 0x9000,
> +	[EXT_CFG_DATA]   = 0x9004,
> +};
> +
> +static const struct pcie_cfg_data bcm7435_cfg = {
> +	.reg_field_info	= pcie_reg_field_info,
> +	.offsets	= pcie_offsets,
> +	.type		= BCM7435,
> +};
> +
> +static const struct pcie_cfg_data generic_cfg = {
> +	.reg_field_info	= pcie_reg_field_info,
> +	.offsets	= pcie_offsets,
> +	.type		= GENERIC,
> +};
> +
> +static const int pcie_offset_bcm7278[] = {
> +	[RGR1_SW_INIT_1] = 0xc010,
> +	[EXT_CFG_INDEX] = 0x9000,
> +	[EXT_CFG_DATA] = 0x9004,
> +};
> +
> +static const struct pcie_cfg_data bcm7278_cfg = {
> +	.reg_field_info = pcie_reg_field_info_bcm7278,
> +	.offsets	= pcie_offset_bcm7278,
> +	.type		= BCM7278,
> +};
> +
> +static void __iomem *brcm_pci_map_cfg(struct pci_bus *bus, unsigned int devfn,
> +				      int where);
> +
> +static struct pci_ops brcm_pci_ops = {
> +	.map_bus = brcm_pci_map_cfg,
> +	.read = pci_generic_config_read32,
> +	.write = pci_generic_config_write32,

Ouch, does your hardware really not support 8- and 16-bit config
accesses?  As you probably know, that can lead to config space
corruption with devices that have RW1C bits in registers.

> +};
> +
> +struct brcm_dev_pwr_supply {
> +	struct list_head node;
> +	char name[32];
> +	struct regulator *regulator;
> +};
> +
> +struct brcm_window {
> +	dma_addr_t pci_addr;
> +	phys_addr_t cpu_addr;
> +	dma_addr_t size;
> +};
> +
> +/* Internal Bus Controller Information.*/
> +struct brcm_pcie {
> +	struct list_head	list;
> +	void __iomem		*base;
> +	char			name[BRCM_PCIE_NAME_SIZE];
> +	bool			suspended;
> +	struct clk		*clk;
> +	struct device_node	*dn;
> +	int			irq;
> +	int			num_out_wins;
> +	bool			ssc;
> +	int			gen;
> +	struct brcm_window	out_wins[BRCM_NUM_PCI_OUT_WINS];
> +	struct list_head	resources;
> +	struct device		*dev;
> +	struct list_head	pwr_supplies;
> +	unsigned int		rev;
> +	unsigned int		num;
> +	bool			bridge_setup_done;

Nobody else needs a "bridge_setup_done" variable; I'm skeptical that
you do.  Please use similar style to other drivers whenever possible.

> +	const int		*reg_offsets;
> +	const int		*reg_field_info;
> +	enum pcie_type		type;
> +	struct pci_bus		*root_bus;
> +	int			id;

Please reorder with more generic info at the top, e.g., "* dev",
"*base", "resources", etc., should be near the top, as other drivers
do.

> +};
> +
> +static struct list_head brcm_pcie = LIST_HEAD_INIT(brcm_pcie);

Do you really need a list of controllers?  It looks like this is only
used for remove.  If you get rid of the list, you probably don't need
brcm_pcie_lock either.

> +static phys_addr_t scb_size[BRCM_MAX_SCB];
> +static int num_memc;
> +static DEFINE_MUTEX(brcm_pcie_lock);
> +
> +/*
> + * The roundup_pow_of_two() from log2.h invokes
> + * __roundup_pow_of_two(unsigned long), but we really need a
> + * such a function to take a native u64 since unsigned long
> + * is 32 bits on some configurations.  So we provide this helper
> + * function below.
> + */
> +static u64 roundup_pow_of_two_64(u64 n)
> +{
> +	return 1ULL << fls64(n - 1);
> +}
> +
> +static int brcm_pcie_add_controller(struct brcm_pcie *pcie)
> +{
> +	mutex_lock(&brcm_pcie_lock);
> +	snprintf(pcie->name, sizeof(pcie->name) - 1, "PCIe%d", pcie->id);
> +	list_add_tail(&pcie->list, &brcm_pcie);
> +	mutex_unlock(&brcm_pcie_lock);
> +
> +	return 0;
> +}
> +
> +static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
> +{
> +	struct list_head *pos, *q;
> +	struct brcm_pcie *tmp;
> +
> +	mutex_lock(&brcm_pcie_lock);
> +	list_for_each_safe(pos, q, &brcm_pcie) {
> +		tmp = list_entry(pos, struct brcm_pcie, list);
> +		if (tmp == pcie) {
> +			list_del(pos);
> +			if (list_empty(&brcm_pcie))
> +				num_memc = 0;
> +			break;
> +		}
> +	}
> +	mutex_unlock(&brcm_pcie_lock);
> +}
> +
> +/* This is to convert the size of the inbound bar region to the
> + * non-liniear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE

Please use conventional comment style for multi-line comments, i.e.,

  /*
   * text ...
   */

> + */
> +int encode_ibar_size(u64 size)
> +{
> +	int log2_in = ilog2(size);
> +
> +	if (log2_in >= 12 && log2_in <= 15)
> +		/* Covers 4KB to 32KB (inclusive) */
> +		return (log2_in - 12) + 0x1c;
> +	else if (log2_in >= 16 && log2_in <= 37)
> +		/* Covers 64KB to 32GB, (inclusive) */
> +		return log2_in - 15;
> +	/* Something is awry so disable */
> +	return 0;
> +}
> +
> +static u32 mdio_form_pkt(int port, int regad, int cmd)
> +{
> +	u32 pkt = 0;
> +
> +	pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
> +	pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
> +	pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
> +
> +	return pkt;
> +}
> +
> +/* negative return value indicates error */
> +static int mdio_read(void __iomem *base, u8 port, u8 regad)
> +{
> +	int tries;
> +	u32 data;
> +
> +	bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
> +		   base + PCIE_RC_DL_MDIO_ADDR);
> +	bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> +
> +	data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> +	for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
> +		udelay(10);
> +		data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> +	}
> +
> +	return MDIO_RD_DONE(data)
> +		? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
> +		: -EIO;
> +}
> +
> +/* negative return value indicates error */
> +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
> +{
> +	int tries;
> +	u32 data;
> +
> +	bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
> +		   base + PCIE_RC_DL_MDIO_ADDR);
> +	bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> +	bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
> +		   base + PCIE_RC_DL_MDIO_WR_DATA);
> +
> +	data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> +	for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
> +		udelay(10);
> +		data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> +	}
> +
> +	return MDIO_WT_DONE(data) ? 0 : -EIO;
> +}
> +
> +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
> +{
> +	return (bcm_readl(p) & mask) >> shift;
> +}
> +
> +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
> +{
> +	u32 reg = bcm_readl(p);
> +
> +	reg = (reg & ~mask) | ((val << shift) & mask);
> +	bcm_writel(reg, p);
> +}
> +
> +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
> +{
> +	wr_fld(p, mask, shift, val);
> +	(void)bcm_readl(p);
> +}
> +
> +/* configures device for ssc mode; negative return value indicates error */
> +static int set_ssc(void __iomem *base)
> +{
> +	int tmp;
> +	u16 wrdata;
> +	int pll, ssc;
> +
> +	tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
> +	if (tmp < 0)
> +		return tmp;
> +
> +	tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
> +	if (tmp < 0)
> +		return tmp;
> +
> +	wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
> +	wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
> +	tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
> +	if (tmp < 0)
> +		return tmp;
> +
> +	usleep_range(1000, 2000);
> +	tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
> +	if (tmp < 0)
> +		return tmp;
> +
> +	ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
> +	pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
> +
> +	return (ssc && pll) ? 0 : -EIO;
> +}
> +
> +/* limits operation to a specific generation (1, 2, or 3) */
> +static void set_gen(void __iomem *base, int gen)
> +{
> +	WR_FLD(base, PCIE_RC_CFG_PCIE_LINK_CAPABILITY, MAX_LINK_SPEED, gen);
> +	WR_FLD(base, PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2,
> +	       TARGET_LINK_SPEED, gen);
> +}
> +
> +static void set_pcie_outbound_win(struct brcm_pcie *pcie, unsigned int win,
> +				  phys_addr_t cpu_addr, dma_addr_t  pci_addr,
> +				  dma_addr_t size)
> +{
> +	void __iomem *base = pcie->base;
> +	phys_addr_t cpu_addr_mb, limit_addr_mb;
> +	u32 tmp;
> +
> +	/* Set the base of the pci_addr window */
> +	bcm_writel(lower_32_bits(pci_addr) + MMIO_ENDIAN,
> +		   base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
> +	bcm_writel(upper_32_bits(pci_addr),
> +		   base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
> +
> +	cpu_addr_mb = cpu_addr >> 20;
> +	limit_addr_mb = (cpu_addr + size - 1) >> 20;
> +
> +	/* Write the addr base low register */
> +	WR_FLD_WITH_OFFSET(base, (win * 4),
> +			   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> +			   BASE, cpu_addr_mb);
> +	/* Write the addr limit low register */
> +	WR_FLD_WITH_OFFSET(base, (win * 4),
> +			   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> +			   LIMIT, limit_addr_mb);
> +
> +	if (pcie->type != BCM7435 && pcie->type != BCM7425) {
> +		/* Write the cpu addr high register */
> +		tmp = (u32)(cpu_addr_mb >>
> +			PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> +		WR_FLD_WITH_OFFSET(base, (win * 8),
> +				   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
> +				   BASE, tmp);
> +		/* Write the cpu limit high register */
> +		tmp = (u32)(limit_addr_mb >>
> +			PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> +		WR_FLD_WITH_OFFSET(base, (win * 8),
> +				   PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
> +				   LIMIT, tmp);
> +	}
> +}
> +
> +static int is_pcie_link_up(struct brcm_pcie *pcie, bool silent)

Please use function names similar to other drivers, e.g.,
brcm_pcie_link_up() in this case.

> +{
> +	void __iomem *base = pcie->base;
> +	u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> +	u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
> +	u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
> +	u32 rc = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
> +
> +	if (!rc && !silent)
> +		dev_err(pcie->dev, "controller configured in EP mode\n");
> +
> +	return  (rc && dla && plu) ? 1 : 0;
> +}
> +
> +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
> +						unsigned int val)
> +{
> +	unsigned int offset;
> +	unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
> +	u32 mask =  pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
> +
> +	if (pcie->type != BCM7278) {
> +		wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
> +			  val);
> +	} else if (of_machine_is_compatible("brcm,bcm7278a0")) {
> +		/* The two PCIE instance on 7278a0 are not even consistent with
> +		 * respect to each other for internal offsets, here we offset
> +		 * by 0x14000 + RGR1_SW_INIT_1's relative offset to account for
> +		 * that.
> +		 */
> +		offset = pcie->id ? 0x14010 : pcie->reg_offsets[RGR1_SW_INIT_1];
> +		wr_fld_rb(pcie->base + offset, mask, shift, val);
> +	} else {
> +		wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
> +			  val);
> +	}
> +}
> +
> +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
> +				       unsigned int val)
> +{
> +	if (pcie->type != BCM7278)
> +		wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
> +			  PCIE_RGR1_SW_INIT_1_PERST_MASK,
> +			  PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
> +	else
> +		/* Assert = 0, de-assert = 1 on 7278 */
> +		WR_FLD_RB(pcie->base, PCIE_MISC_PCIE_CTRL, PCIE_PERSTB, !val);
> +}
> +
> +static int brcm_parse_ranges(struct brcm_pcie *pcie)
> +{
> +	struct resource_entry *win;
> +	int ret;
> +
> +	ret = of_pci_get_host_bridge_resources(pcie->dn, 0, 0xff,
> +					       &pcie->resources, NULL);
> +	if (ret) {
> +		dev_err(pcie->dev, "failed to get host resources\n");
> +		return ret;
> +	}
> +
> +	resource_list_for_each_entry(win, &pcie->resources) {
> +		struct resource *parent, *res = win->res;
> +		dma_addr_t offset = (dma_addr_t)win->offset;
> +
> +		if (resource_type(res) == IORESOURCE_IO) {
> +			parent = &ioport_resource;
> +		} else if (resource_type(res) == IORESOURCE_MEM) {
> +			if (pcie->num_out_wins >= BRCM_NUM_PCI_OUT_WINS) {
> +				dev_err(pcie->dev, "too many outbound wins\n");
> +				return -EINVAL;
> +			}
> +			pcie->out_wins[pcie->num_out_wins].cpu_addr
> +				= (phys_addr_t)res->start;
> +			pcie->out_wins[pcie->num_out_wins].pci_addr
> +				= (dma_addr_t)(res->start
> +					       - (phys_addr_t)offset);
> +			pcie->out_wins[pcie->num_out_wins].size
> +				= (dma_addr_t)(res->end - res->start + 1);
> +			pcie->num_out_wins++;
> +			parent = &iomem_resource;
> +		} else {
> +			continue;
> +		}
> +
> +		ret = devm_request_resource(pcie->dev, parent, res);
> +		if (ret) {
> +			dev_err(pcie->dev, "failed to get res %pR\n", res);
> +			return ret;
> +		}
> +	}
> +	return 0;
> +}
> +
> +static void set_regulators(struct brcm_pcie *pcie, bool on)
> +{
> +	struct list_head *pos;
> +
> +	list_for_each(pos, &pcie->pwr_supplies) {
> +		struct brcm_dev_pwr_supply *supply
> +			= list_entry(pos, struct brcm_dev_pwr_supply, node);
> +
> +		if (on && regulator_enable(supply->regulator))
> +			pr_debug("Unable to turn on %s supply.\n",
> +				 supply->name);
> +		else if (!on && regulator_disable(supply->regulator))
> +			pr_debug("Unable to turn off %s supply.\n",
> +				 supply->name);
> +	}
> +}
> +
> +static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
> +{
> +	void __iomem *base = pcie->base;
> +	unsigned int scb_size_val;
> +	u64 rc_bar2_size = 0, rc_bar2_offset = 0, total_mem_size = 0;
> +	u32 tmp, burst;
> +	int i;
> +
> +	/* reset the bridge and the endpoint device */
> +	/* field: PCIE_BRIDGE_SW_INIT = 1 */
> +	brcm_pcie_bridge_sw_init_set(pcie, 1);
> +
> +	/* field: PCIE_SW_PERST = 1, on 7278, we start de-asserted already */
> +	if (pcie->type != BCM7278)
> +		brcm_pcie_perst_set(pcie, 1);
> +
> +	usleep_range(100, 200);
> +
> +	/* take the bridge out of reset */
> +	/* field: PCIE_BRIDGE_SW_INIT = 0 */
> +	brcm_pcie_bridge_sw_init_set(pcie, 0);
> +
> +	WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> +	/* wait for serdes to be stable */
> +	usleep_range(100, 200);
> +
> +	/* Grab the PCIe hw revision number */
> +	tmp = bcm_readl(base + PCIE_MISC_REVISION);
> +	pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
> +
> +	/* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
> +	tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
> +	tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
> +	burst = (pcie->type == GENERIC || pcie->type == BCM7278)
> +		? BURST_SIZE_512 : BURST_SIZE_256;
> +	tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE, burst);
> +	bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
> +
> +	/* Set up inbound memory view for the EP (called RC_BAR2,
> +	 * not to be confused with the BARs that are advertised by
> +	 * the EP).

Multi-line comment style here and below.

> +	 */
> +	for (i = 0; i < num_memc; i++)
> +		total_mem_size += scb_size[i];
> +
> +	/* The PCI host controller by design must set the inbound
> +	 * viewport to be a contiguous arrangement of all of the
> +	 * system's memory.  In addition, its size mut be a power of
> +	 * two.  To further complicate matters, the viewport must
> +	 * start on a pci-address that is aligned on a multiple of its
> +	 * size.  If a portion of the viewport does not represent
> +	 * system memory -- e.g. 3GB of memory requires a 4GB viewport
> +	 * -- we can map the outbound memory in or after 3GB and even
> +	 * though the viewport will overlap the outbound memory the
> +	 * controller will know to send outbound memory downstream and
> +	 * everything else upstream.
> +	 */
> +	rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
> +
> +	/* Set simple configuration based on memory sizes
> +	 * only.  We always start the viewport at address 0.
> +	 */
> +	rc_bar2_offset = 0;
> +
> +	tmp = lower_32_bits(rc_bar2_offset);
> +	tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> +			   encode_ibar_size(rc_bar2_size));
> +	bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
> +	bcm_writel(upper_32_bits(rc_bar2_offset),
> +		   base + PCIE_MISC_RC_BAR2_CONFIG_HI);
> +
> +	/* field: SCB0_SIZE, default = 0xf (1 GB) */
> +	scb_size_val = scb_size[0]
> +		? ilog2(scb_size[0]) - 15 : 0xf;
> +	WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
> +
> +	/* field: SCB1_SIZE, default = 0xf (1 GB) */
> +	if (num_memc > 1) {
> +		scb_size_val = scb_size[1]
> +			? ilog2(scb_size[1]) - 15 : 0xf;
> +		WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB1_SIZE, scb_size_val);
> +	}
> +
> +	/* field: SCB2_SIZE, default = 0xf (1 GB) */
> +	if (num_memc > 2) {
> +		scb_size_val = scb_size[2]
> +			? ilog2(scb_size[2]) - 15 : 0xf;
> +		WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB2_SIZE, scb_size_val);
> +	}
> +
> +	/* disable the PCIE->GISB memory window (RC_BAR1) */
> +	WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
> +
> +	/* disable the PCIE->SCB memory window (RC_BAR3) */
> +	WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
> +
> +	if (!pcie->suspended) {
> +		/* clear any interrupts we find on boot */
> +		bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
> +		(void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
> +	}
> +
> +	/* Mask all interrupts since we are not handling any yet */
> +	bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
> +	(void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
> +
> +	if (pcie->gen)
> +		set_gen(base, pcie->gen);
> +
> +	/* take the EP device out of reset */
> +	/* field: PCIE_SW_PERST = 0 */
> +	brcm_pcie_perst_set(pcie, 0);
> +}
> +
> +static const char *link_speed_to_str(int s)
> +{
> +	switch (s) {
> +	case 1:
> +		return "2.5";
> +	case 2:
> +		return "5.0";
> +	case 3:
> +		return "8.0";
> +	default:
> +		break;
> +	}
> +	return "???";
> +}
> +
> +static int brcm_pcie_setup_bridge(struct brcm_pcie *pcie)
> +{
> +	void __iomem *base = pcie->base;
> +	const int limit = pcie->suspended ? 1000 : 100;
> +	unsigned int status;
> +	int i, j, ret;
> +	u32 neg_width, neg_speed;
> +	bool ssc_good = false;
> +
> +	/* Give the RC/EP time to wake up, before trying to configure RC.
> +	 * Intermittently check status for link-up, up to a total of 100ms
> +	 * when we don't know if the device is there, and up to 1000ms if
> +	 * we do know the device is there.
> +	 */
> +	for (i = 1, j = 0; j < limit && !is_pcie_link_up(pcie, true);
> +	     j += i, i = i * 2)
> +		msleep(i + j > limit ? limit - j : i);
> +
> +	if (!is_pcie_link_up(pcie, false)) {
> +		dev_info(pcie->dev, "link down\n");
> +		return -ENODEV;
> +	}
> +
> +	for (i = 0; i < pcie->num_out_wins; i++)
> +		set_pcie_outbound_win(pcie, i, pcie->out_wins[i].cpu_addr,
> +				      pcie->out_wins[i].pci_addr,
> +				      pcie->out_wins[i].size);
> +
> +	/* For config space accesses on the RC, show the right class for
> +	 * a PCI-PCI bridge
> +	 */
> +	WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
> +
> +	if (pcie->ssc) {
> +		ret = set_ssc(base);
> +		if (ret == 0)
> +			ssc_good = true;
> +		else
> +			dev_err(pcie->dev,
> +				"failed attempt to enter ssc mode\n");
> +	}
> +
> +	status = bcm_readl(base + PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL);
> +	neg_width = EXTRACT_FIELD(status, PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL,
> +				  NEG_LINK_WIDTH);
> +	neg_speed = EXTRACT_FIELD(status, PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL,
> +				  NEG_LINK_SPEED);
> +	dev_info(pcie->dev, "link up, %s Gbps x%u %s\n",
> +		 link_speed_to_str(neg_speed), neg_width,
> +		 ssc_good ? "(SSC)" : "(!SSC)");
> +
> +	/* Enable configuration request retry (see pci_scan_device()) */
> +	/* field RC_CRS_EN = 1 */
> +	WR_FLD(base, PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL, RC_CRS_EN, 1);

As long as you advertise CRS SV support, the PCI core should be
enabling it automatically; why do you need this here?

> +
> +	/* PCIE->SCB endian mode for BAR */
> +	/* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
> +	WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
> +		  ENDIAN_MODE_BAR2, DATA_ENDIAN);
> +
> +	/* Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
> +	 * is enabled =>  setting the CLKREQ_DEBUG_ENABLE field to 1.
> +	 */
> +	WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
> +
> +	pcie->bridge_setup_done = true;
> +
> +	return 0;
> +}
> +
> +static void enter_l23(struct brcm_pcie *pcie)
> +{
> +	void __iomem *base = pcie->base;
> +	int tries, l23;
> +
> +	/* assert request for L23 */
> +	WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
> +	/* poll L23 status */
> +	for (tries = 0, l23 = 0; tries < 1000 && !l23; tries++)
> +		l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> +	if (!l23)
> +		dev_err(pcie->dev, "failed to enter L23\n");
> +}
> +
> +static void turn_off(struct brcm_pcie *pcie)
> +{
> +	void __iomem *base = pcie->base;
> +
> +	if (is_pcie_link_up(pcie, true))
> +		enter_l23(pcie);
> +	/* Reset endpoint device */
> +	brcm_pcie_perst_set(pcie, 1);
> +	/* deassert request for L23 in case it was asserted */
> +	WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
> +	/* SERDES_IDDQ = 1 */
> +	WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
> +	/* Shutdown PCIe bridge */
> +	brcm_pcie_bridge_sw_init_set(pcie, 1);
> +}
> +
> +static int brcm_pcie_suspend(struct device *dev)
> +{
> +	struct brcm_pcie *pcie = dev_get_drvdata(dev);
> +
> +	if (!pcie->bridge_setup_done)
> +		return 0;
> +
> +	turn_off(pcie);
> +	clk_disable_unprepare(pcie->clk);
> +	set_regulators(pcie, false);
> +	pcie->suspended = true;
> +
> +	return 0;
> +}
> +
> +static int brcm_pcie_resume(struct device *dev)
> +{
> +	struct brcm_pcie *pcie = dev_get_drvdata(dev);
> +	void __iomem *base;
> +	int ret;
> +
> +	if (!pcie->bridge_setup_done)
> +		return 0;
> +
> +	base = pcie->base;
> +	set_regulators(pcie, true);
> +	clk_prepare_enable(pcie->clk);
> +
> +	/* Take bridge out of reset so we can access the SERDES reg */
> +	brcm_pcie_bridge_sw_init_set(pcie, 0);
> +
> +	/* SERDES_IDDQ = 0 */
> +	WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> +	/* wait for serdes to be stable */
> +	usleep_range(100, 200);
> +
> +	brcm_pcie_setup_prep(pcie);
> +
> +	ret = brcm_pcie_setup_bridge(pcie);
> +	if (ret)
> +		return ret;
> +
> +	pcie->suspended = false;
> +
> +	return 0;
> +}
> +
> +/* Configuration space read/write support */
> +static int cfg_index(int busnr, int devfn, int reg)
> +{
> +	return ((PCI_SLOT(devfn) & 0x1f) << PCI_SLOT_SHIFT)
> +		| ((PCI_FUNC(devfn) & 0x07) << PCI_FUNC_SHIFT)
> +		| (busnr << PCI_BUSNUM_SHIFT)
> +		| (reg & ~3);
> +}
> +
> +static void __iomem *brcm_pci_map_cfg(struct pci_bus *bus, unsigned int devfn,
> +				      int where)
> +{
> +	struct brcm_pcie *pcie = bus->sysdata;
> +	void __iomem *base = pcie->base;
> +	bool rc_access = pci_is_root_bus(bus);
> +	int idx;
> +
> +	if (!is_pcie_link_up(pcie, true))
> +		return NULL;

Why do you need this test?  It makes this racy because the link could
go down after you call is_pcie_link_up() but before you perform the
config access.

> +	base = pcie->base;
> +	idx = cfg_index(bus->number, devfn, where);
> +
> +	bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
> +
> +	if (rc_access) {
> +		if (PCI_SLOT(devfn))
> +			return NULL;
> +		return base + (where & ~3);
> +	}

Many drivers have a similar pattern.  Please implement this in a
similar way, e.g., see dw_pcie_valid_device(),
altera_pcie_valid_device(), rockchip_pcie_valid_device(), etc.

> +	return pcie->base + DATA_ADDR(pcie);
> +}
> +
> +static void __attribute__((__section__("pci_fixup_early")))
> +brcm_pcibios_fixup(struct pci_dev *dev)
> +{
> +	struct brcm_pcie *pcie = dev->bus->sysdata;
> +	u8 slot = PCI_SLOT(dev->devfn);
> +
> +	dev_info(pcie->dev,
> +		 "found device %04x:%04x on bus %d (%s), slot %d (irq %d)\n",
> +		 dev->vendor, dev->device, dev->bus->number, pcie->name,
> +		 slot, of_irq_parse_and_map_pci(dev, slot, 1));
> +}
> +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, brcm_pcibios_fixup);

This looks like debug code that should be removed.

> +
> +static const struct of_device_id brcm_pci_match[] = {
> +	{ .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
> +	{ .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
> +	{ .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
> +	{ .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, brcm_pci_match);
> +
> +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
> +{
> +	turn_off(pcie);
> +	clk_disable_unprepare(pcie->clk);
> +	clk_put(pcie->clk);
> +	set_regulators(pcie, false);
> +	brcm_pcie_remove_controller(pcie);
> +}
> +
> +static int brcm_pcie_probe(struct platform_device *pdev)
> +{
> +	struct device_node *dn = pdev->dev.of_node;
> +	struct property *pp;
> +	const struct of_device_id *of_id;
> +	const struct pcie_cfg_data *data;
> +	int ret;
> +	struct brcm_pcie *pcie;
> +	struct resource *res;
> +	void __iomem *base;
> +	u32 tmp;
> +	struct brcm_dev_pwr_supply *supply;
> +	struct pci_host_bridge *bridge;
> +	struct pci_bus *child;
> +	u32 domain;
> +
> +	bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
> +	if (!bridge)
> +		return -ENOMEM;
> +
> +	pcie = pci_host_bridge_priv(bridge);
> +	INIT_LIST_HEAD(&pcie->resources);
> +
> +	of_id = of_match_node(brcm_pci_match, dn);
> +	if (!of_id) {
> +		pr_err("failed to look up compatible string\n");

Please use dev_err(), etc. for every single log message so we can
associate log messages with a device.

> +		return -EINVAL;
> +	}
> +
> +	if (of_property_read_u32(dn, "dma-ranges", &tmp) == 0) {
> +		pr_err("cannot yet handle dma-ranges\n");
> +		return -EINVAL;
> +	}
> +
> +	data = of_id->data;
> +	pcie->reg_offsets = data->offsets;
> +	pcie->reg_field_info = data->reg_field_info;
> +	pcie->type = data->type;
> +	pcie->dn = dn;
> +	pcie->dev = &pdev->dev;
> +
> +	if (of_property_read_u32(dn, "linux,pci-domain", &domain) == 0) {
> +		pcie->id = (int)domain;
> +	} else {
> +		dev_err(pcie->dev, "linux,pci-domain prop missing\n");
> +		return -EINVAL;
> +	}

You should not need this.  This should happen automatically via
of_get_pci_domain_nr() if you have things set up correctly.

> +
> +	INIT_LIST_HEAD(&pcie->pwr_supplies);
> +	for_each_property_of_node(dn, pp) {
> +		const int n = strlen(pp->name);
> +
> +		if (n < 7)
> +			continue;
> +		if (strncmp(pp->name + n - 7, "-supply", 7))
> +			continue;
> +		if (n > sizeof(supply->name) - 1) {
> +			dev_err(&pdev->dev, "prop supply name %s too long\n",
> +				pp->name);
> +			continue;
> +		}
> +		supply = devm_kzalloc(&pdev->dev, sizeof(*supply), GFP_KERNEL);
> +		if (!supply)
> +			return -ENOMEM;
> +		strcpy(supply->name, pp->name);
> +		supply->name[n - 7] = 0; /* remove "-supply" */
> +		supply->regulator = devm_regulator_get(&pdev->dev, supply->name);
> +
> +		if (IS_ERR(supply->regulator)) {
> +			dev_err(&pdev->dev, "Unable to get %s, err=%d\n",
> +				pp->name, (int)PTR_ERR(supply->regulator));
> +			continue;
> +		}
> +		list_add_tail(&supply->node, &pcie->pwr_supplies);
> +	}
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res)
> +		return -EINVAL;
> +
> +	base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(base))
> +		return PTR_ERR(base);
> +
> +	pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
> +	if (IS_ERR(pcie->clk)) {
> +		dev_err(&pdev->dev, "could not get clock\n");
> +		pcie->clk = NULL;
> +	}
> +	pcie->base = base;
> +
> +	ret = of_pci_get_max_link_speed(dn);
> +	pcie->gen = (ret < 0) ? 0 : ret;
> +
> +	pcie->ssc = of_property_read_bool(dn, "brcm,ssc");
> +
> +	ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
> +	if (ret == 0)
> +		/* keep going, as we don't use this intr yet */
> +		dev_warn(pcie->dev, "cannot get pcie interrupt\n");
> +	else
> +		pcie->irq = ret;
> +
> +	ret = brcm_parse_ranges(pcie);
> +	if (ret)
> +		return ret;
> +
> +	ret = clk_prepare_enable(pcie->clk);
> +	if (ret) {
> +		dev_err(&pdev->dev, "could not enable clock\n");
> +		return ret;
> +	}
> +
> +	ret = brcm_pcie_add_controller(pcie);
> +	if (ret)
> +		return ret;
> +
> +	set_regulators(pcie, true);
> +	brcm_pcie_setup_prep(pcie);
> +	ret = brcm_pcie_setup_bridge(pcie);
> +	if (ret)
> +		goto fail;
> +
> +	list_splice_init(&pcie->resources, &bridge->windows);
> +	bridge->dev.parent = &pdev->dev;
> +	bridge->busnr = 0;
> +	bridge->ops = &brcm_pci_ops;
> +	bridge->sysdata = pcie;
> +	bridge->map_irq = of_irq_parse_and_map_pci;
> +	bridge->swizzle_irq = pci_common_swizzle;
> +
> +	ret = pci_scan_root_bus_bridge(bridge);
> +	if (ret < 0) {
> +		dev_err(pcie->dev, "Scanning root bridge failed");
> +		goto fail;
> +	}
> +
> +	pci_assign_unassigned_bus_resources(bridge->bus);
> +	list_for_each_entry(child, &bridge->bus->children, node)
> +		pcie_bus_configure_settings(child);
> +	pci_bus_add_devices(bridge->bus);
> +	platform_set_drvdata(pdev, pcie);
> +	pcie->root_bus = bridge->bus;

General comment, can you scan some of the other drivers in
drivers/pci/host/ and follow a similar style?  Similar structure,
similar function names, similar variable names, etc.  It makes it much
easier to maintain this whole collection.

> +	return 0;
> +
> +fail:
> +	_brcm_pcie_remove(pcie);
> +	return ret;
> +}
> +
> +static int brcm_pcie_remove(struct platform_device *pdev)
> +{
> +	struct brcm_pcie *pcie = platform_get_drvdata(pdev);
> +
> +	pci_stop_root_bus(pcie->root_bus);
> +	pci_remove_root_bus(pcie->root_bus);
> +	_brcm_pcie_remove(pcie);
> +
> +	return 0;
> +}
> +
> +static const struct dev_pm_ops brcm_pcie_pm_ops = {
> +	.suspend_noirq = brcm_pcie_suspend,
> +	.resume_noirq = brcm_pcie_resume,
> +};
> +
> +static struct platform_driver __refdata brcm_pci_driver = {
> +	.probe = brcm_pcie_probe,
> +	.remove = brcm_pcie_remove,
> +	.driver = {
> +		.name = "brcm-pci",
> +		.owner = THIS_MODULE,
> +		.of_match_table = brcm_pci_match,
> +		.pm = &brcm_pcie_pm_ops,
> +	},
> +};
> +
> +module_platform_driver(brcm_pci_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("Broadcom STB PCIE RC driver");
> +MODULE_AUTHOR("Broadcom");
> diff --git a/drivers/pci/host/pci-brcmstb.h b/drivers/pci/host/pci-brcmstb.h
> new file mode 100644
> index 0000000..86f9cd1
> --- /dev/null
> +++ b/drivers/pci/host/pci-brcmstb.h
> @@ -0,0 +1,33 @@
> +#ifndef __BRCMSTB_PCI_H
> +#define __BRCMSTB_PCI_H
> +
> +/*
> + * Copyright (C) 2015 - 2017 Broadcom
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#define BRCM_PCIE_NAME_SIZE		8
> +#define BRCM_INT_PCI_MSI_NR		32
> +#define BRCM_PCIE_HW_REV_33		0x0303
> +
> +/* Broadcom PCIE Offsets */
> +#define PCIE_INTR2_CPU_BASE		0x4300
> +
> +#if defined(CONFIG_MIPS)
> +/* Broadcom MIPs HW implicitly does the swapping if necessary */
> +#define bcm_readl(a)		__raw_readl(a)
> +#define bcm_writel(d, a)	__raw_writel(d, a)
> +#else
> +#define bcm_readl(a)		readl(a)
> +#define bcm_writel(d, a)	writel(d, a)
> +#endif
> +
> +#endif /* __BRCMSTB_PCI_H */
> -- 
> 1.9.0.138.g2de3478
> 
> 
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Re: [PATCH 3/8] PCI: host: brcmstb: Broadcom PCIe Host Controller

[Jim Quinlan]

On Tue, Oct 24, 2017 at 5:15 PM, Bjorn Helgaas <helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> Run "git log --oneline drivers/pci/host" and make yours match, e.g.,
>
> s/PCI: host: brcmstb: Broadcom PCIe Host Controller/
>   PCI: brcmstb: Add Broadcom STB PCIe host controller driver/
>
> On Tue, Oct 24, 2017 at 02:15:44PM -0400, Jim Quinlan wrote:
>> This commit adds the basic Broadcom STB PCIe controller.  Missing is
>> the ability to process MSI and also handle dma-ranges for inbound
>> memory accesses.  These two functionalities are added in subsequent
>> commits.http://stb-bld-00.broadcom.com/gitweb/ejtag.git/blob/d526f31b497072fc2a311e25700957753479cebc:/app/bbsserver/bbsserver/wf_mem.c
>>http://stb-bld-00.broadcom.com/gitweb/ejtag.git/blob/d526f31b497072fc2a311e25700957753479cebc:/app/bbsserver/bbsserver/wf_mem.c
>> The PCIe block contains an MDIO interface.  This is a local interface
>> only accessible by the PCIe controller.  It cannot be used or shared
>> by any other HW.  As such, the small amount of code for this
>> controller is included in this driver as there is little upside to put
>> it elsewhere.
>>
>> Signed-off-by: Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>>  drivers/pci/host/Kconfig       |    8 +
>>  drivers/pci/host/Makefile      |    1 +
>>  drivers/pci/host/pci-brcmstb.c | 1195 ++++++++++++++++++++++++++++++++++++++++
>
> Name this pcie-brcmstb.c.  I used to have the idea we should name
> things "pci-" unless they explicitly used some PCIe interfaces or
> something, but I think that just made it confusing for PCIe
> controllers like yours.
>
>>  drivers/pci/host/pci-brcmstb.h |   33 ++
>
> Unless you need this include file elsewhere, just fold its contents
> into the .c file.
There are three .c files, and one .h file.  There should only be
things in the include file that are needed by at least two of the .c
files.  I'll check this and move anything that is only used by one
file.

>
>>  4 files changed, 1237 insertions(+)
>>  create mode 100644 drivers/pci/host/pci-brcmstb.c
>>  create mode 100644 drivers/pci/host/pci-brcmstb.h
>>
>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> index b868803..b9b4f11 100644
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>> @@ -220,4 +220,12 @@ config VMD
>>         To compile this driver as a module, choose M here: the
>>         module will be called vmd.
>>
>> +config PCI_BRCMSTB
>
> PCIE_BRCMSTB
>
>> +     tristate "Broadcom Brcmstb PCIe platform host driver"
>> +     depends on ARCH_BRCMSTB || BMIPS_GENERIC
>> +     depends on OF
>> +     depends on SOC_BRCMSTB
>> +     default ARCH_BRCMSTB || BMIPS_GENERIC
>> +     help
>> +       Adds support for Broadcom Settop Box PCIe host controller.
>>  endmenu
>> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
>> index 1238278..4398d2c 100644
>> --- a/drivers/pci/host/Makefile
>> +++ b/drivers/pci/host/Makefile
>> @@ -21,6 +21,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
>>  obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
>>  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>>  obj-$(CONFIG_VMD) += vmd.o
>> +obj-$(CONFIG_PCI_BRCMSTB) += pci-brcmstb.o
>>
>>  # The following drivers are for devices that use the generic ACPI
>>  # pci_root.c driver but don't support standard ECAM config access.
>> diff --git a/drivers/pci/host/pci-brcmstb.c b/drivers/pci/host/pci-brcmstb.c
>> new file mode 100644
>> index 0000000..883b435
>> --- /dev/null
>> +++ b/drivers/pci/host/pci-brcmstb.c
>> @@ -0,0 +1,1195 @@
>> +/*
>> + * Copyright (C) 2009 - 2017 Broadcom
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +#include <linux/clk.h>
>> +#include <linux/compiler.h>
>> +#include <linux/delay.h>
>> +#include <linux/init.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/ioport.h>
>> +#include <linux/irqdomain.h>
>> +#include <linux/kernel.h>
>> +#include <linux/list.h>
>> +#include <linux/log2.h>
>> +#include <linux/module.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_pci.h>
>> +#include <linux/of_pci.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/pci.h>
>> +#include <linux/printk.h>
>> +#include <linux/regulator/consumer.h>
>> +#include <linux/sizes.h>
>> +#include <linux/slab.h>
>> +#include <soc/brcmstb/memory_api.h>
>> +#include <linux/string.h>
>> +#include <linux/types.h>
>> +#include "pci-brcmstb.h"
>> +
>> +/* Broadcom Settop Box PCIE Register Offsets.  */
>
> s/PCIE/PCIe/ in comments and other English text throughout.
>
>> +#define PCIE_RC_CFG_PCIE_LINK_CAPABILITY             0x00b8
>> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL         0x00bc
>> +#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL            0x00c8
>> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2               0x00dc
>
> Many of these look like they are describing the PCIe capability.  If
> so, please define a Broadcom-specific base and use the already-defined
> constants from include/uapi/linux/pci_regs.h, e.g., PCI_EXP_LNKCAP,
> etc.
>
>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1              0x0188
>> +#define PCIE_RC_CFG_PRIV1_ID_VAL3                    0x043c
>> +#define PCIE_RC_DL_MDIO_ADDR                         0x1100
>> +#define PCIE_RC_DL_MDIO_WR_DATA                              0x1104
>> +#define PCIE_RC_DL_MDIO_RD_DATA                              0x1108
>> +#define PCIE_MISC_MISC_CTRL                          0x4008
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO             0x400c
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI             0x4010
>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO                  0x402c
>> +#define PCIE_MISC_RC_BAR1_CONFIG_HI                  0x4030
>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO                  0x4034
>> +#define PCIE_MISC_RC_BAR2_CONFIG_HI                  0x4038
>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO                  0x403c
>> +#define PCIE_MISC_RC_BAR3_CONFIG_HI                  0x4040
>> +#define PCIE_MISC_PCIE_CTRL                          0x4064
>> +#define PCIE_MISC_PCIE_STATUS                                0x4068
>> +#define PCIE_MISC_REVISION                           0x406c
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT     0x4070
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI                0x4080
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI               0x4084
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG                       0x4204
>> +
>> +/* Broadcom Settop Box PCIE Register Field Shift, Mask Info.  */
>> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_MASK  0x3f00000
>
> Looks suspiciously like PCI_EXP_LNKSTA_NLW.
The #define symbols I use are machine generated by the RDB tools.
Everytime a new chip comes out, I run
a script that checks that the register offsets have not changed as
compared to our driver (as sometimes they do).
If I start using other names for constants I will probably lose this ability.

>
>> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_SHIFT    0x14
>> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_MASK     0xf0000
>> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_NEG_LINK_SPEED_SHIFT    0x10
>> +#define PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_MASK         0xf
>> +#define PCIE_RC_CFG_PCIE_LINK_CAPABILITY_MAX_LINK_SPEED_SHIFT                0x0
>> +#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK             0x10
>> +#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_SHIFT            0x4
>> +#define      PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_MASK   0xf
>> +#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_SHIFT       0x0
>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_MASK        0x3
>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_SHIFT       0x0
>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK        0xc
>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT       0x2
>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_MASK        0x30
>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_SHIFT       0x4
>> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK            0xffffff
>> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT           0x0
>> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK                       0x1000
>> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT                      0xc
>> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK            0x2000
>> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT           0xd
>> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK                      0x300000
>> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT             0x14
>> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK                   0xf8000000
>> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT                  0x1b
>> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK                   0x7c00000
>> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT                  0x16
>> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK                   0x1f
>> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT                  0x0
>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_MASK               0xfffff000
>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_MATCH_ADDRESS_SHIFT              0xc
>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK                        0x1f
>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT                       0x0
>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_MASK               0xfffff000
>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_MATCH_ADDRESS_SHIFT              0xc
>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK                        0x1f
>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT                       0x0
>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_MASK               0xfffff000
>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_MATCH_ADDRESS_SHIFT              0xc
>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK                        0x1f
>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT                       0x0
>> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK                 0x4
>> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT                        0x2
>> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK            0x1
>> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT           0x0
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK                 0x80
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT                        0x7
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK            0x20
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT           0x5
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK            0x10
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT           0x4
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK          0x40
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT         0x6
>> +#define PCIE_MISC_REVISION_MAJMIN_MASK                               0xffff
>> +#define PCIE_MISC_REVISION_MAJMIN_SHIFT                              0
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK  0xfff00000
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK   0xfff0
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT  0x4
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS       0xc
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK              0xff
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT     0x0
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK    0xff
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT   0x0
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK      0x2
>> +#define PCIE_MISC_HARD_PCIE
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK              0x08000000
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT     0x1b
>> +#define PCIE_RGR1_SW_INIT_1_PERST_MASK                               0x1
>> +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT                              0x0
>
> Many of these definitions aren't used, and I'm dubious about the value
> of including them all
I will remove those that are not being used.

>
>> +#define BRCM_NUM_PCI_OUT_WINS                0x4
>> +#define BRCM_MAX_SCB                 0x4
>> +
>> +#define BRCM_MSI_TARGET_ADDR_LT_4GB  0x0fffffffcULL
>> +#define BRCM_MSI_TARGET_ADDR_GT_4GB  0xffffffffcULL
>> +
>> +#define BURST_SIZE_128                       0
>> +#define BURST_SIZE_256                       1
>> +#define BURST_SIZE_512                       2
>> +
>> +/* Offsets from PCIE_INTR2_CPU_BASE */
>> +#define STATUS                               0x0
>> +#define SET                          0x4
>> +#define CLR                          0x8
>> +#define MASK_STATUS                  0xc
>> +#define MASK_SET                     0x10
>> +#define MASK_CLR                     0x14
>> +
>> +#define PCI_BUSNUM_SHIFT             20
>> +#define PCI_SLOT_SHIFT                       15
>> +#define PCI_FUNC_SHIFT                       12
>> +
>> +#if defined(__BIG_ENDIAN)
>> +#define      DATA_ENDIAN             2       /* PCI->DDR inbound accesses */
>> +#define MMIO_ENDIAN          2       /* CPU->PCI outbound accesses */
>> +#else
>> +#define      DATA_ENDIAN             0
>> +#define MMIO_ENDIAN          0
>> +#endif
>> +
>> +#define MDIO_PORT0           0x0
>> +#define MDIO_DATA_MASK               0x7fffffff
>> +#define MDIO_DATA_SHIFT              0x0
>> +#define MDIO_PORT_MASK               0xf0000
>> +#define MDIO_PORT_SHIFT              0x16
>> +#define MDIO_REGAD_MASK              0xffff
>> +#define MDIO_REGAD_SHIFT     0x0
>> +#define MDIO_CMD_MASK                0xfff00000
>> +#define MDIO_CMD_SHIFT               0x14
>> +#define MDIO_CMD_READ                0x1
>> +#define MDIO_CMD_WRITE               0x0
>> +#define MDIO_DATA_DONE_MASK  0x80000000
>> +#define MDIO_RD_DONE(x)              (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
>> +#define MDIO_WT_DONE(x)              (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
>> +#define SSC_REGS_ADDR                0x1100
>> +#define SET_ADDR_OFFSET              0x1f
>> +#define SSC_CNTL_OFFSET              0x2
>> +#define SSC_CNTL_OVRD_EN_MASK        0x8000
>> +#define SSC_CNTL_OVRD_EN_SHIFT       0xf
>> +#define SSC_CNTL_OVRD_VAL_MASK       0x4000
>> +#define SSC_CNTL_OVRD_VAL_SHIFT      0xe
>> +#define SSC_STATUS_OFFSET    0x1
>> +#define SSC_STATUS_SSC_MASK  0x400
>> +#define SSC_STATUS_SSC_SHIFT 0xa
>> +#define SSC_STATUS_PLL_LOCK_MASK     0x800
>> +#define SSC_STATUS_PLL_LOCK_SHIFT    0xb
>> +
>> +#define IDX_ADDR(pcie)       \
>> +     ((pcie)->reg_offsets[EXT_CFG_INDEX])
>> +#define DATA_ADDR(pcie)      \
>> +     ((pcie)->reg_offsets[EXT_CFG_DATA])
>> +#define PCIE_RGR1_SW_INIT_1(pcie) \
>> +     ((pcie)->reg_offsets[RGR1_SW_INIT_1])
>> +
>> +enum {
>> +     RGR1_SW_INIT_1,
>> +     EXT_CFG_INDEX,
>> +     EXT_CFG_DATA,
>> +};
>> +
>> +enum {
>> +     RGR1_SW_INIT_1_INIT_MASK,
>> +     RGR1_SW_INIT_1_INIT_SHIFT,
>> +     RGR1_SW_INIT_1_PERST_MASK,
>> +     RGR1_SW_INIT_1_PERST_SHIFT,
>> +};
>> +
>> +enum pcie_type {
>> +     BCM7425,
>> +     BCM7435,
>> +     GENERIC,
>> +     BCM7278,
>> +};
>> +
>> +#define RD_FLD(base, reg, field) \
>> +     rd_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
>> +#define WR_FLD(base, reg, field, val) \
>> +     wr_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
>> +#define WR_FLD_RB(base, reg, field, val) \
>> +     wr_fld_rb(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
>> +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
>> +     wr_fld(base + reg + off, reg##_##field##_MASK, \
>> +            reg##_##field##_SHIFT, val)
>> +#define EXTRACT_FIELD(val, reg, field) \
>> +     ((val & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
>> +#define INSERT_FIELD(val, reg, field, field_val) \
>> +     ((val & ~reg##_##field##_MASK) | \
>> +      (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
>> +
>> +struct pcie_cfg_data {
>> +     const int *reg_field_info;
>> +     const int *offsets;
>> +     const enum pcie_type type;
>> +};
>> +
>> +static const int pcie_reg_field_info[] = {
>> +     [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
>> +     [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
>> +};
>> +
>> +static const int pcie_reg_field_info_bcm7278[] = {
>> +     [RGR1_SW_INIT_1_INIT_MASK] = 0x1,
>> +     [RGR1_SW_INIT_1_INIT_SHIFT] = 0x0,
>> +};
>> +
>> +static const int pcie_offset_bcm7425[] = {
>> +     [RGR1_SW_INIT_1] = 0x8010,
>> +     [EXT_CFG_INDEX]  = 0x8300,
>> +     [EXT_CFG_DATA]   = 0x8304,
>> +};
>> +
>> +static const struct pcie_cfg_data bcm7425_cfg = {
>> +     .reg_field_info = pcie_reg_field_info,
>> +     .offsets        = pcie_offset_bcm7425,
>> +     .type           = BCM7425,
>> +};
>> +
>> +static const int pcie_offsets[] = {
>> +     [RGR1_SW_INIT_1] = 0x9210,
>> +     [EXT_CFG_INDEX]  = 0x9000,
>> +     [EXT_CFG_DATA]   = 0x9004,
>> +};
>> +
>> +static const struct pcie_cfg_data bcm7435_cfg = {
>> +     .reg_field_info = pcie_reg_field_info,
>> +     .offsets        = pcie_offsets,
>> +     .type           = BCM7435,
>> +};
>> +
>> +static const struct pcie_cfg_data generic_cfg = {
>> +     .reg_field_info = pcie_reg_field_info,
>> +     .offsets        = pcie_offsets,
>> +     .type           = GENERIC,
>> +};
>> +
>> +static const int pcie_offset_bcm7278[] = {
>> +     [RGR1_SW_INIT_1] = 0xc010,
>> +     [EXT_CFG_INDEX] = 0x9000,
>> +     [EXT_CFG_DATA] = 0x9004,
>> +};
>> +
>> +static const struct pcie_cfg_data bcm7278_cfg = {
>> +     .reg_field_info = pcie_reg_field_info_bcm7278,
>> +     .offsets        = pcie_offset_bcm7278,
>> +     .type           = BCM7278,
>> +};
>> +
>> +static void __iomem *brcm_pci_map_cfg(struct pci_bus *bus, unsigned int devfn,
>> +                                   int where);
>> +
>> +static struct pci_ops brcm_pci_ops = {
>> +     .map_bus = brcm_pci_map_cfg,
>> +     .read = pci_generic_config_read32,
>> +     .write = pci_generic_config_write32,
>
> Ouch, does your hardware really not support 8- and 16-bit config
> accesses?  As you probably know, that can lead to config space
> corruption with devices that have RW1C bits in registers.
>
Our hardware can access 8/16/32 and I was going to modify this at a
later time.  As you requested it I will do it with the next patchset
version.

>> +};
>> +
>> +struct brcm_dev_pwr_supply {
>> +     struct list_head node;
>> +     char name[32];
>> +     struct regulator *regulator;
>> +};
>> +
>> +struct brcm_window {
>> +     dma_addr_t pci_addr;
>> +     phys_addr_t cpu_addr;
>> +     dma_addr_t size;
>> +};
>> +
>> +/* Internal Bus Controller Information.*/
>> +struct brcm_pcie {
>> +     struct list_head        list;
>> +     void __iomem            *base;
>> +     char                    name[BRCM_PCIE_NAME_SIZE];
>> +     bool                    suspended;
>> +     struct clk              *clk;
>> +     struct device_node      *dn;
>> +     int                     irq;
>> +     int                     num_out_wins;
>> +     bool                    ssc;
>> +     int                     gen;
>> +     struct brcm_window      out_wins[BRCM_NUM_PCI_OUT_WINS];
>> +     struct list_head        resources;
>> +     struct device           *dev;
>> +     struct list_head        pwr_supplies;
>> +     unsigned int            rev;
>> +     unsigned int            num;
>> +     bool                    bridge_setup_done;
>
> Nobody else needs a "bridge_setup_done" variable; I'm skeptical that
> you do.  Please use similar style to other drivers whenever possible.
I will investigate and remove if possible.

>
>> +     const int               *reg_offsets;
>> +     const int               *reg_field_info;
>> +     enum pcie_type          type;
>> +     struct pci_bus          *root_bus;
>> +     int                     id;
>
> Please reorder with more generic info at the top, e.g., "* dev",
> "*base", "resources", etc., should be near the top, as other drivers
> do.
>
>> +};
>> +
>> +static struct list_head brcm_pcie = LIST_HEAD_INIT(brcm_pcie);
>
> Do you really need a list of controllers?  It looks like this is only
> used for remove.  If you get rid of the list, you probably don't need
> brcm_pcie_lock either.
We've had chips with three RC controllers.   There is a structure --
dma_ranges -- which is kzalloc'd and is shared by the controllers.
The first controller born and the last controller removed does the
alloc/free.  Similarly, we need to coordinate adding/removing
tContrary urhe pci bus notifier.  I'm not sure how this can be done
w/o an array/list.

>
>> +static phys_addr_t scb_size[BRCM_MAX_SCB];
>> +static int num_memc;
>> +static DEFINE_MUTEX(brcm_pcie_lock);
>> +
>> +/*
>> + * The roundup_pow_of_two() from log2.h invokes
>> + * __roundup_pow_of_two(unsigned long), but we really need a
>> + * such a function to take a native u64 since unsigned long
>> + * is 32 bits on some configurations.  So we provide this helper
>> + * function below.
>> + */
>> +static u64 roundup_pow_of_two_64(u64 n)
>> +{
>> +     return 1ULL << fls64(n - 1);
>> +}
>> +
>> +static int brcm_pcie_add_controller(struct brcm_pcie *pcie)
>> +{
>> +     mutex_lock(&brcm_pcie_lock);
>> +     snprintf(pcie->name, sizeof(pcie->name) - 1, "PCIe%d", pcie->id);
>> +     list_add_tail(&pcie->list, &brcm_pcie);
>> +     mutex_unlock(&brcm_pcie_lock);
>> +
>> +     return 0;
>> +}
>> +
>> +static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
>> +{
>> +     struct list_head *pos, *q;
>> +     struct brcm_pcie *tmp;
>> +
>> +     mutex_lock(&brcm_pcie_lock);
>> +     list_for_each_safe(pos, q, &brcm_pcie) {
>> +             tmp = list_entry(pos, struct brcm_pcie, list);
>> +             if (tmp == pcie) {
>> +                     list_del(pos);
>> +                     if (list_empty(&brcm_pcie))
>> +                             num_memc = 0;
>> +                     break;
>> +             }
>> +     }
>> +     mutex_unlock(&brcm_pcie_lock);
>> +}
>> +
>> +/* This is to convert the size of the inbound bar region to the
>> + * non-liniear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
>
> Please use conventional comment style for multi-line comments, i.e.,
>
>   /*
>    * text ...
>    */
>
>> + */
>> +int encode_ibar_size(u64 size)
>> +{
>> +     int log2_in = ilog2(size);
>> +
>> +     if (log2_in >= 12 && log2_in <= 15)
>> +             /* Covers 4KB to 32KB (inclusive) */
>> +             return (log2_in - 12) + 0x1c;
>> +     else if (log2_in >= 16 && log2_in <= 37)
>> +             /* Covers 64KB to 32GB, (inclusive) */
>> +             return log2_in - 15;
>> +     /* Something is awry so disable */
>> +     return 0;
>> +}
>> +
>> +static u32 mdio_form_pkt(int port, int regad, int cmd)
>> +{
>> +     u32 pkt = 0;
>> +
>> +     pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
>> +     pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
>> +     pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
>> +
>> +     return pkt;
>> +}
>> +
>> +/* negative return value indicates error */
>> +static int mdio_read(void __iomem *base, u8 port, u8 regad)
>> +{
>> +     int tries;
>> +     u32 data;
>> +
>> +     bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
>> +                base + PCIE_RC_DL_MDIO_ADDR);
>> +     bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
>> +
>> +     data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
>> +     for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
>> +             udelay(10);
>> +             data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
>> +     }
>> +
>> +     return MDIO_RD_DONE(data)
>> +             ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
>> +             : -EIO;
>> +}
>> +
>> +/* negative return value indicates error */
>> +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
>> +{
>> +     int tries;
>> +     u32 data;
>> +
>> +     bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
>> +                base + PCIE_RC_DL_MDIO_ADDR);
>> +     bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
>> +     bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
>> +                base + PCIE_RC_DL_MDIO_WR_DATA);
>> +
>> +     data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
>> +     for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
>> +             udelay(10);
>> +             data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
>> +     }
>> +
>> +     return MDIO_WT_DONE(data) ? 0 : -EIO;
>> +}
>> +
>> +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
>> +{
>> +     return (bcm_readl(p) & mask) >> shift;
>> +}
>> +
>> +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
>> +{
>> +     u32 reg = bcm_readl(p);
>> +
>> +     reg = (reg & ~mask) | ((val << shift) & mask);
>> +     bcm_writel(reg, p);
>> +}
>> +
>> +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
>> +{
>> +     wr_fld(p, mask, shift, val);
>> +     (void)bcm_readl(p);
>> +}
>> +
>> +/* configures device for ssc mode; negative return value indicates error */
>> +static int set_ssc(void __iomem *base)
>> +{
>> +     int tmp;
>> +     u16 wrdata;
>> +     int pll, ssc;
>> +
>> +     tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
>> +     if (tmp < 0)
>> +             return tmp;
>> +
>> +     tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
>> +     if (tmp < 0)
>> +             return tmp;
>> +
>> +     wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
>> +     wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
>> +     tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
>> +     if (tmp < 0)
>> +             return tmp;
>> +
>> +     usleep_range(1000, 2000);
>> +     tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
>> +     if (tmp < 0)
>> +             return tmp;
>> +
>> +     ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
>> +     pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
>> +
>> +     return (ssc && pll) ? 0 : -EIO;
>> +}
>> +
>> +/* limits operation to a specific generation (1, 2, or 3) */
>> +static void set_gen(void __iomem *base, int gen)
>> +{
>> +     WR_FLD(base, PCIE_RC_CFG_PCIE_LINK_CAPABILITY, MAX_LINK_SPEED, gen);
>> +     WR_FLD(base, PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2,
>> +            TARGET_LINK_SPEED, gen);
>> +}
>> +
>> +static void set_pcie_outbound_win(struct brcm_pcie *pcie, unsigned int win,
>> +                               phys_addr_t cpu_addr, dma_addr_t  pci_addr,
>> +                               dma_addr_t size)
>> +{
>> +     void __iomem *base = pcie->base;
>> +     phys_addr_t cpu_addr_mb, limit_addr_mb;
>> +     u32 tmp;
>> +
>> +     /* Set the base of the pci_addr window */
>> +     bcm_writel(lower_32_bits(pci_addr) + MMIO_ENDIAN,
>> +                base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
>> +     bcm_writel(upper_32_bits(pci_addr),
>> +                base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
>> +
>> +     cpu_addr_mb = cpu_addr >> 20;
>> +     limit_addr_mb = (cpu_addr + size - 1) >> 20;
>> +
>> +     /* Write the addr base low register */
>> +     WR_FLD_WITH_OFFSET(base, (win * 4),
>> +                        PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
>> +                        BASE, cpu_addr_mb);
>> +     /* Write the addr limit low register */
>> +     WR_FLD_WITH_OFFSET(base, (win * 4),
>> +                        PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
>> +                        LIMIT, limit_addr_mb);
>> +
>> +     if (pcie->type != BCM7435 && pcie->type != BCM7425) {
>> +             /* Write the cpu addr high register */
>> +             tmp = (u32)(cpu_addr_mb >>
>> +                     PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
>> +             WR_FLD_WITH_OFFSET(base, (win * 8),
>> +                                PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
>> +                                BASE, tmp);
>> +             /* Write the cpu limit high register */
>> +             tmp = (u32)(limit_addr_mb >>
>> +                     PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
>> +             WR_FLD_WITH_OFFSET(base, (win * 8),
>> +                                PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
>> +                                LIMIT, tmp);
>> +     }
>> +}
>> +
>> +static int is_pcie_link_up(struct brcm_pcie *pcie, bool silent)
>
> Please use function names similar to other drivers, e.g.,
> brcm_pcie_link_up() in this case.
>
>> +{
>> +     void __iomem *base = pcie->base;
>> +     u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
>> +     u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
>> +     u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
>> +     u32 rc = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
>> +
>> +     if (!rc && !silent)
>> +             dev_err(pcie->dev, "controller configured in EP mode\n");
>> +
>> +     return  (rc && dla && plu) ? 1 : 0;
>> +}
>> +
>> +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
>> +                                             unsigned int val)
>> +{
>> +     unsigned int offset;
>> +     unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
>> +     u32 mask =  pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
>> +
>> +     if (pcie->type != BCM7278) {
>> +             wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
>> +                       val);
>> +     } else if (of_machine_is_compatible("brcm,bcm7278a0")) {
>> +             /* The two PCIE instance on 7278a0 are not even consistent with
>> +              * respect to each other for internal offsets, here we offset
>> +              * by 0x14000 + RGR1_SW_INIT_1's relative offset to account for
>> +              * that.
>> +              */
>> +             offset = pcie->id ? 0x14010 : pcie->reg_offsets[RGR1_SW_INIT_1];
>> +             wr_fld_rb(pcie->base + offset, mask, shift, val);
>> +     } else {
>> +             wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
>> +                       val);
>> +     }
>> +}
>> +
>> +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
>> +                                    unsigned int val)
>> +{
>> +     if (pcie->type != BCM7278)
>> +             wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
>> +                       PCIE_RGR1_SW_INIT_1_PERST_MASK,
>> +                       PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
>> +     else
>> +             /* Assert = 0, de-assert = 1 on 7278 */
>> +             WR_FLD_RB(pcie->base, PCIE_MISC_PCIE_CTRL, PCIE_PERSTB, !val);
>> +}
>> +
>> +static int brcm_parse_ranges(struct brcm_pcie *pcie)
>> +{
>> +     struct resource_entry *win;
>> +     int ret;
>> +
>> +     ret = of_pci_get_host_bridge_resources(pcie->dn, 0, 0xff,
>> +                                            &pcie->resources, NULL);
>> +     if (ret) {
>> +             dev_err(pcie->dev, "failed to get host resources\n");
>> +             return ret;
>> +     }
>> +
>> +     resource_list_for_each_entry(win, &pcie->resources) {
>> +             struct resource *parent, *res = win->res;
>> +             dma_addr_t offset = (dma_addr_t)win->offset;
>> +
>> +             if (resource_type(res) == IORESOURCE_IO) {
>> +                     parent = &ioport_resource;
>> +             } else if (resource_type(res) == IORESOURCE_MEM) {
>> +                     if (pcie->num_out_wins >= BRCM_NUM_PCI_OUT_WINS) {
>> +                             dev_err(pcie->dev, "too many outbound wins\n");
>> +                             return -EINVAL;
>> +                     }
>> +                     pcie->out_wins[pcie->num_out_wins].cpu_addr
>> +                             = (phys_addr_t)res->start;
>> +                     pcie->out_wins[pcie->num_out_wins].pci_addr
>> +                             = (dma_addr_t)(res->start
>> +                                            - (phys_addr_t)offset);
>> +                     pcie->out_wins[pcie->num_out_wins].size
>> +                             = (dma_addr_t)(res->end - res->start + 1);
>> +                     pcie->num_out_wins++;
>> +                     parent = &iomem_resource;
>> +             } else {
>> +                     continue;
>> +             }
>> +
>> +             ret = devm_request_resource(pcie->dev, parent, res);
>> +             if (ret) {
>> +                     dev_err(pcie->dev, "failed to get res %pR\n", res);
>> +                     return ret;
>> +             }
>> +     }
>> +     return 0;
>> +}
>> +
>> +static void set_regulators(struct brcm_pcie *pcie, bool on)
>> +{
>> +     struct list_head *pos;
>> +
>> +     list_for_each(pos, &pcie->pwr_supplies) {
>> +             struct brcm_dev_pwr_supply *supply
>> +                     = list_entry(pos, struct brcm_dev_pwr_supply, node);
>> +
>> +             if (on && regulator_enable(supply->regulator))
>> +                     pr_debug("Unable to turn on %s supply.\n",
>> +                              supply->name);
>> +             else if (!on && regulator_disable(supply->regulator))
>> +                     pr_debug("Unable to turn off %s supply.\n",
>> +                              supply->name);
>> +     }
>> +}
>> +
>> +static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
>> +{
>> +     void __iomem *base = pcie->base;
>> +     unsigned int scb_size_val;
>> +     u64 rc_bar2_size = 0, rc_bar2_offset = 0, total_mem_size = 0;
>> +     u32 tmp, burst;
>> +     int i;
>> +
>> +     /* reset the bridge and the endpoint device */
>> +     /* field: PCIE_BRIDGE_SW_INIT = 1 */
>> +     brcm_pcie_bridge_sw_init_set(pcie, 1);
>> +
>> +     /* field: PCIE_SW_PERST = 1, on 7278, we start de-asserted already */
>> +     if (pcie->type != BCM7278)
>> +             brcm_pcie_perst_set(pcie, 1);
>> +
>> +     usleep_range(100, 200);
>> +
>> +     /* take the bridge out of reset */
>> +     /* field: PCIE_BRIDGE_SW_INIT = 0 */
>> +     brcm_pcie_bridge_sw_init_set(pcie, 0);
>> +
>> +     WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
>> +     /* wait for serdes to be stable */
>> +     usleep_range(100, 200);
>> +
>> +     /* Grab the PCIe hw revision number */
>> +     tmp = bcm_readl(base + PCIE_MISC_REVISION);
>> +     pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
>> +
>> +     /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
>> +     tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
>> +     tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
>> +     burst = (pcie->type == GENERIC || pcie->type == BCM7278)
>> +             ? BURST_SIZE_512 : BURST_SIZE_256;
>> +     tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE, burst);
>> +     bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
>> +
>> +     /* Set up inbound memory view for the EP (called RC_BAR2,
>> +      * not to be confused with the BARs that are advertised by
>> +      * the EP).
>
> Multi-line comment style here and below.
>
>> +      */
>> +     for (i = 0; i < num_memc; i++)
>> +             total_mem_size += scb_size[i];
>> +
>> +     /* The PCI host controller by design must set the inbound
>> +      * viewport to be a contiguous arrangement of all of the
>> +      * system's memory.  In addition, its size mut be a power of
>> +      * two.  To further complicate matters, the viewport must
>> +      * start on a pci-address that is aligned on a multiple of its
>> +      * size.  If a portion of the viewport does not represent
>> +      * system memory -- e.g. 3GB of memory requires a 4GB viewport
>> +      * -- we can map the outbound memory in or after 3GB and even
>> +      * though the viewport will overlap the outbound memory the
>> +      * controller will know to send outbound memory downstream and
>> +      * everything else upstream.
>> +      */
>> +     rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
>> +
>> +     /* Set simple configuration based on memory sizes
>> +      * only.  We always start the viewport at address 0.
>> +      */
>> +     rc_bar2_offset = 0;
>> +
>> +     tmp = lower_32_bits(rc_bar2_offset);
>> +     tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
>> +                        encode_ibar_size(rc_bar2_size));
>> +     bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
>> +     bcm_writel(upper_32_bits(rc_bar2_offset),
>> +                base + PCIE_MISC_RC_BAR2_CONFIG_HI);
>> +
>> +     /* field: SCB0_SIZE, default = 0xf (1 GB) */
>> +     scb_size_val = scb_size[0]
>> +             ? ilog2(scb_size[0]) - 15 : 0xf;
>> +     WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
>> +
>> +     /* field: SCB1_SIZE, default = 0xf (1 GB) */
>> +     if (num_memc > 1) {
>> +             scb_size_val = scb_size[1]
>> +                     ? ilog2(scb_size[1]) - 15 : 0xf;
>> +             WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB1_SIZE, scb_size_val);
>> +     }
>> +
>> +     /* field: SCB2_SIZE, default = 0xf (1 GB) */
>> +     if (num_memc > 2) {
>> +             scb_size_val = scb_size[2]
>> +                     ? ilog2(scb_size[2]) - 15 : 0xf;
>> +             WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB2_SIZE, scb_size_val);
>> +     }
>> +
>> +     /* disable the PCIE->GISB memory window (RC_BAR1) */
>> +     WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
>> +
>> +     /* disable the PCIE->SCB memory window (RC_BAR3) */
>> +     WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
>> +
>> +     if (!pcie->suspended) {
>> +             /* clear any interrupts we find on boot */
>> +             bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
>> +             (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
>> +     }
>> +
>> +     /* Mask all interrupts since we are not handling any yet */
>> +     bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
>> +     (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
>> +
>> +     if (pcie->gen)
>> +             set_gen(base, pcie->gen);
>> +
>> +     /* take the EP device out of reset */
>> +     /* field: PCIE_SW_PERST = 0 */
>> +     brcm_pcie_perst_set(pcie, 0);
>> +}
>> +
>> +static const char *link_speed_to_str(int s)
>> +{
>> +     switch (s) {
>> +     case 1:
>> +             return "2.5";
>> +     case 2:
>> +             return "5.0";
>> +     case 3:
>> +             return "8.0";
>> +     default:
>> +             break;
>> +     }
>> +     return "???";
>> +}
>> +
>> +static int brcm_pcie_setup_bridge(struct brcm_pcie *pcie)
>> +{
>> +     void __iomem *base = pcie->base;
>> +     const int limit = pcie->suspended ? 1000 : 100;
>> +     unsigned int status;
>> +     int i, j, ret;
>> +     u32 neg_width, neg_speed;
>> +     bool ssc_good = false;
>> +
>> +     /* Give the RC/EP time to wake up, before trying to configure RC.
>> +      * Intermittently check status for link-up, up to a total of 100ms
>> +      * when we don't know if the device is there, and up to 1000ms if
>> +      * we do know the device is there.
>> +      */
>> +     for (i = 1, j = 0; j < limit && !is_pcie_link_up(pcie, true);
>> +          j += i, i = i * 2)
>> +             msleep(i + j > limit ? limit - j : i);
>> +
>> +     if (!is_pcie_link_up(pcie, false)) {
>> +             dev_info(pcie->dev, "link down\n");
>> +             return -ENODEV;
>> +     }
>> +
>> +     for (i = 0; i < pcie->num_out_wins; i++)
>> +             set_pcie_outbound_win(pcie, i, pcie->out_wins[i].cpu_addr,
>> +                                   pcie->out_wins[i].pci_addr,
>> +                                   pcie->out_wins[i].size);
>> +
>> +     /* For config space accesses on the RC, show the right class for
>> +      * a PCI-PCI bridge
>> +      */
>> +     WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
>> +
>> +     if (pcie->ssc) {
>> +             ret = set_ssc(base);
>> +             if (ret == 0)
>> +                     ssc_good = true;
>> +             else
>> +                     dev_err(pcie->dev,
>> +                             "failed attempt to enter ssc mode\n");
>> +     }
>> +
>> +     status = bcm_readl(base + PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL);
>> +     neg_width = EXTRACT_FIELD(status, PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL,
>> +                               NEG_LINK_WIDTH);
>> +     neg_speed = EXTRACT_FIELD(status, PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL,
>> +                               NEG_LINK_SPEED);
>> +     dev_info(pcie->dev, "link up, %s Gbps x%u %s\n",
>> +              link_speed_to_str(neg_speed), neg_width,
>> +              ssc_good ? "(SSC)" : "(!SSC)");
>> +
>> +     /* Enable configuration request retry (see pci_scan_device()) */
>> +     /* field RC_CRS_EN = 1 */
>> +     WR_FLD(base, PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL, RC_CRS_EN, 1);
>
> As long as you advertise CRS SV support, the PCI core should be
> enabling it automatically; why do you need this here?
>
Will investigate.

>> +
>> +     /* PCIE->SCB endian mode for BAR */
>> +     /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
>> +     WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
>> +               ENDIAN_MODE_BAR2, DATA_ENDIAN);
>> +
>> +     /* Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
>> +      * is enabled =>  setting the CLKREQ_DEBUG_ENABLE field to 1.
>> +      */
>> +     WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
>> +
>> +     pcie->bridge_setup_done = true;
>> +
>> +     return 0;
>> +}
>> +
>> +static void enter_l23(struct brcm_pcie *pcie)
>> +{
>> +     void __iomem *base = pcie->base;
>> +     int tries, l23;
>> +
>> +     /* assert request for L23 */
>> +     WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
>> +     /* poll L23 status */
>> +     for (tries = 0, l23 = 0; tries < 1000 && !l23; tries++)
>> +             l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
>> +     if (!l23)
>> +             dev_err(pcie->dev, "failed to enter L23\n");
>> +}
>> +
>> +static void turn_off(struct brcm_pcie *pcie)
>> +{
>> +     void __iomem *base = pcie->base;
>> +
>> +     if (is_pcie_link_up(pcie, true))
>> +             enter_l23(pcie);
>> +     /* Reset endpoint device */
>> +     brcm_pcie_perst_set(pcie, 1);
>> +     /* deassert request for L23 in case it was asserted */
>> +     WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
>> +     /* SERDES_IDDQ = 1 */
>> +     WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
>> +     /* Shutdown PCIe bridge */
>> +     brcm_pcie_bridge_sw_init_set(pcie, 1);
>> +}
>> +
>> +static int brcm_pcie_suspend(struct device *dev)
>> +{
>> +     struct brcm_pcie *pcie = dev_get_drvdata(dev);
>> +
>> +     if (!pcie->bridge_setup_done)
>> +             return 0;
>> +
>> +     turn_off(pcie);
>> +     clk_disable_unprepare(pcie->clk);
>> +     set_regulators(pcie, false);
>> +     pcie->suspended = true;
>> +
>> +     return 0;
>> +}
>> +
>> +static int brcm_pcie_resume(struct device *dev)
>> +{
>> +     struct brcm_pcie *pcie = dev_get_drvdata(dev);
>> +     void __iomem *base;
>> +     int ret;
>> +
>> +     if (!pcie->bridge_setup_done)
>> +             return 0;
>> +
>> +     base = pcie->base;
>> +     set_regulators(pcie, true);
>> +     clk_prepare_enable(pcie->clk);
>> +
>> +     /* Take bridge out of reset so we can access the SERDES reg */
>> +     brcm_pcie_bridge_sw_init_set(pcie, 0);
>> +
>> +     /* SERDES_IDDQ = 0 */
>> +     WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
>> +     /* wait for serdes to be stable */
>> +     usleep_range(100, 200);
>> +
>> +     brcm_pcie_setup_prep(pcie);
>> +
>> +     ret = brcm_pcie_setup_bridge(pcie);
>> +     if (ret)
>> +             return ret;
>> +
>> +     pcie->suspended = false;
>> +
>> +     return 0;
>> +}
>> +
>> +/* Configuration space read/write support */
>> +static int cfg_index(int busnr, int devfn, int reg)
>> +{
>> +     return ((PCI_SLOT(devfn) & 0x1f) << PCI_SLOT_SHIFT)
>> +             | ((PCI_FUNC(devfn) & 0x07) << PCI_FUNC_SHIFT)
>> +             | (busnr << PCI_BUSNUM_SHIFT)
>> +             | (reg & ~3);
>> +}
>> +
>> +static void __iomem *brcm_pci_map_cfg(struct pci_bus *bus, unsigned int devfn,
>> +                                   int where)
>> +{
>> +     struct brcm_pcie *pcie = bus->sysdata;
>> +     void __iomem *base = pcie->base;
>> +     bool rc_access = pci_is_root_bus(bus);
>> +     int idx;
>> +
>> +     if (!is_pcie_link_up(pcie, true))
>> +             return NULL;
>
> Why do you need this test?  It makes this racy because the link could
> go down after you call is_pcie_link_up() but before you perform the
> config access.
We've had a scenario where the EP resets itself and the link is down.
This code recognizes that situation and errors out
instead of making a call that effects an imprecise abort.

>
>> +     base = pcie->base;
>> +     idx = cfg_index(bus->number, devfn, where);
>> +
>> +     bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
>> +
>> +     if (rc_access) {
>> +             if (PCI_SLOT(devfn))
>> +                     return NULL;
>> +             return base + (where & ~3);
>> +     }
>
> Many drivers have a similar pattern.  Please implement this in a
> similar way, e.g., see dw_pcie_valid_device(),
> altera_pcie_valid_device(), rockchip_pcie_valid_device(), etc.
>
>> +     return pcie->base + DATA_ADDR(pcie);
>> +}
>> +
>> +static void __attribute__((__section__("pci_fixup_early")))
>> +brcm_pcibios_fixup(struct pci_dev *dev)
>> +{
>> +     struct brcm_pcie *pcie = dev->bus->sysdata;
>> +     u8 slot = PCI_SLOT(dev->devfn);
>> +
>> +     dev_info(pcie->dev,
>> +              "found device %04x:%04x on bus %d (%s), slot %d (irq %d)\n",
>> +              dev->vendor, dev->device, dev->bus->number, pcie->name,
>> +              slot, of_irq_parse_and_map_pci(dev, slot, 1));
>> +}
>> +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, brcm_pcibios_fixup);
>
> This looks like debug code that should be removed.
>
>> +
>> +static const struct of_device_id brcm_pci_match[] = {
>> +     { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
>> +     { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
>> +     { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
>> +     { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
>> +     {},
>> +};
>> +MODULE_DEVICE_TABLE(of, brcm_pci_match);
>> +
>> +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
>> +{
>> +     turn_off(pcie);
>> +     clk_disable_unprepare(pcie->clk);
>> +     clk_put(pcie->clk);
>> +     set_regulators(pcie, false);
>> +     brcm_pcie_remove_controller(pcie);
>> +}
>> +
>> +static int brcm_pcie_probe(struct platform_device *pdev)
>> +{
>> +     struct device_node *dn = pdev->dev.of_node;
>> +     struct property *pp;
>> +     const struct of_device_id *of_id;
>> +     const struct pcie_cfg_data *data;
>> +     int ret;
>> +     struct brcm_pcie *pcie;
>> +     struct resource *res;
>> +     void __iomem *base;
>> +     u32 tmp;
>> +     struct brcm_dev_pwr_supply *supply;
>> +     struct pci_host_bridge *bridge;
>> +     struct pci_bus *child;
>> +     u32 domain;
>> +
>> +     bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
>> +     if (!bridge)
>> +             return -ENOMEM;
>> +
>> +     pcie = pci_host_bridge_priv(bridge);
>> +     INIT_LIST_HEAD(&pcie->resources);
>> +
>> +     of_id = of_match_node(brcm_pci_match, dn);
>> +     if (!of_id) {
>> +             pr_err("failed to look up compatible string\n");
>
> Please use dev_err(), etc. for every single log message so we can
> associate log messages with a device.
>
>> +             return -EINVAL;
>> +     }
>> +
>> +     if (of_property_read_u32(dn, "dma-ranges", &tmp) == 0) {
>> +             pr_err("cannot yet handle dma-ranges\n");
>> +             return -EINVAL;
>> +     }
>> +
>> +     data = of_id->data;
>> +     pcie->reg_offsets = data->offsets;
>> +     pcie->reg_field_info = data->reg_field_info;
>> +     pcie->type = data->type;
>> +     pcie->dn = dn;
>> +     pcie->dev = &pdev->dev;
>> +
>> +     if (of_property_read_u32(dn, "linux,pci-domain", &domain) == 0) {
>> +             pcie->id = (int)domain;
>> +     } else {
>> +             dev_err(pcie->dev, "linux,pci-domain prop missing\n");
>> +             return -EINVAL;
>> +     }
>
> You should not need this.  This should happen automatically via
> of_get_pci_domain_nr() if you have things set up correctly.
>
>> +
>> +     INIT_LIST_HEAD(&pcie->pwr_supplies);
>> +     for_each_property_of_node(dn, pp) {
>> +             const int n = strlen(pp->name);
>> +
>> +             if (n < 7)
>> +                     continue;
>> +             if (strncmp(pp->name + n - 7, "-supply", 7))
>> +                     continue;
>> +             if (n > sizeof(supply->name) - 1) {
>> +                     dev_err(&pdev->dev, "prop supply name %s too long\n",
>> +                             pp->name);
>> +                     continue;
>> +             }
>> +             supply = devm_kzalloc(&pdev->dev, sizeof(*supply), GFP_KERNEL);
>> +             if (!supply)
>> +                     return -ENOMEM;
>> +             strcpy(supply->name, pp->name);
>> +             supply->name[n - 7] = 0; /* remove "-supply" */
>> +             supply->regulator = devm_regulator_get(&pdev->dev, supply->name);
>> +
>> +             if (IS_ERR(supply->regulator)) {
>> +                     dev_err(&pdev->dev, "Unable to get %s, err=%d\n",
>> +                             pp->name, (int)PTR_ERR(supply->regulator));
>> +                     continue;
>> +             }
>> +             list_add_tail(&supply->node, &pcie->pwr_supplies);
>> +     }
>> +
>> +     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +     if (!res)
>> +             return -EINVAL;
>> +
>> +     base = devm_ioremap_resource(&pdev->dev, res);
>> +     if (IS_ERR(base))
>> +             return PTR_ERR(base);
>> +
>> +     pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
>> +     if (IS_ERR(pcie->clk)) {
>> +             dev_err(&pdev->dev, "could not get clock\n");
>> +             pcie->clk = NULL;
>> +     }
>> +     pcie->base = base;
>> +
>> +     ret = of_pci_get_max_link_speed(dn);
>> +     pcie->gen = (ret < 0) ? 0 : ret;
>> +
>> +     pcie->ssc = of_property_read_bool(dn, "brcm,ssc");
>> +
>> +     ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
>> +     if (ret == 0)
>> +             /* keep going, as we don't use this intr yet */
>> +             dev_warn(pcie->dev, "cannot get pcie interrupt\n");
>> +     else
>> +             pcie->irq = ret;
>> +
>> +     ret = brcm_parse_ranges(pcie);
>> +     if (ret)
>> +             return ret;
>> +
>> +     ret = clk_prepare_enable(pcie->clk);
>> +     if (ret) {
>> +             dev_err(&pdev->dev, "could not enable clock\n");
>> +             return ret;
>> +     }
>> +
>> +     ret = brcm_pcie_add_controller(pcie);
>> +     if (ret)
>> +             return ret;
>> +
>> +     set_regulators(pcie, true);
>> +     brcm_pcie_setup_prep(pcie);
>> +     ret = brcm_pcie_setup_bridge(pcie);
>> +     if (ret)
>> +             goto fail;
>> +
>> +     list_splice_init(&pcie->resources, &bridge->windows);
>> +     bridge->dev.parent = &pdev->dev;
>> +     bridge->busnr = 0;
>> +     bridge->ops = &brcm_pci_ops;
>> +     bridge->sysdata = pcie;
>> +     bridge->map_irq = of_irq_parse_and_map_pci;
>> +     bridge->swizzle_irq = pci_common_swizzle;
>> +
>> +     ret = pci_scan_root_bus_bridge(bridge);
>> +     if (ret < 0) {
>> +             dev_err(pcie->dev, "Scanning root bridge failed");
>> +             goto fail;
>> +     }
>> +
>> +     pci_assign_unassigned_bus_resources(bridge->bus);
>> +     list_for_each_entry(child, &bridge->bus->children, node)
>> +             pcie_bus_configure_settings(child);
>> +     pci_bus_add_devices(bridge->bus);
>> +     platform_set_drvdata(pdev, pcie);
>> +     pcie->root_bus = bridge->bus;
>
> General comment, can you scan some of the other drivers in
> drivers/pci/host/ and follow a similar style?  Similar structure,
> similar function names, similar variable names, etc.  It makes it much
> easier to maintain this whole collection.
>
>> +     return 0;
>> +
>> +fail:
>> +     _brcm_pcie_remove(pcie);
>> +     return ret;
>> +}
>> +
>> +static int brcm_pcie_remove(struct platform_device *pdev)
>> +{
>> +     struct brcm_pcie *pcie = platform_get_drvdata(pdev);
>> +
>> +     pci_stop_root_bus(pcie->root_bus);
>> +     pci_remove_root_bus(pcie->root_bus);
>> +     _brcm_pcie_remove(pcie);
>> +
>> +     return 0;
>> +}
>> +
>> +static const struct dev_pm_ops brcm_pcie_pm_ops = {
>> +     .suspend_noirq = brcm_pcie_suspend,
>> +     .resume_noirq = brcm_pcie_resume,
>> +};
>> +
>> +static struct platform_driver __refdata brcm_pci_driver = {
>> +     .probe = brcm_pcie_probe,
>> +     .remove = brcm_pcie_remove,
>> +     .driver = {
>> +             .name = "brcm-pci",
>> +             .owner = THIS_MODULE,
>> +             .of_match_table = brcm_pci_match,
>> +             .pm = &brcm_pcie_pm_ops,
>> +     },
>> +};
>> +
>> +module_platform_driver(brcm_pci_driver);
>> +
>> +MODULE_LICENSE("GPL");
>> +MODULE_DESCRIPTION("Broadcom STB PCIE RC driver");
>> +MODULE_AUTHOR("Broadcom");
>> diff --git a/drivers/pci/host/pci-brcmstb.h b/drivers/pci/host/pci-brcmstb.h
>> new file mode 100644
>> index 0000000..86f9cd1
>> --- /dev/null
>> +++ b/drivers/pci/host/pci-brcmstb.h
>> @@ -0,0 +1,33 @@
>> +#ifndef __BRCMSTB_PCI_H
>> +#define __BRCMSTB_PCI_H
>> +
>> +/*
>> + * Copyright (C) 2015 - 2017 Broadcom
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#define BRCM_PCIE_NAME_SIZE          8
>> +#define BRCM_INT_PCI_MSI_NR          32
>> +#define BRCM_PCIE_HW_REV_33          0x0303
>> +
>> +/* Broadcom PCIE Offsets */
>> +#define PCIE_INTR2_CPU_BASE          0x4300
>> +
>> +#if defined(CONFIG_MIPS)
>> +/* Broadcom MIPs HW implicitly does the swapping if necessary */
>> +#define bcm_readl(a)         __raw_readl(a)
>> +#define bcm_writel(d, a)     __raw_writel(d, a)
>> +#else
>> +#define bcm_readl(a)         readl(a)
>> +#define bcm_writel(d, a)     writel(d, a)
>> +#endif
>> +
>> +#endif /* __BRCMSTB_PCI_H */
>> --
>> 1.9.0.138.g2de3478
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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[PATCH 4/8] PCI: host: brcmstb: add dma-ranges for inbound traffic

[Jim Quinlan]

The Broadcom STB PCIe host controller is intimately related to the
memory subsystem.  This close relationship adds complexity to how cpu
system memory is mapped to PCIe memory.  Ideally, this mapping is an
identity mapping, or an identity mapping off by a constant.  Not so in
this case.

Consider the Broadcom reference board BCM97445LCC_4X8 which has 6 GB
of system memory.  Here is how the PCIe controller maps the
system memory to PCIe memory:

  memc0-a@[        0....3fffffff] <=> pci@[        0....3fffffff]
  memc0-b@[100000000...13fffffff] <=> pci@[ 40000000....7fffffff]
  memc1-a@[ 40000000....7fffffff] <=> pci@[ 80000000....bfffffff]
  memc1-b@[300000000...33fffffff] <=> pci@[ c0000000....ffffffff]
  memc2-a@[ 80000000....bfffffff] <=> pci@[100000000...13fffffff]
  memc2-b@[c00000000...c3fffffff] <=> pci@[140000000...17fffffff]

Although there are some "gaps" that can be added between the
individual mappings by software, the permutation of memory regions for
the most part is fixed by HW.  The solution of having something close
to an identity mapping is not possible.

The idea behind this HW design is that the same PCIe module can
act as an RC or EP, and if it acts as an EP it concatenates all
of system memory into a BAR so anything can be accessed.  Unfortunately,
when the PCIe block is in the role of an RC it also presents this
"BAR" to downstream PCIe devices, rather than offering an identity map
between its system memory and PCIe space.

Suppose that an endpoint driver allocs some DMA memory.  Suppose this
memory is located at 0x6000_0000, which is in the middle of memc1-a.
The driver wants a dma_addr_t value that it can pass on to the EP to
use.  Without doing any custom mapping, the EP will use this value for
DMA: the driver will get a dma_addr_t equal to 0x6000_0000.  But this
won't work; the device needs a dma_addr_t that reflects the PCIe space
address, namely 0xa000_0000.

So, essentially the solution to this problem must modify the
dma_addr_t returned by the DMA routines routines.  There are two
ways (I know of) of doing this:

(a) overriding/redefining the dma_to_phys() and phys_to_dma() calls
that are used by the dma_ops routines.  This is the approach of

	arch/mips/cavium-octeon/dma-octeon.c

In ARM and ARM64 these two routines are defiend in asm/dma-mapping.h
as static inline functions.

(b) Subscribe to a notifier that notifies when a device is added to a
bus.  When this happens, set_dma_ops() can be called for the device.
This method is mentioned in:

    http://lxr.free-electrons.com/source/drivers/of/platform.c?v=3.16#L152

where it says as a comment

    "In case if platform code need to use own special DMA
    configuration, it can use Platform bus notifier and
    handle BUS_NOTIFY_ADD_DEVICE event to fix up DMA
    configuration."

Solution (b) is what this commit does.  It uses its own set of
dma_ops which are wrappers around the arch_dma_ops.  The
wrappers translate the dma addresses before/after invoking
the arch_dma_ops, as appropriate.

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 drivers/pci/host/Makefile          |   3 +-
 drivers/pci/host/pci-brcmstb-dma.c | 317 +++++++++++++++++++++++++++++++++++++
 drivers/pci/host/pci-brcmstb.c     | 137 ++++++++++++++--
 drivers/pci/host/pci-brcmstb.h     |   6 +
 4 files changed, 449 insertions(+), 14 deletions(-)
 create mode 100644 drivers/pci/host/pci-brcmstb-dma.c

diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 4398d2c..c283321 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -21,7 +21,8 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
-obj-$(CONFIG_PCI_BRCMSTB) += pci-brcmstb.o
+obj-$(CONFIG_PCI_BRCMSTB) += brcmstb-pci.o
+brcmstb-pci-objs := pci-brcmstb.o pci-brcmstb-dma.o
 
 # The following drivers are for devices that use the generic ACPI
 # pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/host/pci-brcmstb-dma.c b/drivers/pci/host/pci-brcmstb-dma.c
new file mode 100644
index 0000000..02c4061
--- /dev/null
+++ b/drivers/pci/host/pci-brcmstb-dma.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (C) 2015-2017 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/smp.h>
+
+#include "pci-brcmstb.h"
+
+static const struct dma_map_ops *arch_dma_ops;
+static const struct dma_map_ops *brcm_dma_ops_ptr;
+
+static dma_addr_t brcm_to_pci(dma_addr_t addr)
+{
+	struct of_pci_range *p;
+
+	if (!num_dma_ranges)
+		return addr;
+
+	for (p = dma_ranges; p < &dma_ranges[num_dma_ranges]; p++)
+		if (addr >= p->cpu_addr && addr < (p->cpu_addr + p->size))
+			return addr - p->cpu_addr + p->pci_addr;
+
+	return addr;
+}
+
+static dma_addr_t brcm_to_cpu(dma_addr_t addr)
+{
+	struct of_pci_range *p;
+
+	if (!num_dma_ranges)
+		return addr;
+
+	for (p = dma_ranges; p < &dma_ranges[num_dma_ranges]; p++)
+		if (addr >= p->pci_addr && addr < (p->pci_addr + p->size))
+			return addr - p->pci_addr + p->cpu_addr;
+
+	return addr;
+}
+
+static void *brcm_alloc(struct device *dev, size_t size, dma_addr_t *handle,
+			gfp_t gfp, unsigned long attrs)
+{
+	void *ret;
+
+	ret = arch_dma_ops->alloc(dev, size, handle, gfp, attrs);
+	if (ret)
+		*handle = brcm_to_pci(*handle);
+	return ret;
+}
+
+static void brcm_free(struct device *dev, size_t size, void *cpu_addr,
+		      dma_addr_t handle, unsigned long attrs)
+{
+	handle = brcm_to_cpu(handle);
+	arch_dma_ops->free(dev, size, cpu_addr, handle, attrs);
+}
+
+static int brcm_mmap(struct device *dev, struct vm_area_struct *vma,
+		     void *cpu_addr, dma_addr_t dma_addr, size_t size,
+		     unsigned long attrs)
+{
+	dma_addr = brcm_to_cpu(dma_addr);
+	return arch_dma_ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
+}
+
+static int brcm_get_sgtable(struct device *dev, struct sg_table *sgt,
+			    void *cpu_addr, dma_addr_t handle, size_t size,
+			    unsigned long attrs)
+{
+	handle = brcm_to_cpu(handle);
+	return arch_dma_ops->get_sgtable(dev, sgt, cpu_addr, handle, size,
+				       attrs);
+}
+
+static dma_addr_t brcm_map_page(struct device *dev, struct page *page,
+				unsigned long offset, size_t size,
+				enum dma_data_direction dir,
+				unsigned long attrs)
+{
+	return brcm_to_pci(arch_dma_ops->map_page(dev, page, offset, size,
+						  dir, attrs));
+}
+
+static void brcm_unmap_page(struct device *dev, dma_addr_t handle,
+			    size_t size, enum dma_data_direction dir,
+			    unsigned long attrs)
+{
+	handle = brcm_to_cpu(handle);
+	arch_dma_ops->unmap_page(dev, handle, size, dir, attrs);
+}
+
+static int brcm_map_sg(struct device *dev, struct scatterlist *sgl,
+		       int nents, enum dma_data_direction dir,
+		       unsigned long attrs)
+{
+	int i, j;
+	struct scatterlist *sg;
+
+	for_each_sg(sgl, sg, nents, i) {
+#ifdef CONFIG_NEED_SG_DMA_LENGTH
+		sg->dma_length = sg->length;
+#endif
+		sg->dma_address =
+			brcm_dma_ops_ptr->map_page(dev, sg_page(sg), sg->offset,
+						   sg->length, dir, attrs);
+		if (dma_mapping_error(dev, sg->dma_address))
+			goto bad_mapping;
+	}
+	return nents;
+
+bad_mapping:
+	for_each_sg(sgl, sg, i, j)
+		brcm_dma_ops_ptr->unmap_page(dev, sg_dma_address(sg),
+					     sg_dma_len(sg), dir, attrs);
+	return 0;
+}
+
+static void brcm_unmap_sg(struct device *dev,
+			  struct scatterlist *sgl, int nents,
+			  enum dma_data_direction dir,
+			  unsigned long attrs)
+{
+	int i;
+	struct scatterlist *sg;
+
+	for_each_sg(sgl, sg, nents, i)
+		brcm_dma_ops_ptr->unmap_page(dev, sg_dma_address(sg),
+					     sg_dma_len(sg), dir, attrs);
+}
+
+static void brcm_sync_single_for_cpu(struct device *dev,
+				     dma_addr_t handle, size_t size,
+				     enum dma_data_direction dir)
+{
+	handle = brcm_to_cpu(handle);
+	arch_dma_ops->sync_single_for_cpu(dev, handle, size, dir);
+}
+
+static void brcm_sync_single_for_device(struct device *dev,
+					dma_addr_t handle, size_t size,
+					enum dma_data_direction dir)
+{
+	handle = brcm_to_cpu(handle);
+	arch_dma_ops->sync_single_for_device(dev, handle, size, dir);
+}
+
+static dma_addr_t brcm_map_resource(struct device *dev, phys_addr_t phys,
+				    size_t size,
+				    enum dma_data_direction dir,
+				    unsigned long attrs)
+{
+	if (arch_dma_ops->map_resource)
+		return brcm_to_pci(arch_dma_ops->map_resource
+				   (dev, phys, size, dir, attrs));
+	return brcm_to_pci((dma_addr_t)phys);
+}
+
+static void brcm_unmap_resource(struct device *dev, dma_addr_t handle,
+				size_t size, enum dma_data_direction dir,
+				unsigned long attrs)
+{
+	if (arch_dma_ops->unmap_resource)
+		arch_dma_ops->unmap_resource(dev, brcm_to_cpu(handle), size,
+					     dir, attrs);
+}
+
+void brcm_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl,
+			  int nents, enum dma_data_direction dir)
+{
+	struct scatterlist *sg;
+	int i;
+
+	for_each_sg(sgl, sg, nents, i)
+		brcm_dma_ops_ptr->sync_single_for_cpu(dev, sg_dma_address(sg),
+						      sg->length, dir);
+}
+
+void brcm_sync_sg_for_device(struct device *dev, struct scatterlist *sgl,
+			     int nents, enum dma_data_direction dir)
+{
+	struct scatterlist *sg;
+	int i;
+
+	for_each_sg(sgl, sg, nents, i)
+		brcm_dma_ops_ptr->sync_single_for_device(dev,
+							 sg_dma_address(sg),
+							 sg->length, dir);
+}
+
+static int brcm_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+	return arch_dma_ops->mapping_error(dev, dma_addr);
+}
+
+static int brcm_dma_supported(struct device *dev, u64 mask)
+{
+	if (num_dma_ranges) {
+		/* It is our translated addresses that the EP will "see", so
+		 * we check all of the ranges for the largest possible value.
+		 */
+		int i;
+
+		for (i = 0; i < num_dma_ranges; i++)
+			if (dma_ranges[i].pci_addr + dma_ranges[i].size - 1
+			    > mask)
+				return 0;
+		return 1;
+	}
+
+	return arch_dma_ops->dma_supported(dev, mask);
+}
+
+#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
+u64 brcm_get_required_mask)(struct device *dev)
+{
+	return arch_dma_ops->get_required_mask(dev);
+}
+#endif
+
+static const struct dma_map_ops brcm_dma_ops = {
+	.alloc			= brcm_alloc,
+	.free			= brcm_free,
+	.mmap			= brcm_mmap,
+	.get_sgtable		= brcm_get_sgtable,
+	.map_page		= brcm_map_page,
+	.unmap_page		= brcm_unmap_page,
+	.map_sg			= brcm_map_sg,
+	.unmap_sg		= brcm_unmap_sg,
+	.map_resource		= brcm_map_resource,
+	.unmap_resource		= brcm_unmap_resource,
+	.sync_single_for_cpu	= brcm_sync_single_for_cpu,
+	.sync_single_for_device	= brcm_sync_single_for_device,
+	.sync_sg_for_cpu	= brcm_sync_sg_for_cpu,
+	.sync_sg_for_device	= brcm_sync_sg_for_device,
+	.mapping_error		= brcm_mapping_error,
+	.dma_supported		= brcm_dma_supported,
+#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
+	.get_required_mask	= brcm_get_required_mask,
+#endif
+};
+
+static void brcm_set_dma_ops(struct device *dev)
+{
+	int ret;
+
+	if (IS_ENABLED(CONFIG_ARM64)) {
+		/* We are going to invoke get_dma_ops().  That
+		 * function, at this point in time, invokes
+		 * get_arch_dma_ops(), and for ARM64 that function
+		 * returns a pointer to dummy_dma_ops.  So then we'd
+		 * like to call arch_setup_dma_ops(), but that isn't
+		 * exported.  Instead, we call of_dma_configure(),
+		 * which is exported, and this calls
+		 * arch_setup_dma_ops().  Once we do this the call to
+		 * get_dma_ops() will work properly because
+		 * dev->dma_ops will be set.
+		 */
+		ret = of_dma_configure(dev, dev->of_node);
+		if (ret) {
+			dev_err(dev, "of_dma_configure() failed: %d\n", ret);
+			return;
+		}
+	}
+
+	arch_dma_ops = get_dma_ops(dev);
+	if (!arch_dma_ops) {
+		dev_err(dev, "failed to get arch_dma_ops\n");
+		return;
+	}
+
+	set_dma_ops(dev, &brcm_dma_ops);
+}
+
+static int brcmstb_platform_notifier(struct notifier_block *nb,
+				     unsigned long event, void *__dev)
+{
+	struct device *dev = __dev;
+
+	brcm_dma_ops_ptr = &brcm_dma_ops;
+	if (event != BUS_NOTIFY_ADD_DEVICE)
+		return NOTIFY_DONE;
+
+	brcm_set_dma_ops(dev);
+	return NOTIFY_OK;
+}
+
+static struct notifier_block brcmstb_platform_nb = {
+	.notifier_call = brcmstb_platform_notifier,
+};
+
+int brcm_register_notifier(void)
+{
+	return bus_register_notifier(&pci_bus_type, &brcmstb_platform_nb);
+}
+
+int brcm_unregister_notifier(void)
+{
+	return bus_unregister_notifier(&pci_bus_type, &brcmstb_platform_nb);
+}
diff --git a/drivers/pci/host/pci-brcmstb.c b/drivers/pci/host/pci-brcmstb.c
index 883b435..f5d80e6 100644
--- a/drivers/pci/host/pci-brcmstb.c
+++ b/drivers/pci/host/pci-brcmstb.c
@@ -341,6 +341,10 @@ struct brcm_pcie {
 	int			id;
 };
 
+/* Also used by pci-brcmstb-dma.c */
+struct of_pci_range *dma_ranges;
+int num_dma_ranges;
+
 static struct list_head brcm_pcie = LIST_HEAD_INIT(brcm_pcie);
 static phys_addr_t scb_size[BRCM_MAX_SCB];
 static int num_memc;
@@ -360,26 +364,43 @@ static u64 roundup_pow_of_two_64(u64 n)
 
 static int brcm_pcie_add_controller(struct brcm_pcie *pcie)
 {
+	int ret = 0;
+
 	mutex_lock(&brcm_pcie_lock);
+	if (list_empty(&brcm_pcie)) {
+		ret = brcm_register_notifier();
+		if (ret) {
+			dev_err(pcie->dev,
+				"failed to register pci bus notifier\n");
+			goto done;
+		}
+	}
 	snprintf(pcie->name, sizeof(pcie->name) - 1, "PCIe%d", pcie->id);
 	list_add_tail(&pcie->list, &brcm_pcie);
+done:
 	mutex_unlock(&brcm_pcie_lock);
-
-	return 0;
+	return ret;
 }
 
 static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
 {
 	struct list_head *pos, *q;
 	struct brcm_pcie *tmp;
+	static const char *err_msg = "failed to unregister pci bus notifier\n";
 
 	mutex_lock(&brcm_pcie_lock);
 	list_for_each_safe(pos, q, &brcm_pcie) {
 		tmp = list_entry(pos, struct brcm_pcie, list);
 		if (tmp == pcie) {
 			list_del(pos);
-			if (list_empty(&brcm_pcie))
+			if (list_empty(&brcm_pcie)) {
+				if (brcm_unregister_notifier())
+					dev_err(pcie->dev, err_msg);
+				kfree(dma_ranges);
+				dma_ranges = NULL;
+				num_dma_ranges = 0;
 				num_memc = 0;
+			}
 			break;
 		}
 	}
@@ -652,6 +673,74 @@ static int brcm_parse_ranges(struct brcm_pcie *pcie)
 	return 0;
 }
 
+static int brcm_pci_dma_range_parser_init(struct of_pci_range_parser *parser,
+					  struct device_node *node)
+{
+	const int na = 3, ns = 2;
+	int rlen;
+
+	parser->node = node;
+	parser->pna = of_n_addr_cells(node);
+	parser->np = parser->pna + na + ns;
+
+	parser->range = of_get_property(node, "dma-ranges", &rlen);
+	if (!parser->range)
+		return -ENOENT;
+
+	parser->end = parser->range + rlen / sizeof(__be32);
+
+	return 0;
+}
+
+static int brcm_parse_dma_ranges(struct brcm_pcie *pcie)
+{
+	int i, ret = 0;
+	struct of_pci_range_parser parser;
+	struct device_node *dn = pcie->dn;
+
+	mutex_lock(&brcm_pcie_lock);
+	if (dma_ranges)
+		goto done;
+
+	/* Parse dma-ranges property if present.  If there are multiple
+	 * PCI controllers, we only have to parse from one of them since
+	 * the others will have an identical mapping.
+	 */
+	if (!brcm_pci_dma_range_parser_init(&parser, dn)) {
+		unsigned int max_ranges
+			= (parser.end - parser.range) / parser.np;
+
+		dma_ranges = kcalloc(max_ranges, sizeof(struct of_pci_range),
+				     GFP_KERNEL);
+		if (!dma_ranges) {
+			ret =  -ENOMEM;
+			goto done;
+		}
+		for (i = 0; of_pci_range_parser_one(&parser, dma_ranges + i);
+		     i++)
+			num_dma_ranges++;
+	}
+
+	for (i = 0, num_memc = 0; i < BRCM_MAX_SCB; i++) {
+		u64 size = brcmstb_memory_memc_size(i);
+
+		if (size == (u64)-1) {
+			dev_err(pcie->dev, "cannot get memc%d size", i);
+			ret = -EINVAL;
+			goto done;
+		} else if (size) {
+			scb_size[i] = roundup_pow_of_two_64(size);
+			num_memc++;
+		} else {
+			break;
+		}
+	}
+
+done:
+	mutex_unlock(&brcm_pcie_lock);
+	return ret;
+}
+
 static void set_regulators(struct brcm_pcie *pcie, bool on)
 {
 	struct list_head *pos;
@@ -728,10 +817,34 @@ static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
 	 */
 	rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
 
-	/* Set simple configuration based on memory sizes
-	 * only.  We always start the viewport at address 0.
-	 */
-	rc_bar2_offset = 0;
+	if (dma_ranges) {
+		/* The best-case scenario is to place the inbound
+		 * region in the first 4GB of pci-space, as some
+		 * legacy devices can only address 32bits.
+		 * We would also like to put the MSI under 4GB
+		 * as well, since some devices require a 32bit
+		 * MSI target address.
+		 */
+		if (total_mem_size <= 0xc0000000ULL &&
+		    rc_bar2_size <= 0x100000000ULL) {
+			rc_bar2_offset = 0;
+		} else {
+			/* The system memory is 4GB or larger so we
+			 * cannot start the inbound region at location
+			 * 0 (since we have to allow some space for
+			 * outbound memory @ 3GB).  So instead we
+			 * start it at the 1x multiple of its size
+			 */
+			rc_bar2_offset = rc_bar2_size;
+		}
+
+	} else {
+		/* Set simple configuration based on memory sizes
+		 * only.  We always start the viewport at address 0,
+		 * and set the MSI target address accordingly.
+		 */
+		rc_bar2_offset = 0;
+	}
 
 	tmp = lower_32_bits(rc_bar2_offset);
 	tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
@@ -1020,7 +1133,6 @@ static int brcm_pcie_probe(struct platform_device *pdev)
 	struct brcm_pcie *pcie;
 	struct resource *res;
 	void __iomem *base;
-	u32 tmp;
 	struct brcm_dev_pwr_supply *supply;
 	struct pci_host_bridge *bridge;
 	struct pci_bus *child;
@@ -1039,11 +1151,6 @@ static int brcm_pcie_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
-	if (of_property_read_u32(dn, "dma-ranges", &tmp) == 0) {
-		pr_err("cannot yet handle dma-ranges\n");
-		return -EINVAL;
-	}
-
 	data = of_id->data;
 	pcie->reg_offsets = data->offsets;
 	pcie->reg_field_info = data->reg_field_info;
@@ -1117,6 +1224,10 @@ static int brcm_pcie_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
+	ret = brcm_parse_dma_ranges(pcie);
+	if (ret)
+		return ret;
+
 	ret = clk_prepare_enable(pcie->clk);
 	if (ret) {
 		dev_err(&pdev->dev, "could not enable clock\n");
diff --git a/drivers/pci/host/pci-brcmstb.h b/drivers/pci/host/pci-brcmstb.h
index 86f9cd1..c3b148a 100644
--- a/drivers/pci/host/pci-brcmstb.h
+++ b/drivers/pci/host/pci-brcmstb.h
@@ -21,6 +21,12 @@
 /* Broadcom PCIE Offsets */
 #define PCIE_INTR2_CPU_BASE		0x4300
 
+int brcm_register_notifier(void);
+int brcm_unregister_notifier(void);
+
+extern struct of_pci_range *dma_ranges;
+extern int num_dma_ranges;
+
 #if defined(CONFIG_MIPS)
 /* Broadcom MIPs HW implicitly does the swapping if necessary */
 #define bcm_readl(a)		__raw_readl(a)
-- 
1.9.0.138.g2de3478

RE: [PATCH 4/8] PCI: host: brcmstb: add dma-ranges for inbound traffic

[David Laight]

From: Jim Quinlan
> Sent: 24 October 2017 19:16
> The Broadcom STB PCIe host controller is intimately related to the
> memory subsystem.  This close relationship adds complexity to how cpu
> system memory is mapped to PCIe memory.  Ideally, this mapping is an
> identity mapping, or an identity mapping off by a constant.  Not so in
> this case.
> 
> Consider the Broadcom reference board BCM97445LCC_4X8 which has 6 GB
> of system memory.  Here is how the PCIe controller maps the
> system memory to PCIe memory:
> 
>   memc0-a@[        0....3fffffff] <=> pci@[        0....3fffffff]
>   memc0-b@[100000000...13fffffff] <=> pci@[ 40000000....7fffffff]
>   memc1-a@[ 40000000....7fffffff] <=> pci@[ 80000000....bfffffff]
>   memc1-b@[300000000...33fffffff] <=> pci@[ c0000000....ffffffff]
>   memc2-a@[ 80000000....bfffffff] <=> pci@[100000000...13fffffff]
>   memc2-b@[c00000000...c3fffffff] <=> pci@[140000000...17fffffff]

I presume the first column is the 'cpu physical address'
and the second the 'pci' address?

...

Isn't this just the same as having an iommu that converts 'bus'
addresses into 'physical' ones?

A simple table lookup of the high address bits will do the
conversion.

	David

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Re: [PATCH 4/8] PCI: host: brcmstb: add dma-ranges for inbound traffic

[Jim Quinlan]

On Wed, Oct 25, 2017 at 5:46 AM, David Laight <David.Laight-JxhZ9S5GRejQT0dZR+AlfA@public.gmane.org> wrote:
> From: Jim QuinlanPCIE_IPROC_MSI
>> Sent: 24 October 2017 19:16
>> The Broadcom STB PCIe host controller is intimately related to the
>> memory subsystem.  This close relationship adds complexity to how cpu
>> system memory is mapped to PCIe memory.  Ideally, this mapping is an
>> identity mapping, or an identity mapping off by a constant.  Not so in
>> this case.
>>
>> Consider the Broadcom reference board BCM97445LCC_4X8 which has 6 GB
>> of system memory.  Here is how the PCIe controller maps the
>> system memory to PCIe memory:
>>
>>   memc0-a@[        0....3fffffff] <=> pci@[        0....3fffffff]
>>   memc0-b@[100000000...13fffffff] <=> pci@[ 40000000....7fffffff]
>>   memc1-a@[ 40000000....7fffffff] <=> pci@[ 80000000....bfffffff]
>>   memc1-b@[300000000...33fffffff] <=> pci@[ c0000000....ffffffff]
>>   memc2-a@[ 80000000....bfffffff] <=> pci@[100000000...13fffffff]
>>   memc2-b@[c00000000...c3fffffff] <=> pci@[140000000...17fffffff]
>
> I presume the first column is the 'cpu physical address'
> and the second the 'pci' address?
>
Yes.  I probably made this more difficult to read because I ordered
the rows by PCI addresses.

> ...
>
> Isn't this just the same as having an iommu that converts 'bus'
> addresses into 'physical' ones?

Pretty much, but for PCIe devices only.  This could be done by somehow
overriding the arch specific phys_to_dma() and dma_to_phys() calls.

>
> A simple table lookup of the high address bits will do the
> conversion.
True, but this table could be passed something like ARM_MAPPING_ERROR,
which may be out the table (the driver is not privy to
ARM_MAPPING_ERROR's definition).

Thanks,
Jim

>
>         David
>
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[PATCH 5/8] PCI/MSI: Enable PCI_MSI_IRQ_DOMAIN support for MIPS

[Jim Quinlan]

Add MIPS as an arch that supports PCI_MSI_IRQ_DOMAIN and add
generation of msi.h in the MIPS arch.

Signed-off-by: Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/mips/include/asm/Kbuild | 1 +
 drivers/pci/Kconfig          | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 7c8aab2..8c78ba7 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -9,6 +9,7 @@ generic-y += irq_work.h
 generic-y += local64.h
 generic-y += mcs_spinlock.h
 generic-y += mm-arch-hooks.h
+generic-y += msi.h
 generic-y += parport.h
 generic-y += percpu.h
 generic-y += preempt.h
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index c32a77f..927c335 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -25,7 +25,7 @@ config PCI_MSI
 	   If you don't know what to do here, say Y.
 
 config PCI_MSI_IRQ_DOMAIN
-	def_bool ARC || ARM || ARM64 || X86
+	def_bool ARC || ARM || ARM64 || MIPS || X86
 	depends on PCI_MSI
 	select GENERIC_MSI_IRQ_DOMAIN
 
-- 
1.9.0.138.g2de3478

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[PATCH 6/8] PCI: host: brcmstb: add MSI capability

[Jim Quinlan]

This commit adds MSI to the Broadcom STB PCIe host controller. It does
not add MSIX since that functionality is not in the HW.  The MSI
controller is physically located within the PCIe block, however, there
is no reason why the MSI controller could not be moved elsewhere in
the future.

Since the internal Brcmstb MSI controller is intertwined with the PCIe
controller, it is not its own platform device but rather part of the
PCIe platform device.

Signed-off-by: Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/pci/host/Kconfig           |  12 ++
 drivers/pci/host/Makefile          |   1 +
 drivers/pci/host/pci-brcmstb-msi.c | 318 +++++++++++++++++++++++++++++++++++++
 drivers/pci/host/pci-brcmstb.c     |  72 +++++++--
 drivers/pci/host/pci-brcmstb.h     |  26 +++
 5 files changed, 419 insertions(+), 10 deletions(-)
 create mode 100644 drivers/pci/host/pci-brcmstb-msi.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index b9b4f11..54aa5d2 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -228,4 +228,16 @@ config PCI_BRCMSTB
 	default ARCH_BRCMSTB || BMIPS_GENERIC
 	help
 	  Adds support for Broadcom Settop Box PCIe host controller.
+	  To compile this driver as a module, choose m here.
+
+config PCI_BRCMSTB_MSI
+	bool "Broadcom Brcmstb PCIe MSI support"
+	depends on ARCH_BRCMSTB || BMIPS_GENERIC
+	depends on OF
+	depends on PCI_MSI
+	default PCI_BRCMSTB
+	help
+	  Say Y here if you want to enable MSI support for Broadcom's iProc
+	  PCIe controller
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index c283321..1026d6f 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCI_BRCMSTB) += brcmstb-pci.o
 brcmstb-pci-objs := pci-brcmstb.o pci-brcmstb-dma.o
+obj-$(CONFIG_PCI_BRCMSTB_MSI) += pci-brcmstb-msi.o
 
 # The following drivers are for devices that use the generic ACPI
 # pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/host/pci-brcmstb-msi.c b/drivers/pci/host/pci-brcmstb-msi.c
new file mode 100644
index 0000000..c805e2f
--- /dev/null
+++ b/drivers/pci/host/pci-brcmstb-msi.c
@@ -0,0 +1,318 @@
+/*
+ * Copyright (C) 2015-2017 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/bitops.h>
+#include <linux/compiler.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/msi.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+
+#include "pci-brcmstb.h"
+
+#define PCIE_MISC_MSI_DATA_CONFIG			0x404c
+#define PCIE_MSI_INTR2_BASE				0x4500
+#define PCIE_MISC_MSI_BAR_CONFIG_LO			0x4044
+#define PCIE_MISC_MSI_BAR_CONFIG_HI			0x4048
+
+/* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */
+#define STATUS				0x0
+#define SET				0x4
+#define CLR				0x8
+#define MASK_STATUS			0xc
+#define MASK_SET			0x10
+#define MASK_CLR			0x14
+
+struct brcm_msi {
+	struct irq_domain *msi_domain;
+	struct irq_domain *inner_domain;
+	struct mutex lock; /* guards the alloc/free operations */
+	u64 target_addr;
+	int irq;
+	/* intr_base is the base pointer for interrupt status/set/clr regs */
+	void __iomem *intr_base;
+	/* intr_legacy_mask indicates how many bits are MSI interrupts */
+	u32 intr_legacy_mask;
+	/* intr_legacy_offset indicates bit position of MSI_01. It is
+	 * to map the register bit position to a hwirq that starts at 0.
+	 */
+	u32 intr_legacy_offset;
+	/* used indicates which MSI interrupts have been alloc'd */
+	unsigned long used;
+
+	void __iomem *base;
+	struct device *dev;
+	struct device_node *dn;
+	unsigned int rev;
+};
+
+static struct irq_chip brcm_msi_irq_chip = {
+	.name = "Brcm_MSI",
+	.irq_mask = pci_msi_mask_irq,
+	.irq_unmask = pci_msi_unmask_irq,
+};
+
+static struct msi_domain_info brcm_msi_domain_info = {
+	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+		   MSI_FLAG_PCI_MSIX),
+	.chip	= &brcm_msi_irq_chip,
+};
+
+static void brcm_pcie_msi_isr(struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	struct brcm_msi *msi;
+	unsigned long status, virq;
+	u32 mask, bit, hwirq;
+
+	chained_irq_enter(chip, desc);
+	msi = irq_desc_get_handler_data(desc);
+	mask = msi->intr_legacy_mask;
+
+	while ((status = bcm_readl(msi->intr_base + STATUS) & mask)) {
+		for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) {
+			/* clear the interrupt */
+			bcm_writel(1 << bit, msi->intr_base + CLR);
+
+			/* Account for legacy interrupt offset */
+			hwirq = bit - msi->intr_legacy_offset;
+
+			virq = irq_find_mapping(msi->inner_domain, hwirq);
+			if (virq) {
+				if (msi->used & (1 << hwirq))
+					generic_handle_irq(virq);
+				else
+					dev_info(msi->dev, "unhandled MSI %d\n",
+						 hwirq);
+			} else {
+				/* Unknown MSI, just clear it */
+				dev_dbg(msi->dev, "unexpected MSI\n");
+			}
+		}
+	}
+	chained_irq_exit(chip, desc);
+}
+
+static void brcm_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+	struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
+	u32 temp;
+
+	msg->address_lo = lower_32_bits(msi->target_addr);
+	msg->address_hi = upper_32_bits(msi->target_addr);
+	temp = bcm_readl(msi->base + PCIE_MISC_MSI_DATA_CONFIG);
+	msg->data = ((temp >> 16) & (temp & 0xffff)) | data->hwirq;
+}
+
+static int brcm_msi_set_affinity(struct irq_data *irq_data,
+				 const struct cpumask *mask, bool force)
+{
+	return -EINVAL;
+}
+
+static struct irq_chip brcm_msi_bottom_irq_chip = {
+	.name			= "Brcm MSI",
+	.irq_compose_msi_msg	= brcm_compose_msi_msg,
+	.irq_set_affinity	= brcm_msi_set_affinity,
+};
+
+static int brcm_msi_alloc(struct brcm_msi *msi)
+{
+	int bit, hwirq;
+
+	mutex_lock(&msi->lock);
+	bit = ~msi->used ? ffz(msi->used) : -1;
+
+	if (bit >= 0 && bit < BRCM_INT_PCI_MSI_NR) {
+		msi->used |= (1 << bit);
+		hwirq = bit - msi->intr_legacy_offset;
+	} else {
+		hwirq = -ENOSPC;
+	}
+
+	mutex_unlock(&msi->lock);
+	return hwirq;
+}
+
+static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
+{
+	mutex_lock(&msi->lock);
+	msi->used &= ~(1 << (hwirq + msi->intr_legacy_offset));
+	mutex_unlock(&msi->lock);
+}
+
+static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+				 unsigned int nr_irqs, void *args)
+{
+	struct brcm_msi *msi = domain->host_data;
+	int hwirq;
+
+	hwirq = brcm_msi_alloc(msi);
+
+	if (hwirq < 0)
+		return hwirq;
+
+	irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
+			    &brcm_msi_bottom_irq_chip, domain->host_data,
+			    handle_simple_irq, NULL, NULL);
+	return 0;
+}
+
+static void brcm_irq_domain_free(struct irq_domain *domain,
+				 unsigned int virq, unsigned int nr_irqs)
+{
+	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
+	struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
+
+	brcm_msi_free(msi, d->hwirq);
+}
+
+void brcm_msi_set_regs(struct brcm_msi *msi)
+{
+	u32 data_val, msi_lo, msi_hi;
+
+	if (msi->rev >= BRCM_PCIE_HW_REV_33) {
+		/* ffe0 -- least sig 5 bits are 0 indicating 32 msgs
+		 * 6540 -- this is our arbitrary unique data value
+		 */
+		data_val = 0xffe06540;
+	} else {
+		/* fff8 -- least sig 3 bits are 0 indicating 8 msgs
+		 * 6540 -- this is our arbitrary unique data value
+		 */
+		data_val = 0xfff86540;
+	}
+
+	/* Make sure we are not masking MSIs.  Note that MSIs can be masked,
+	 * but that occurs on the PCIe EP device
+	 */
+	bcm_writel(0xffffffff & msi->intr_legacy_mask,
+		   msi->intr_base + MASK_CLR);
+
+	msi_lo = lower_32_bits(msi->target_addr);
+	msi_hi = upper_32_bits(msi->target_addr);
+	/* The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
+	 * enable, which we set to 1.
+	 */
+	bcm_writel(msi_lo | 1, msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
+	bcm_writel(msi_hi, msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
+	bcm_writel(data_val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
+}
+EXPORT_SYMBOL(brcm_msi_set_regs);
+
+static const struct irq_domain_ops msi_domain_ops = {
+	.alloc	= brcm_irq_domain_alloc,
+	.free	= brcm_irq_domain_free,
+};
+
+static int brcm_allocate_domains(struct brcm_msi *msi)
+{
+	struct fwnode_handle *fwnode = of_node_to_fwnode(msi->dn);
+
+	msi->inner_domain = irq_domain_add_linear(NULL, BRCM_INT_PCI_MSI_NR,
+						  &msi_domain_ops, msi);
+	if (!msi->inner_domain) {
+		dev_err(msi->dev, "failed to create IRQ domain\n");
+		return -ENOMEM;
+	}
+
+	msi->msi_domain = pci_msi_create_irq_domain(fwnode,
+						    &brcm_msi_domain_info,
+						    msi->inner_domain);
+	if (!msi->msi_domain) {
+		dev_err(msi->dev, "failed to create MSI domain\n");
+		irq_domain_remove(msi->inner_domain);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static void brcm_free_domains(struct brcm_msi *msi)
+{
+	irq_domain_remove(msi->msi_domain);
+	irq_domain_remove(msi->inner_domain);
+}
+
+void brcm_msi_remove(struct brcm_msi *msi)
+{
+	if (!msi)
+		return;
+	irq_set_chained_handler(msi->irq, NULL);
+	irq_set_handler_data(msi->irq, NULL);
+	brcm_free_domains(msi);
+}
+EXPORT_SYMBOL(brcm_msi_remove);
+
+int brcm_msi_probe(struct platform_device *pdev, struct brcm_info *info)
+{
+	struct brcm_msi *msi;
+	int irq, ret;
+
+	irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
+	if (irq <= 0) {
+		dev_err(&pdev->dev, "cannot map msi intr\n");
+		return -ENODEV;
+	}
+
+	msi = devm_kzalloc(&pdev->dev, sizeof(struct brcm_msi), GFP_KERNEL);
+	if (!msi)
+		return -ENOMEM;
+
+	msi->dev = &pdev->dev;
+	msi->base = info->base;
+	msi->rev =  info->rev;
+	msi->dn = pdev->dev.of_node;
+	msi->target_addr = info->msi_target_addr;
+	msi->irq = irq;
+
+	ret = brcm_allocate_domains(msi);
+	if (ret)
+		return ret;
+
+	irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
+
+	if (msi->rev >= BRCM_PCIE_HW_REV_33) {
+		msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
+		/* This version of PCIe hw has only 32 intr bits
+		 * starting at bit position 0.
+		 */
+		msi->intr_legacy_mask = 0xffffffff;
+		msi->intr_legacy_offset = 0x0;
+		msi->used = 0x0;
+
+	} else {
+		msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
+		/* This version of PCIe hw has only 8 intr bits starting
+		 * at bit position 24.
+		 */
+		msi->intr_legacy_mask = 0xff000000;
+		msi->intr_legacy_offset = 24;
+		msi->used = 0x00ffffff;
+	}
+
+	brcm_msi_set_regs(msi);
+	info->msi = msi;
+
+	return 0;
+}
+EXPORT_SYMBOL(brcm_msi_probe);
diff --git a/drivers/pci/host/pci-brcmstb.c b/drivers/pci/host/pci-brcmstb.c
index f5d80e6..99900d9 100644
--- a/drivers/pci/host/pci-brcmstb.c
+++ b/drivers/pci/host/pci-brcmstb.c
@@ -22,6 +22,7 @@
 #include <linux/list.h>
 #include <linux/log2.h>
 #include <linux/module.h>
+#include <linux/msi.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_pci.h>
@@ -327,10 +328,13 @@ struct brcm_pcie {
 	int			num_out_wins;
 	bool			ssc;
 	int			gen;
+	u64			msi_target_addr;
 	struct brcm_window	out_wins[BRCM_NUM_PCI_OUT_WINS];
 	struct list_head	resources;
 	struct device		*dev;
 	struct list_head	pwr_supplies;
+	struct brcm_msi		*msi;
+	bool			msi_internal;
 	unsigned int		rev;
 	unsigned int		num;
 	bool			bridge_setup_done;
@@ -763,6 +767,7 @@ static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
 	void __iomem *base = pcie->base;
 	unsigned int scb_size_val;
 	u64 rc_bar2_size = 0, rc_bar2_offset = 0, total_mem_size = 0;
+	u64 msi_target_addr;
 	u32 tmp, burst;
 	int i;
 
@@ -806,14 +811,17 @@ static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
 	/* The PCI host controller by design must set the inbound
 	 * viewport to be a contiguous arrangement of all of the
 	 * system's memory.  In addition, its size mut be a power of
-	 * two.  To further complicate matters, the viewport must
-	 * start on a pci-address that is aligned on a multiple of its
-	 * size.  If a portion of the viewport does not represent
-	 * system memory -- e.g. 3GB of memory requires a 4GB viewport
-	 * -- we can map the outbound memory in or after 3GB and even
-	 * though the viewport will overlap the outbound memory the
-	 * controller will know to send outbound memory downstream and
-	 * everything else upstream.
+	 * two.  Further, the MSI target address must NOT be placed
+	 * inside this region, as the decoding logic will consider its
+	 * address to be inbound memory traffic.  To further
+	 * complicate matters, the viewport must start on a
+	 * pci-address that is aligned on a multiple of its size.
+	 * If a portion of the viewport does not represent system
+	 * memory -- e.g. 3GB of memory requires a 4GB viewport --
+	 * we can map the outbound memory in or after 3GB and even
+	 * though the viewport will overlap the outbound memory
+	 * the controller will know to send outbound memory downstream
+	 * and everything else upstream.
 	 */
 	rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
 
@@ -828,6 +836,14 @@ static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
 		if (total_mem_size <= 0xc0000000ULL &&
 		    rc_bar2_size <= 0x100000000ULL) {
 			rc_bar2_offset = 0;
+			/* If the viewport is less then 4GB we can fit
+			 * the MSI target address under 4GB. Otherwise
+			 * put it right below 64GB.
+			 */
+			msi_target_addr =
+				(rc_bar2_size == 0x100000000ULL)
+				? BRCM_MSI_TARGET_ADDR_GT_4GB
+				: BRCM_MSI_TARGET_ADDR_LT_4GB;
 		} else {
 			/* The system memory is 4GB or larger so we
 			 * cannot start the inbound region at location
@@ -836,15 +852,24 @@ static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
 			 * start it at the 1x multiple of its size
 			 */
 			rc_bar2_offset = rc_bar2_size;
-		}
 
+			/* Since we are starting the viewport at 4GB or
+			 * higher, put the MSI target address below 4GB
+			 */
+			msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
+		}
 	} else {
 		/* Set simple configuration based on memory sizes
 		 * only.  We always start the viewport at address 0,
 		 * and set the MSI target address accordingly.
 		 */
 		rc_bar2_offset = 0;
+
+		msi_target_addr = (rc_bar2_size >= 0x100000000ULL)
+			? BRCM_MSI_TARGET_ADDR_GT_4GB
+			: BRCM_MSI_TARGET_ADDR_LT_4GB;
 	}
+	pcie->msi_target_addr = msi_target_addr;
 
 	tmp = lower_32_bits(rc_bar2_offset);
 	tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
@@ -1053,6 +1078,9 @@ static int brcm_pcie_resume(struct device *dev)
 	if (ret)
 		return ret;
 
+	if (pcie->msi && pcie->msi_internal)
+		brcm_msi_set_regs(pcie->msi);
+
 	pcie->suspended = false;
 
 	return 0;
@@ -1116,6 +1144,7 @@ static void __attribute__((__section__("pci_fixup_early")))
 
 static void _brcm_pcie_remove(struct brcm_pcie *pcie)
 {
+	brcm_msi_remove(pcie->msi);
 	turn_off(pcie);
 	clk_disable_unprepare(pcie->clk);
 	clk_put(pcie->clk);
@@ -1125,7 +1154,7 @@ static void _brcm_pcie_remove(struct brcm_pcie *pcie)
 
 static int brcm_pcie_probe(struct platform_device *pdev)
 {
-	struct device_node *dn = pdev->dev.of_node;
+	struct device_node *dn = pdev->dev.of_node, *msi_dn;
 	struct property *pp;
 	const struct of_device_id *of_id;
 	const struct pcie_cfg_data *data;
@@ -1244,6 +1273,29 @@ static int brcm_pcie_probe(struct platform_device *pdev)
 	if (ret)
 		goto fail;
 
+	msi_dn = of_parse_phandle(pcie->dn, "msi-parent", 0);
+	/* Use the internal MSI if no msi-parent property */
+	if (!msi_dn)
+		msi_dn = pcie->dn;
+
+	if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_enabled()
+	    && msi_dn == pcie->dn) {
+		struct brcm_info info;
+
+		info.rev = pcie->rev;
+		info.msi_target_addr = pcie->msi_target_addr;
+		info.base = pcie->base;
+
+		ret = brcm_msi_probe(pdev, &info);
+		if (ret)
+			dev_err(pcie->dev,
+				"probe of internal MSI failed: %d)", ret);
+		else
+			pcie->msi_internal = true;
+
+		pcie->msi = info.msi;
+	}
+
 	list_splice_init(&pcie->resources, &bridge->windows);
 	bridge->dev.parent = &pdev->dev;
 	bridge->busnr = 0;
diff --git a/drivers/pci/host/pci-brcmstb.h b/drivers/pci/host/pci-brcmstb.h
index c3b148a..f969c2a 100644
--- a/drivers/pci/host/pci-brcmstb.h
+++ b/drivers/pci/host/pci-brcmstb.h
@@ -27,6 +27,32 @@
 extern struct of_pci_range *dma_ranges;
 extern int num_dma_ranges;
 
+struct brcm_msi;
+struct brcm_info;
+struct platform_device;
+
+#ifdef CONFIG_PCI_BRCMSTB_MSI
+int brcm_msi_probe(struct platform_device *pdev, struct brcm_info *info);
+void brcm_msi_set_regs(struct brcm_msi *chip);
+void brcm_msi_remove(struct brcm_msi *chip);
+#else
+static inline int brcm_msi_probe(struct platform_device *pdev,
+				 struct brcm_info *info)
+{
+	return -ENODEV;
+}
+
+static inline void brcm_msi_set_regs(struct brcm_msi *chip) {}
+static inline void brcm_msi_remove(struct brcm_msi *chip) {}
+#endif /* CONFIG_PCI_BRCMSTB_MSI */
+
+struct brcm_info {
+	int rev;
+	u64 msi_target_addr;
+	void __iomem *base;
+	struct brcm_msi *msi;
+};
+
 #if defined(CONFIG_MIPS)
 /* Broadcom MIPs HW implicitly does the swapping if necessary */
 #define bcm_readl(a)		__raw_readl(a)
-- 
1.9.0.138.g2de3478

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Re: [PATCH 6/8] PCI: host: brcmstb: add MSI capability

[Florian Fainelli]

Hi Jim,

On 10/24/2017 11:15 AM, Jim Quinlan wrote:
> This commit adds MSI to the Broadcom STB PCIe host controller. It does
> not add MSIX since that functionality is not in the HW.  The MSI
> controller is physically located within the PCIe block, however, there
> is no reason why the MSI controller could not be moved elsewhere in
> the future.
> 
> Since the internal Brcmstb MSI controller is intertwined with the PCIe
> controller, it is not its own platform device but rather part of the
> PCIe platform device.
> 
> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> ---
>  drivers/pci/host/Kconfig           |  12 ++
>  drivers/pci/host/Makefile          |   1 +
>  drivers/pci/host/pci-brcmstb-msi.c | 318 +++++++++++++++++++++++++++++++++++++
>  drivers/pci/host/pci-brcmstb.c     |  72 +++++++--
>  drivers/pci/host/pci-brcmstb.h     |  26 +++
>  5 files changed, 419 insertions(+), 10 deletions(-)
>  create mode 100644 drivers/pci/host/pci-brcmstb-msi.c
> 
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index b9b4f11..54aa5d2 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -228,4 +228,16 @@ config PCI_BRCMSTB
>  	default ARCH_BRCMSTB || BMIPS_GENERIC
>  	help
>  	  Adds support for Broadcom Settop Box PCIe host controller.
> +	  To compile this driver as a module, choose m here.
> +
> +config PCI_BRCMSTB_MSI
> +	bool "Broadcom Brcmstb PCIe MSI support"
> +	depends on ARCH_BRCMSTB || BMIPS_GENERIC

This could probably be depends on PCI_BRCMSTB, which would imply these
two conditions. PCI_BRCMSTB_MSI on its own is probably not very useful
without the parent RC driver.

> +	depends on OF
> +	depends on PCI_MSI
> +	default PCI_BRCMSTB
> +	help
> +	  Say Y here if you want to enable MSI support for Broadcom's iProc
> +	  PCIe controller
> +
>  endmenu
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index c283321..1026d6f 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -23,6 +23,7 @@ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>  obj-$(CONFIG_VMD) += vmd.o
>  obj-$(CONFIG_PCI_BRCMSTB) += brcmstb-pci.o
>  brcmstb-pci-objs := pci-brcmstb.o pci-brcmstb-dma.o
> +obj-$(CONFIG_PCI_BRCMSTB_MSI) += pci-brcmstb-msi.o

Should we combine this file with the brcmstb-pci.o? There is probably no
functional difference, except that pci-brcmstb-msi.ko needs to be loaded
first, right?
-- 
Florian

Re: [PATCH 6/8] PCI: host: brcmstb: add MSI capability

[Jim Quinlan]

On Tue, Oct 24, 2017 at 2:57 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> Hi Jim,
>
> On 10/24/2017 11:15 AM, Jim Quinlan wrote:
>> This commit adds MSI to the Broadcom STB PCIe host controller. It does
>> not add MSIX since that functionality is not in the HW.  The MSI
>> controller is physically located within the PCIe block, however, there
>> is no reason why the MSI controller could not be moved elsewhere in
>> the future.
>>
>> Since the internal Brcmstb MSI controller is intertwined with the PCIe
>> controller, it is not its own platform device but rather part of the
>> PCIe platform device.
>>
>> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
>> ---
>>  drivers/pci/host/Kconfig           |  12 ++
>>  drivers/pci/host/Makefile          |   1 +
>>  drivers/pci/host/pci-brcmstb-msi.c | 318 +++++++++++++++++++++++++++++++++++++
>>  drivers/pci/host/pci-brcmstb.c     |  72 +++++++--
>>  drivers/pci/host/pci-brcmstb.h     |  26 +++
>>  5 files changed, 419 insertions(+), 10 deletions(-)
>>  create mode 100644 drivers/pci/host/pci-brcmstb-msi.c
>>
>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> index b9b4f11..54aa5d2 100644
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>> @@ -228,4 +228,16 @@ config PCI_BRCMSTB
>>       default ARCH_BRCMSTB || BMIPS_GENERIC
>>       help
>>         Adds support for Broadcom Settop Box PCIe host controller.
>> +       To compile this driver as a module, choose m here.
>> +
>> +config PCI_BRCMSTB_MSI
>> +     bool "Broadcom Brcmstb PCIe MSI support"
>> +     depends on ARCH_BRCMSTB || BMIPS_GENERIC
>
> This could probably be depends on PCI_BRCMSTB, which would imply these
> two conditions. PCI_BRCMSTB_MSI on its own is probably not very useful
> without the parent RC driver.
>
>> +     depends on OF
>> +     depends on PCI_MSI
>> +     default PCI_BRCMSTB
>> +     help
>> +       Say Y here if you want to enable MSI support for Broadcom's iProc
>> +       PCIe controller
>> +
>>  endmenu
>> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
>> index c283321..1026d6f 100644
>> --- a/drivers/pci/host/Makefile
>> +++ b/drivers/pci/host/Makefile
>> @@ -23,6 +23,7 @@ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>>  obj-$(CONFIG_VMD) += vmd.o
>>  obj-$(CONFIG_PCI_BRCMSTB) += brcmstb-pci.o
>>  brcmstb-pci-objs := pci-brcmstb.o pci-brcmstb-dma.o
>> +obj-$(CONFIG_PCI_BRCMSTB_MSI) += pci-brcmstb-msi.o
>
> Should we combine this file with the brcmstb-pci.o? There is probably no
> functional difference, except that pci-brcmstb-msi.ko needs to be loaded
> first, right?
> --
> Florian

If you look at the pci/host/Kconfig you will see that other drivers
also have a separate MSI config (eg iproc, altera, xgene) so there is
precedent.  The reason that pci-brcmstb-msi.c is its own file is
because it depends on an irq function that is not exported.  That is
why CONFIG_PCI_BRCMSTB_MSI is bool, and CONFIG_PCI_BRCMSTB is
tristate.  -- Jim

Re: [PATCH 6/8] PCI: host: brcmstb: add MSI capability

[Bjorn Helgaas]

[+cc Ray, Scott, Jon]

On Wed, Oct 25, 2017 at 11:28:07AM -0400, Jim Quinlan wrote:
> On Tue, Oct 24, 2017 at 2:57 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> > Hi Jim,
> >
> > On 10/24/2017 11:15 AM, Jim Quinlan wrote:
> >> This commit adds MSI to the Broadcom STB PCIe host controller. It does
> >> not add MSIX since that functionality is not in the HW.  The MSI
> >> controller is physically located within the PCIe block, however, there
> >> is no reason why the MSI controller could not be moved elsewhere in
> >> the future.
> >>
> >> Since the internal Brcmstb MSI controller is intertwined with the PCIe
> >> controller, it is not its own platform device but rather part of the
> >> PCIe platform device.
> >>
> >> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> >> ---
> >>  drivers/pci/host/Kconfig           |  12 ++
> >>  drivers/pci/host/Makefile          |   1 +
> >>  drivers/pci/host/pci-brcmstb-msi.c | 318 +++++++++++++++++++++++++++++++++++++
> >>  drivers/pci/host/pci-brcmstb.c     |  72 +++++++--
> >>  drivers/pci/host/pci-brcmstb.h     |  26 +++
> >>  5 files changed, 419 insertions(+), 10 deletions(-)
> >>  create mode 100644 drivers/pci/host/pci-brcmstb-msi.c
> >>
> >> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> >> index b9b4f11..54aa5d2 100644
> >> --- a/drivers/pci/host/Kconfig
> >> +++ b/drivers/pci/host/Kconfig
> >> @@ -228,4 +228,16 @@ config PCI_BRCMSTB
> >>       default ARCH_BRCMSTB || BMIPS_GENERIC
> >>       help
> >>         Adds support for Broadcom Settop Box PCIe host controller.
> >> +       To compile this driver as a module, choose m here.
> >> +
> >> +config PCI_BRCMSTB_MSI
> >> +     bool "Broadcom Brcmstb PCIe MSI support"
> >> +     depends on ARCH_BRCMSTB || BMIPS_GENERIC
> >
> > This could probably be depends on PCI_BRCMSTB, which would imply these
> > two conditions. PCI_BRCMSTB_MSI on its own is probably not very useful
> > without the parent RC driver.
> >
> >> +     depends on OF
> >> +     depends on PCI_MSI
> >> +     default PCI_BRCMSTB
> >> +     help
> >> +       Say Y here if you want to enable MSI support for Broadcom's iProc
> >> +       PCIe controller
> >> +
> >>  endmenu
> >> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> >> index c283321..1026d6f 100644
> >> --- a/drivers/pci/host/Makefile
> >> +++ b/drivers/pci/host/Makefile
> >> @@ -23,6 +23,7 @@ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> >>  obj-$(CONFIG_VMD) += vmd.o
> >>  obj-$(CONFIG_PCI_BRCMSTB) += brcmstb-pci.o
> >>  brcmstb-pci-objs := pci-brcmstb.o pci-brcmstb-dma.o
> >> +obj-$(CONFIG_PCI_BRCMSTB_MSI) += pci-brcmstb-msi.o
> >
> > Should we combine this file with the brcmstb-pci.o? There is probably no
> > functional difference, except that pci-brcmstb-msi.ko needs to be loaded
> > first, right?
> > --
> > Florian
> 
> If you look at the pci/host/Kconfig you will see that other drivers
> also have a separate MSI config (eg iproc, altera, xgene) so there is
> precedent.  The reason that pci-brcmstb-msi.c is its own file is
> because it depends on an irq function that is not exported.  That is
> why CONFIG_PCI_BRCMSTB_MSI is bool, and CONFIG_PCI_BRCMSTB is
> tristate.  -- Jim

There is precedent, but that doesn't mean I like it :)
I would strongly prefer one file per driver when possible.

Take iproc for example.  iproc-msi.c is enabled by a Kconfig bool.  It
contains a bunch of code with the only external entry points being
iproc_msi_init() and iproc_msi_exit().  These are only called via
iproc_pcie_bcma_probe() or iproc_pcie_pltfm_probe(), both of which are
tristate.  So iproc-msi.c is only compiled if CONFIG_IPROC_BCMA or
CONFIG_IPROC_PLATFORM are enabled, but all that text is loaded even if
neither module is loaded, which seems suboptimal.

I don't care if you have several config options to enable the BCMA
probe and the platform probe (although these could probably be
replaced in the code by a simple "#ifdef CONFIG_BCMA" and "#ifdef
CONFIG_OF"), and making CONFIG_PCIE_IPROC tristate so it can be a
module makes sense.  But I think it would be better to put all the
code in one file instead of five, and probably remove
CONFIG_PCIE_IPROC_MSI.  Maybe this requires exporting some IRQ
function that currently isn't exported.  But that seems like a simpler
solution than what we currently have.

Bjorn

Re: [PATCH 6/8] PCI: host: brcmstb: add MSI capability

[Scott Branden]

Hi Bjorn,


On 17-10-25 10:23 AM, Bjorn Helgaas wrote:
> [+cc Ray, Scott, Jon]
>
> On Wed, Oct 25, 2017 at 11:28:07AM -0400, Jim Quinlan wrote:
>> On Tue, Oct 24, 2017 at 2:57 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
>>> Hi Jim,
>>>
>>> On 10/24/2017 11:15 AM, Jim Quinlan wrote:
>>>> This commit adds MSI to the Broadcom STB PCIe host controller. It does
>>>> not add MSIX since that functionality is not in the HW.  The MSI
>>>> controller is physically located within the PCIe block, however, there
>>>> is no reason why the MSI controller could not be moved elsewhere in
>>>> the future.
>>>>
>>>> Since the internal Brcmstb MSI controller is intertwined with the PCIe
>>>> controller, it is not its own platform device but rather part of the
>>>> PCIe platform device.
>>>>
>>>> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
>>>> ---
>>>>   drivers/pci/host/Kconfig           |  12 ++
>>>>   drivers/pci/host/Makefile          |   1 +
>>>>   drivers/pci/host/pci-brcmstb-msi.c | 318 +++++++++++++++++++++++++++++++++++++
>>>>   drivers/pci/host/pci-brcmstb.c     |  72 +++++++--
>>>>   drivers/pci/host/pci-brcmstb.h     |  26 +++
>>>>   5 files changed, 419 insertions(+), 10 deletions(-)
>>>>   create mode 100644 drivers/pci/host/pci-brcmstb-msi.c
>>>>
>>>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>>>> index b9b4f11..54aa5d2 100644
>>>> --- a/drivers/pci/host/Kconfig
>>>> +++ b/drivers/pci/host/Kconfig
>>>> @@ -228,4 +228,16 @@ config PCI_BRCMSTB
>>>>        default ARCH_BRCMSTB || BMIPS_GENERIC
>>>>        help
>>>>          Adds support for Broadcom Settop Box PCIe host controller.
>>>> +       To compile this driver as a module, choose m here.
>>>> +
>>>> +config PCI_BRCMSTB_MSI
>>>> +     bool "Broadcom Brcmstb PCIe MSI support"
>>>> +     depends on ARCH_BRCMSTB || BMIPS_GENERIC
>>> This could probably be depends on PCI_BRCMSTB, which would imply these
>>> two conditions. PCI_BRCMSTB_MSI on its own is probably not very useful
>>> without the parent RC driver.
>>>
>>>> +     depends on OF
>>>> +     depends on PCI_MSI
>>>> +     default PCI_BRCMSTB
>>>> +     help
>>>> +       Say Y here if you want to enable MSI support for Broadcom's iProc
>>>> +       PCIe controller
>>>> +
>>>>   endmenu
>>>> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
>>>> index c283321..1026d6f 100644
>>>> --- a/drivers/pci/host/Makefile
>>>> +++ b/drivers/pci/host/Makefile
>>>> @@ -23,6 +23,7 @@ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>>>>   obj-$(CONFIG_VMD) += vmd.o
>>>>   obj-$(CONFIG_PCI_BRCMSTB) += brcmstb-pci.o
>>>>   brcmstb-pci-objs := pci-brcmstb.o pci-brcmstb-dma.o
>>>> +obj-$(CONFIG_PCI_BRCMSTB_MSI) += pci-brcmstb-msi.o
>>> Should we combine this file with the brcmstb-pci.o? There is probably no
>>> functional difference, except that pci-brcmstb-msi.ko needs to be loaded
>>> first, right?
>>> --
>>> Florian
>> If you look at the pci/host/Kconfig you will see that other drivers
>> also have a separate MSI config (eg iproc, altera, xgene) so there is
>> precedent.  The reason that pci-brcmstb-msi.c is its own file is
>> because it depends on an irq function that is not exported.  That is
>> why CONFIG_PCI_BRCMSTB_MSI is bool, and CONFIG_PCI_BRCMSTB is
>> tristate.  -- Jim
> There is precedent, but that doesn't mean I like it :)
> I would strongly prefer one file per driver when possible.
>
> Take iproc for example.  iproc-msi.c is enabled by a Kconfig bool.  It
> contains a bunch of code with the only external entry points being
> iproc_msi_init() and iproc_msi_exit().  These are only called via
> iproc_pcie_bcma_probe() or iproc_pcie_pltfm_probe(), both of which are
> tristate.  So iproc-msi.c is only compiled if CONFIG_IPROC_BCMA or
> CONFIG_IPROC_PLATFORM are enabled, but all that text is loaded even if
> neither module is loaded, which seems suboptimal.
>
> I don't care if you have several config options to enable the BCMA
> probe and the platform probe (although these could probably be
> replaced in the code by a simple "#ifdef CONFIG_BCMA" and "#ifdef
> CONFIG_OF"), and making CONFIG_PCIE_IPROC tristate so it can be a
> module makes sense.  But I think it would be better to put all the
> code in one file instead of five, and probably remove
> CONFIG_PCIE_IPROC_MSI.  Maybe this requires exporting some IRQ
> function that currently isn't exported.  But that seems like a simpler
> solution than what we currently have.
Placing pcie-iproc-bcma.c in its own file is useful in being able to 
read the code that is actually used.  BCMA is really unnecessary if a 
few platforms stopped using BCMA and declared everything via devicetree 
or ACPI.  Same with pcie-iproc-platform.c.  Both keep the mess out of 
pcie-iproc.c.

It looks like pcie-iproc-msi.c followed existing pci drivers in place.  
So if msi was cleaned up through the entire pci drivers then yes it 
would make sense to remove CONFIG_PCIE_IPROC_MSI and combine code in 
pcie-iproc.c.  But I think leaving the bcma and platform code in their 
own files makes it easier for us to work with the code rather than 
placing unused code in ifdefs in the same file.
>
> Bjorn
Regards,
Scott

Re: [PATCH 6/8] PCI: host: brcmstb: add MSI capability

[Bjorn Helgaas]

On Wed, Oct 25, 2017 at 11:40:47AM -0700, Scott Branden wrote:
> Hi Bjorn,
> 
> 
> On 17-10-25 10:23 AM, Bjorn Helgaas wrote:
> >[+cc Ray, Scott, Jon]
> >
> >On Wed, Oct 25, 2017 at 11:28:07AM -0400, Jim Quinlan wrote:
> >>On Tue, Oct 24, 2017 at 2:57 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> >>>Hi Jim,
> >>>
> >>>On 10/24/2017 11:15 AM, Jim Quinlan wrote:
> >>>>This commit adds MSI to the Broadcom STB PCIe host controller. It does
> >>>>not add MSIX since that functionality is not in the HW.  The MSI
> >>>>controller is physically located within the PCIe block, however, there
> >>>>is no reason why the MSI controller could not be moved elsewhere in
> >>>>the future.
> >>>>
> >>>>Since the internal Brcmstb MSI controller is intertwined with the PCIe
> >>>>controller, it is not its own platform device but rather part of the
> >>>>PCIe platform device.
> >>>>
> >>>>Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> >>>>---
> >>>>  drivers/pci/host/Kconfig           |  12 ++
> >>>>  drivers/pci/host/Makefile          |   1 +
> >>>>  drivers/pci/host/pci-brcmstb-msi.c | 318 +++++++++++++++++++++++++++++++++++++
> >>>>  drivers/pci/host/pci-brcmstb.c     |  72 +++++++--
> >>>>  drivers/pci/host/pci-brcmstb.h     |  26 +++
> >>>>  5 files changed, 419 insertions(+), 10 deletions(-)
> >>>>  create mode 100644 drivers/pci/host/pci-brcmstb-msi.c
> >>>>
> >>>>diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> >>>>index b9b4f11..54aa5d2 100644
> >>>>--- a/drivers/pci/host/Kconfig
> >>>>+++ b/drivers/pci/host/Kconfig
> >>>>@@ -228,4 +228,16 @@ config PCI_BRCMSTB
> >>>>       default ARCH_BRCMSTB || BMIPS_GENERIC
> >>>>       help
> >>>>         Adds support for Broadcom Settop Box PCIe host controller.
> >>>>+       To compile this driver as a module, choose m here.
> >>>>+
> >>>>+config PCI_BRCMSTB_MSI
> >>>>+     bool "Broadcom Brcmstb PCIe MSI support"
> >>>>+     depends on ARCH_BRCMSTB || BMIPS_GENERIC
> >>>This could probably be depends on PCI_BRCMSTB, which would imply these
> >>>two conditions. PCI_BRCMSTB_MSI on its own is probably not very useful
> >>>without the parent RC driver.
> >>>
> >>>>+     depends on OF
> >>>>+     depends on PCI_MSI
> >>>>+     default PCI_BRCMSTB
> >>>>+     help
> >>>>+       Say Y here if you want to enable MSI support for Broadcom's iProc
> >>>>+       PCIe controller
> >>>>+
> >>>>  endmenu
> >>>>diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> >>>>index c283321..1026d6f 100644
> >>>>--- a/drivers/pci/host/Makefile
> >>>>+++ b/drivers/pci/host/Makefile
> >>>>@@ -23,6 +23,7 @@ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> >>>>  obj-$(CONFIG_VMD) += vmd.o
> >>>>  obj-$(CONFIG_PCI_BRCMSTB) += brcmstb-pci.o
> >>>>  brcmstb-pci-objs := pci-brcmstb.o pci-brcmstb-dma.o
> >>>>+obj-$(CONFIG_PCI_BRCMSTB_MSI) += pci-brcmstb-msi.o
> >>>Should we combine this file with the brcmstb-pci.o? There is probably no
> >>>functional difference, except that pci-brcmstb-msi.ko needs to be loaded
> >>>first, right?
> >>>--
> >>>Florian
> >>If you look at the pci/host/Kconfig you will see that other drivers
> >>also have a separate MSI config (eg iproc, altera, xgene) so there is
> >>precedent.  The reason that pci-brcmstb-msi.c is its own file is
> >>because it depends on an irq function that is not exported.  That is
> >>why CONFIG_PCI_BRCMSTB_MSI is bool, and CONFIG_PCI_BRCMSTB is
> >>tristate.  -- Jim
> >There is precedent, but that doesn't mean I like it :)
> >I would strongly prefer one file per driver when possible.
> >
> >Take iproc for example.  iproc-msi.c is enabled by a Kconfig bool.  It
> >contains a bunch of code with the only external entry points being
> >iproc_msi_init() and iproc_msi_exit().  These are only called via
> >iproc_pcie_bcma_probe() or iproc_pcie_pltfm_probe(), both of which are
> >tristate.  So iproc-msi.c is only compiled if CONFIG_IPROC_BCMA or
> >CONFIG_IPROC_PLATFORM are enabled, but all that text is loaded even if
> >neither module is loaded, which seems suboptimal.
> >
> >I don't care if you have several config options to enable the BCMA
> >probe and the platform probe (although these could probably be
> >replaced in the code by a simple "#ifdef CONFIG_BCMA" and "#ifdef
> >CONFIG_OF"), and making CONFIG_PCIE_IPROC tristate so it can be a
> >module makes sense.  But I think it would be better to put all the
> >code in one file instead of five, and probably remove
> >CONFIG_PCIE_IPROC_MSI.  Maybe this requires exporting some IRQ
> >function that currently isn't exported.  But that seems like a simpler
> >solution than what we currently have.
> Placing pcie-iproc-bcma.c in its own file is useful in being able to
> read the code that is actually used.  BCMA is really unnecessary if
> a few platforms stopped using BCMA and declared everything via
> devicetree or ACPI.  Same with pcie-iproc-platform.c.  Both keep the
> mess out of pcie-iproc.c.

Maybe.  Both pcie-iproc-bcma.c and pcie-iproc-platform.c are small
(280 lines combined) relative to pcie-iproc.c + pcie-iproc-msi.c (2150
lines combined), and keeping them separate requires pcie-iproc.h,
which could otherwise be folded into pcie-iproc.c.  So I'm still a
little skeptical.  You think of combining them as a mess, but I think
of it as a big convenience because I could see all the iproc-related
code in one place :)

> It looks like pcie-iproc-msi.c followed existing pci drivers in
> place.  So if msi was cleaned up through the entire pci drivers then
> yes it would make sense to remove CONFIG_PCIE_IPROC_MSI and combine
> code in pcie-iproc.c.  But I think leaving the bcma and platform
> code in their own files makes it easier for us to work with the code
> rather than placing unused code in ifdefs in the same file.

But I do object *more* to putting MSI in a separate file, especially
given the fact that all PCIe devices that generate interrupts must
support MSI.  So any reasonable PCIe root complex must also support
MSI, and I don't really see the benefit of configuring and building it
separately.

Anyway, iproc is already in the tree, and we *could* maybe change
something eventually.

The question we need to decide now is about how brcmstb should be
structured.  Somebody mentioned an IRQ function that would have to be
exported for the brcmstb main driver & MSI pieces to be combined.  I
don't know what specifically that is, but I thought maybe iproc had
the same issue.

Bjorn

Re: [PATCH 6/8] PCI: host: brcmstb: add MSI capability

[Jim Quinlan]

On Wed, Oct 25, 2017 at 4:16 PM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> On Wed, Oct 25, 2017 at 11:40:47AM -0700, Scott Branden wrote:
>> Hi Bjorn,
>>
>>
>> On 17-10-25 10:23 AM, Bjorn Helgaas wrote:
>> >[+cc Ray, Scott, Jon]
>> >
>> >On Wed, Oct 25, 2017 at 11:28:07AM -0400, Jim Quinlan wrote:
>> >>On Tue, Oct 24, 2017 at 2:57 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
>> >>>Hi Jim,
>> >>>
>> >>>On 10/24/2017 11:15 AM, Jim Quinlan wrote:
>> >>>>This commit adds MSI to the Broadcom STB PCIe host controller. It does
>> >>>>not add MSIX since that functionality is not in the HW.  The MSI
>> >>>>controller is physically located within the PCIe block, however, there
>> >>>>is no reason why the MSI controller could not be moved elsewhere in
>> >>>>the future.
>> >>>>
>> >>>>Since the internal Brcmstb MSI controller is intertwined with the PCIe
>> >>>>controller, it is not its own platform device but rather part of the
>> >>>>PCIe platform device.
>> >>>>
>> >>>>Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
>> >>>>---
>> >>>>  drivers/pci/host/Kconfig           |  12 ++
>> >>>>  drivers/pci/host/Makefile          |   1 +
>> >>>>  drivers/pci/host/pci-brcmstb-msi.c | 318 +++++++++++++++++++++++++++++++++++++
>> >>>>  drivers/pci/host/pci-brcmstb.c     |  72 +++++++--
>> >>>>  drivers/pci/host/pci-brcmstb.h     |  26 +++
>> >>>>  5 files changed, 419 insertions(+), 10 deletions(-)
>> >>>>  create mode 100644 drivers/pci/host/pci-brcmstb-msi.c
>> >>>>
>> >>>>diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> >>>>index b9b4f11..54aa5d2 100644
>> >>>>--- a/drivers/pci/host/Kconfig
>> >>>>+++ b/drivers/pci/host/Kconfig
>> >>>>@@ -228,4 +228,16 @@ config PCI_BRCMSTB
>> >>>>       default ARCH_BRCMSTB || BMIPS_GENERIC
>> >>>>       help
>> >>>>         Adds support for Broadcom Settop Box PCIe host controller.
>> >>>>+       To compile this driver as a module, choose m here.
>> >>>>+
>> >>>>+config PCI_BRCMSTB_MSI
>> >>>>+     bool "Broadcom Brcmstb PCIe MSI support"
>> >>>>+     depends on ARCH_BRCMSTB || BMIPS_GENERIC
>> >>>This could probably be depends on PCI_BRCMSTB, which would imply these
>> >>>two conditions. PCI_BRCMSTB_MSI on its own is probably not very useful
>> >>>without the parent RC driver.
>> >>>
>> >>>>+     depends on OF
>> >>>>+     depends on PCI_MSI
>> >>>>+     default PCI_BRCMSTB
>> >>>>+     help
>> >>>>+       Say Y here if you want to enable MSI support for Broadcom's iProc
>> >>>>+       PCIe controller
>> >>>>+
>> >>>>  endmenu
>> >>>>diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
>> >>>>index c283321..1026d6f 100644
>> >>>>--- a/drivers/pci/host/Makefile
>> >>>>+++ b/drivers/pci/host/Makefile
>> >>>>@@ -23,6 +23,7 @@ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>> >>>>  obj-$(CONFIG_VMD) += vmd.o
>> >>>>  obj-$(CONFIG_PCI_BRCMSTB) += brcmstb-pci.o
>> >>>>  brcmstb-pci-objs := pci-brcmstb.o pci-brcmstb-dma.o
>> >>>>+obj-$(CONFIG_PCI_BRCMSTB_MSI) += pci-brcmstb-msi.o
>> >>>Should we combine this file with the brcmstb-pci.o? There is probably no
>> >>>functional difference, except that pci-brcmstb-msi.ko needs to be loaded
>> >>>first, right?
>> >>>--
>> >>>Florian
>> >>If you look at the pci/host/Kconfig you will see that other drivers
>> >>also have a separate MSI config (eg iproc, altera, xgene) so there is
>> >>precedent.  The reason that pci-brcmstb-msi.c is its own file is
>> >>because it depends on an irq function that is not exported.  That is
>> >>why CONFIG_PCI_BRCMSTB_MSI is bool, and CONFIG_PCI_BRCMSTB is
>> >>tristate.  -- Jim
>> >There is precedent, but that doesn't mean I like it :)
>> >I would strongly prefer one file per driver when possible.
>> >
>> >Take iproc for example.  iproc-msi.c is enabled by a Kconfig bool.  It
>> >contains a bunch of code with the only external entry points being
>> >iproc_msi_init() and iproc_msi_exit().  These are only called via
>> >iproc_pcie_bcma_probe() or iproc_pcie_pltfm_probe(), both of which are
>> >tristate.  So iproc-msi.c is only compiled if CONFIG_IPROC_BCMA or
>> >CONFIG_IPROC_PLATFORM are enabled, but all that text is loaded even if
>> >neither module is loaded, which seems suboptimal.
>> >
>> >I don't care if you have several config options to enable the BCMA
>> >probe and the platform probe (although these could probably be
>> >replaced in the code by a simple "#ifdef CONFIG_BCMA" and "#ifdef
>> >CONFIG_OF"), and making CONFIG_PCIE_IPROC tristate so it can be a
>> >module makes sense.  But I think it would be better to put all the
>> >code in one file instead of five, and probably remove
>> >CONFIG_PCIE_IPROC_MSI.  Maybe this requires exporting some IRQ
>> >function that currently isn't exported.  But that seems like a simpler
>> >solution than what we currently have.
>> Placing pcie-iproc-bcma.c in its own file is useful in being able to
>> read the code that is actually used.  BCMA is really unnecessary if
>> a few platforms stopped using BCMA and declared everything via
>> devicetree or ACPI.  Same with pcie-iproc-platform.c.  Both keep the
>> mess out of pcie-iproc.c.
>
> Maybe.  Both pcie-iproc-bcma.c and pcie-iproc-platform.c are small
> (280 lines combined) relative to pcie-iproc.c + pcie-iproc-msi.c (2150
> lines combined), and keeping them separate requires pcie-iproc.h,
> which could otherwise be folded into pcie-iproc.c.  So I'm still a
> little skeptical.  You think of combining them as a mess, but I think
> of it as a big convenience because I could see all the iproc-related
> code in one place :)
>
>> It looks like pcie-iproc-msi.c followed existing pci drivers in
>> place.  So if msi was cleaned up through the entire pci drivers then
>> yes it would make sense to remove CONFIG_PCIE_IPROC_MSI and combine
>> code in pcie-iproc.c.  But I think leaving the bcma and platform
>> code in their own files makes it easier for us to work with the code
>> rather than placing unused code in ifdefs in the same file.
>
> But I do object *more* to putting MSI in a separate file, especially
> given the fact that all PCIe devices that generate interrupts must
> support MSI.  So any reasonable PCIe root complex must also support
> MSI, and I don't really see the benefit of configuring and building it
> separately.
>
> Anyway, iproc is already in the tree, and we *could* maybe change
> something eventually.
>
> The question we need to decide now is about how brcmstb should be
> structured.  Somebody mentioned an IRQ function that would have to be
> exported for the brcmstb main driver & MSI pieces to be combined.  I
> don't know what specifically that is, but I thought maybe iproc had
> the same issue.
I was one the one who said an export was needed but I just recompiled
the MSI code as a module and had no problem.  I was probably using an
older tree when I concluded this.  So I'm fine with combining the MSI
code in the same file as the driver.

>
> Bjorn

Re: [PATCH 6/8] PCI: host: brcmstb: add MSI capability

[Bjorn Helgaas]

On Tue, Oct 24, 2017 at 02:15:47PM -0400, Jim Quinlan wrote:
> This commit adds MSI to the Broadcom STB PCIe host controller. It does
> not add MSIX since that functionality is not in the HW.  The MSI
> controller is physically located within the PCIe block, however, there
> is no reason why the MSI controller could not be moved elsewhere in
> the future.
> 
> Since the internal Brcmstb MSI controller is intertwined with the PCIe
> controller, it is not its own platform device but rather part of the
> PCIe platform device.
> 
> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> ---
>  drivers/pci/host/Kconfig           |  12 ++
>  drivers/pci/host/Makefile          |   1 +
>  drivers/pci/host/pci-brcmstb-msi.c | 318 +++++++++++++++++++++++++++++++++++++
>  drivers/pci/host/pci-brcmstb.c     |  72 +++++++--
>  drivers/pci/host/pci-brcmstb.h     |  26 +++
>  5 files changed, 419 insertions(+), 10 deletions(-)
>  create mode 100644 drivers/pci/host/pci-brcmstb-msi.c
> 
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index b9b4f11..54aa5d2 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -228,4 +228,16 @@ config PCI_BRCMSTB
>  	default ARCH_BRCMSTB || BMIPS_GENERIC
>  	help
>  	  Adds support for Broadcom Settop Box PCIe host controller.
> +	  To compile this driver as a module, choose m here.
> +
> +config PCI_BRCMSTB_MSI
> +	bool "Broadcom Brcmstb PCIe MSI support"
> +	depends on ARCH_BRCMSTB || BMIPS_GENERIC
> +	depends on OF
> +	depends on PCI_MSI
> +	default PCI_BRCMSTB
> +	help
> +	  Say Y here if you want to enable MSI support for Broadcom's iProc
> +	  PCIe controller

Is there any reason *not* to enable MSI?  Most drivers just include
MSI support in the base driver, in the same file and under the same
config symbol.

> +
>  endmenu
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index c283321..1026d6f 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -23,6 +23,7 @@ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>  obj-$(CONFIG_VMD) += vmd.o
>  obj-$(CONFIG_PCI_BRCMSTB) += brcmstb-pci.o
>  brcmstb-pci-objs := pci-brcmstb.o pci-brcmstb-dma.o
> +obj-$(CONFIG_PCI_BRCMSTB_MSI) += pci-brcmstb-msi.o
>  
>  # The following drivers are for devices that use the generic ACPI
>  # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/host/pci-brcmstb-msi.c b/drivers/pci/host/pci-brcmstb-msi.c
> new file mode 100644
> index 0000000..c805e2f
> --- /dev/null
> +++ b/drivers/pci/host/pci-brcmstb-msi.c
> @@ -0,0 +1,318 @@
> +/*
> + * Copyright (C) 2015-2017 Broadcom
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */

Remove last blank line of comment and add a blank line between comment
and #includes.

> +#include <linux/bitops.h>
> +#include <linux/compiler.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/irqchip/chained_irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/msi.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_platform.h>
> +#include <linux/pci.h>
> +#include <linux/types.h>
> +
> +#include "pci-brcmstb.h"
> +
> +#define PCIE_MISC_MSI_DATA_CONFIG			0x404c
> +#define PCIE_MSI_INTR2_BASE				0x4500
> +#define PCIE_MISC_MSI_BAR_CONFIG_LO			0x4044
> +#define PCIE_MISC_MSI_BAR_CONFIG_HI			0x4048
> +
> +/* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */
> +#define STATUS				0x0
> +#define SET				0x4
> +#define CLR				0x8
> +#define MASK_STATUS			0xc
> +#define MASK_SET			0x10
> +#define MASK_CLR			0x14
> +
> +struct brcm_msi {
> +	struct irq_domain *msi_domain;
> +	struct irq_domain *inner_domain;
> +	struct mutex lock; /* guards the alloc/free operations */
> +	u64 target_addr;
> +	int irq;
> +	/* intr_base is the base pointer for interrupt status/set/clr regs */
> +	void __iomem *intr_base;
> +	/* intr_legacy_mask indicates how many bits are MSI interrupts */
> +	u32 intr_legacy_mask;
> +	/* intr_legacy_offset indicates bit position of MSI_01. It is
> +	 * to map the register bit position to a hwirq that starts at 0.
> +	 */
> +	u32 intr_legacy_offset;
> +	/* used indicates which MSI interrupts have been alloc'd */
> +	unsigned long used;
> +
> +	void __iomem *base;
> +	struct device *dev;
> +	struct device_node *dn;
> +	unsigned int rev;
> +};
> +
> +static struct irq_chip brcm_msi_irq_chip = {
> +	.name = "Brcm_MSI",
> +	.irq_mask = pci_msi_mask_irq,
> +	.irq_unmask = pci_msi_unmask_irq,
> +};
> +
> +static struct msi_domain_info brcm_msi_domain_info = {
> +	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
> +		   MSI_FLAG_PCI_MSIX),
> +	.chip	= &brcm_msi_irq_chip,
> +};
> +
> +static void brcm_pcie_msi_isr(struct irq_desc *desc)
> +{
> +	struct irq_chip *chip = irq_desc_get_chip(desc);
> +	struct brcm_msi *msi;
> +	unsigned long status, virq;
> +	u32 mask, bit, hwirq;
> +
> +	chained_irq_enter(chip, desc);
> +	msi = irq_desc_get_handler_data(desc);
> +	mask = msi->intr_legacy_mask;
> +
> +	while ((status = bcm_readl(msi->intr_base + STATUS) & mask)) {
> +		for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) {
> +			/* clear the interrupt */
> +			bcm_writel(1 << bit, msi->intr_base + CLR);
> +
> +			/* Account for legacy interrupt offset */
> +			hwirq = bit - msi->intr_legacy_offset;
> +
> +			virq = irq_find_mapping(msi->inner_domain, hwirq);
> +			if (virq) {
> +				if (msi->used & (1 << hwirq))
> +					generic_handle_irq(virq);
> +				else
> +					dev_info(msi->dev, "unhandled MSI %d\n",
> +						 hwirq);
> +			} else {
> +				/* Unknown MSI, just clear it */
> +				dev_dbg(msi->dev, "unexpected MSI\n");

Use a local "struct device *dev" to avoid repeating the "msi->dev"
here and elsewhere.

> +			}
> +		}
> +	}
> +	chained_irq_exit(chip, desc);
> +}
> +
> +static void brcm_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
> +{
> +	struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
> +	u32 temp;
> +
> +	msg->address_lo = lower_32_bits(msi->target_addr);
> +	msg->address_hi = upper_32_bits(msi->target_addr);
> +	temp = bcm_readl(msi->base + PCIE_MISC_MSI_DATA_CONFIG);
> +	msg->data = ((temp >> 16) & (temp & 0xffff)) | data->hwirq;
> +}
> +
> +static int brcm_msi_set_affinity(struct irq_data *irq_data,
> +				 const struct cpumask *mask, bool force)
> +{
> +	return -EINVAL;
> +}
> +
> +static struct irq_chip brcm_msi_bottom_irq_chip = {
> +	.name			= "Brcm MSI",

Why the different name from brcm_msi_irq_chip above ("Brcm_MSI" vs
"Brcm MSI")?  If the "_" signifies something, it should be made more
explicit.

> +	.irq_compose_msi_msg	= brcm_compose_msi_msg,
> +	.irq_set_affinity	= brcm_msi_set_affinity,
> +};
> +
> +static int brcm_msi_alloc(struct brcm_msi *msi)
> +{
> +	int bit, hwirq;
> +
> +	mutex_lock(&msi->lock);
> +	bit = ~msi->used ? ffz(msi->used) : -1;
> +
> +	if (bit >= 0 && bit < BRCM_INT_PCI_MSI_NR) {
> +		msi->used |= (1 << bit);
> +		hwirq = bit - msi->intr_legacy_offset;
> +	} else {
> +		hwirq = -ENOSPC;
> +	}
> +
> +	mutex_unlock(&msi->lock);
> +	return hwirq;
> +}
> +
> +static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
> +{
> +	mutex_lock(&msi->lock);
> +	msi->used &= ~(1 << (hwirq + msi->intr_legacy_offset));
> +	mutex_unlock(&msi->lock);
> +}
> +
> +static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> +				 unsigned int nr_irqs, void *args)
> +{
> +	struct brcm_msi *msi = domain->host_data;
> +	int hwirq;
> +
> +	hwirq = brcm_msi_alloc(msi);
> +
> +	if (hwirq < 0)
> +		return hwirq;
> +
> +	irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
> +			    &brcm_msi_bottom_irq_chip, domain->host_data,
> +			    handle_simple_irq, NULL, NULL);
> +	return 0;
> +}
> +
> +static void brcm_irq_domain_free(struct irq_domain *domain,
> +				 unsigned int virq, unsigned int nr_irqs)
> +{
> +	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
> +	struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
> +
> +	brcm_msi_free(msi, d->hwirq);
> +}
> +
> +void brcm_msi_set_regs(struct brcm_msi *msi)
> +{
> +	u32 data_val, msi_lo, msi_hi;
> +
> +	if (msi->rev >= BRCM_PCIE_HW_REV_33) {
> +		/* ffe0 -- least sig 5 bits are 0 indicating 32 msgs
> +		 * 6540 -- this is our arbitrary unique data value
> +		 */

Multi-line comment style.

> +		data_val = 0xffe06540;
> +	} else {
> +		/* fff8 -- least sig 3 bits are 0 indicating 8 msgs
> +		 * 6540 -- this is our arbitrary unique data value
> +		 */
> +		data_val = 0xfff86540;
> +	}
> +
> +	/* Make sure we are not masking MSIs.  Note that MSIs can be masked,
> +	 * but that occurs on the PCIe EP device
> +	 */
> +	bcm_writel(0xffffffff & msi->intr_legacy_mask,
> +		   msi->intr_base + MASK_CLR);
> +
> +	msi_lo = lower_32_bits(msi->target_addr);
> +	msi_hi = upper_32_bits(msi->target_addr);
> +	/* The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
> +	 * enable, which we set to 1.
> +	 */
> +	bcm_writel(msi_lo | 1, msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
> +	bcm_writel(msi_hi, msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
> +	bcm_writel(data_val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
> +}
> +EXPORT_SYMBOL(brcm_msi_set_regs);
> +
> +static const struct irq_domain_ops msi_domain_ops = {
> +	.alloc	= brcm_irq_domain_alloc,
> +	.free	= brcm_irq_domain_free,
> +};
> +
> +static int brcm_allocate_domains(struct brcm_msi *msi)
> +{
> +	struct fwnode_handle *fwnode = of_node_to_fwnode(msi->dn);
> +
> +	msi->inner_domain = irq_domain_add_linear(NULL, BRCM_INT_PCI_MSI_NR,
> +						  &msi_domain_ops, msi);
> +	if (!msi->inner_domain) {
> +		dev_err(msi->dev, "failed to create IRQ domain\n");
> +		return -ENOMEM;
> +	}
> +
> +	msi->msi_domain = pci_msi_create_irq_domain(fwnode,
> +						    &brcm_msi_domain_info,
> +						    msi->inner_domain);
> +	if (!msi->msi_domain) {
> +		dev_err(msi->dev, "failed to create MSI domain\n");
> +		irq_domain_remove(msi->inner_domain);
> +		return -ENOMEM;
> +	}
> +
> +	return 0;
> +}
> +
> +static void brcm_free_domains(struct brcm_msi *msi)
> +{
> +	irq_domain_remove(msi->msi_domain);
> +	irq_domain_remove(msi->inner_domain);
> +}
> +
> +void brcm_msi_remove(struct brcm_msi *msi)
> +{
> +	if (!msi)
> +		return;
> +	irq_set_chained_handler(msi->irq, NULL);
> +	irq_set_handler_data(msi->irq, NULL);
> +	brcm_free_domains(msi);
> +}
> +EXPORT_SYMBOL(brcm_msi_remove);
> +
> +int brcm_msi_probe(struct platform_device *pdev, struct brcm_info *info)
> +{
> +	struct brcm_msi *msi;
> +	int irq, ret;
> +
> +	irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
> +	if (irq <= 0) {
> +		dev_err(&pdev->dev, "cannot map msi intr\n");
> +		return -ENODEV;
> +	}
> +
> +	msi = devm_kzalloc(&pdev->dev, sizeof(struct brcm_msi), GFP_KERNEL);
> +	if (!msi)
> +		return -ENOMEM;
> +
> +	msi->dev = &pdev->dev;
> +	msi->base = info->base;
> +	msi->rev =  info->rev;
> +	msi->dn = pdev->dev.of_node;
> +	msi->target_addr = info->msi_target_addr;
> +	msi->irq = irq;
> +
> +	ret = brcm_allocate_domains(msi);
> +	if (ret)
> +		return ret;
> +
> +	irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
> +
> +	if (msi->rev >= BRCM_PCIE_HW_REV_33) {
> +		msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
> +		/* This version of PCIe hw has only 32 intr bits
> +		 * starting at bit position 0.
> +		 */
> +		msi->intr_legacy_mask = 0xffffffff;
> +		msi->intr_legacy_offset = 0x0;
> +		msi->used = 0x0;
> +
> +	} else {
> +		msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
> +		/* This version of PCIe hw has only 8 intr bits starting
> +		 * at bit position 24.
> +		 */
> +		msi->intr_legacy_mask = 0xff000000;
> +		msi->intr_legacy_offset = 24;
> +		msi->used = 0x00ffffff;
> +	}
> +
> +	brcm_msi_set_regs(msi);
> +	info->msi = msi;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(brcm_msi_probe);
> diff --git a/drivers/pci/host/pci-brcmstb.c b/drivers/pci/host/pci-brcmstb.c
> index f5d80e6..99900d9 100644
> --- a/drivers/pci/host/pci-brcmstb.c
> +++ b/drivers/pci/host/pci-brcmstb.c
> @@ -22,6 +22,7 @@
>  #include <linux/list.h>
>  #include <linux/log2.h>
>  #include <linux/module.h>
> +#include <linux/msi.h>
>  #include <linux/of_address.h>
>  #include <linux/of_irq.h>
>  #include <linux/of_pci.h>
> @@ -327,10 +328,13 @@ struct brcm_pcie {
>  	int			num_out_wins;
>  	bool			ssc;
>  	int			gen;
> +	u64			msi_target_addr;
>  	struct brcm_window	out_wins[BRCM_NUM_PCI_OUT_WINS];
>  	struct list_head	resources;
>  	struct device		*dev;
>  	struct list_head	pwr_supplies;
> +	struct brcm_msi		*msi;
> +	bool			msi_internal;
>  	unsigned int		rev;
>  	unsigned int		num;
>  	bool			bridge_setup_done;
> @@ -763,6 +767,7 @@ static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
>  	void __iomem *base = pcie->base;
>  	unsigned int scb_size_val;
>  	u64 rc_bar2_size = 0, rc_bar2_offset = 0, total_mem_size = 0;
> +	u64 msi_target_addr;
>  	u32 tmp, burst;
>  	int i;
>  
> @@ -806,14 +811,17 @@ static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
>  	/* The PCI host controller by design must set the inbound
>  	 * viewport to be a contiguous arrangement of all of the
>  	 * system's memory.  In addition, its size mut be a power of
> -	 * two.  To further complicate matters, the viewport must
> -	 * start on a pci-address that is aligned on a multiple of its
> -	 * size.  If a portion of the viewport does not represent
> -	 * system memory -- e.g. 3GB of memory requires a 4GB viewport
> -	 * -- we can map the outbound memory in or after 3GB and even
> -	 * though the viewport will overlap the outbound memory the
> -	 * controller will know to send outbound memory downstream and
> -	 * everything else upstream.
> +	 * two.  Further, the MSI target address must NOT be placed
> +	 * inside this region, as the decoding logic will consider its
> +	 * address to be inbound memory traffic.  To further
> +	 * complicate matters, the viewport must start on a
> +	 * pci-address that is aligned on a multiple of its size.
> +	 * If a portion of the viewport does not represent system
> +	 * memory -- e.g. 3GB of memory requires a 4GB viewport --
> +	 * we can map the outbound memory in or after 3GB and even
> +	 * though the viewport will overlap the outbound memory
> +	 * the controller will know to send outbound memory downstream
> +	 * and everything else upstream.
>  	 */
>  	rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
>  
> @@ -828,6 +836,14 @@ static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
>  		if (total_mem_size <= 0xc0000000ULL &&
>  		    rc_bar2_size <= 0x100000000ULL) {
>  			rc_bar2_offset = 0;
> +			/* If the viewport is less then 4GB we can fit
> +			 * the MSI target address under 4GB. Otherwise
> +			 * put it right below 64GB.
> +			 */
> +			msi_target_addr =
> +				(rc_bar2_size == 0x100000000ULL)
> +				? BRCM_MSI_TARGET_ADDR_GT_4GB
> +				: BRCM_MSI_TARGET_ADDR_LT_4GB;
>  		} else {
>  			/* The system memory is 4GB or larger so we
>  			 * cannot start the inbound region at location
> @@ -836,15 +852,24 @@ static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
>  			 * start it at the 1x multiple of its size
>  			 */
>  			rc_bar2_offset = rc_bar2_size;
> -		}
>  
> +			/* Since we are starting the viewport at 4GB or
> +			 * higher, put the MSI target address below 4GB
> +			 */
> +			msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
> +		}
>  	} else {
>  		/* Set simple configuration based on memory sizes
>  		 * only.  We always start the viewport at address 0,
>  		 * and set the MSI target address accordingly.
>  		 */
>  		rc_bar2_offset = 0;
> +
> +		msi_target_addr = (rc_bar2_size >= 0x100000000ULL)
> +			? BRCM_MSI_TARGET_ADDR_GT_4GB
> +			: BRCM_MSI_TARGET_ADDR_LT_4GB;
>  	}
> +	pcie->msi_target_addr = msi_target_addr;
>  
>  	tmp = lower_32_bits(rc_bar2_offset);
>  	tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> @@ -1053,6 +1078,9 @@ static int brcm_pcie_resume(struct device *dev)
>  	if (ret)
>  		return ret;
>  
> +	if (pcie->msi && pcie->msi_internal)
> +		brcm_msi_set_regs(pcie->msi);
> +
>  	pcie->suspended = false;
>  
>  	return 0;
> @@ -1116,6 +1144,7 @@ static void __attribute__((__section__("pci_fixup_early")))
>  
>  static void _brcm_pcie_remove(struct brcm_pcie *pcie)
>  {
> +	brcm_msi_remove(pcie->msi);
>  	turn_off(pcie);
>  	clk_disable_unprepare(pcie->clk);
>  	clk_put(pcie->clk);
> @@ -1125,7 +1154,7 @@ static void _brcm_pcie_remove(struct brcm_pcie *pcie)
>  
>  static int brcm_pcie_probe(struct platform_device *pdev)
>  {
> -	struct device_node *dn = pdev->dev.of_node;
> +	struct device_node *dn = pdev->dev.of_node, *msi_dn;
>  	struct property *pp;
>  	const struct of_device_id *of_id;
>  	const struct pcie_cfg_data *data;
> @@ -1244,6 +1273,29 @@ static int brcm_pcie_probe(struct platform_device *pdev)
>  	if (ret)
>  		goto fail;
>  
> +	msi_dn = of_parse_phandle(pcie->dn, "msi-parent", 0);
> +	/* Use the internal MSI if no msi-parent property */
> +	if (!msi_dn)
> +		msi_dn = pcie->dn;
> +
> +	if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_enabled()
> +	    && msi_dn == pcie->dn) {
> +		struct brcm_info info;
> +
> +		info.rev = pcie->rev;
> +		info.msi_target_addr = pcie->msi_target_addr;
> +		info.base = pcie->base;
> +
> +		ret = brcm_msi_probe(pdev, &info);
> +		if (ret)
> +			dev_err(pcie->dev,
> +				"probe of internal MSI failed: %d)", ret);
> +		else
> +			pcie->msi_internal = true;
> +
> +		pcie->msi = info.msi;
> +	}
> +
>  	list_splice_init(&pcie->resources, &bridge->windows);
>  	bridge->dev.parent = &pdev->dev;
>  	bridge->busnr = 0;
> diff --git a/drivers/pci/host/pci-brcmstb.h b/drivers/pci/host/pci-brcmstb.h
> index c3b148a..f969c2a 100644
> --- a/drivers/pci/host/pci-brcmstb.h
> +++ b/drivers/pci/host/pci-brcmstb.h
> @@ -27,6 +27,32 @@
>  extern struct of_pci_range *dma_ranges;
>  extern int num_dma_ranges;
>  
> +struct brcm_msi;
> +struct brcm_info;
> +struct platform_device;
> +
> +#ifdef CONFIG_PCI_BRCMSTB_MSI
> +int brcm_msi_probe(struct platform_device *pdev, struct brcm_info *info);
> +void brcm_msi_set_regs(struct brcm_msi *chip);
> +void brcm_msi_remove(struct brcm_msi *chip);
> +#else
> +static inline int brcm_msi_probe(struct platform_device *pdev,
> +				 struct brcm_info *info)
> +{
> +	return -ENODEV;
> +}
> +
> +static inline void brcm_msi_set_regs(struct brcm_msi *chip) {}
> +static inline void brcm_msi_remove(struct brcm_msi *chip) {}
> +#endif /* CONFIG_PCI_BRCMSTB_MSI */
> +
> +struct brcm_info {
> +	int rev;
> +	u64 msi_target_addr;
> +	void __iomem *base;
> +	struct brcm_msi *msi;
> +};
> +
>  #if defined(CONFIG_MIPS)
>  /* Broadcom MIPs HW implicitly does the swapping if necessary */
>  #define bcm_readl(a)		__raw_readl(a)
> -- 
> 1.9.0.138.g2de3478
> 

Re: [PATCH 6/8] PCI: host: brcmstb: add MSI capability

[Jim Quinlan]

On Wed, Oct 25, 2017 at 9:22 AM, Bjorn Helgaas <helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Tue, Oct 24, 2017 at 02:15:47PM -0400, Jim Quinlan wrote:
>> This commit adds MSI to the Broadcom STB PCIe host controller. It does
>> not add MSIX since that functiostbsrvnality is not in the HW.  The MSI
>> controller is physically located within the PCIe block, however, there
>> is no reason why the MSI controller could not be moved elsewhere in
>> the future.
>>
>> Since the internal Brcmstb MSI controller is intertwined with the PCIe
>> controller, it is not its own platform device but rather part of the
>> PCIe platform device.
>>
>> Signed-off-by: Jim Quinlan <jim2101024-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>>  drivers/pci/host/Kconfig           |  12 ++
>>  drivers/pci/host/Makefile          |   1 +
>>  drivers/pci/host/pci-brcmstb-msi.c | 318 +++++++++++++++++++++++++++++++++++++
>>  drivers/pci/host/pci-brcmstb.c     |  72 +++++++--
>>  drivers/pci/host/pci-brcmstb.h     |  26 +++
>>  5 files changed, 419 insertions(+), 10 deletions(-)
>>  create mode 100644 drivers/pci/host/pci-brcmstb-msi.c
>>
>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> index b9b4f11..54aa5d2 100644
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>> @@ -228,4 +228,16 @@ config PCI_BRCMSTB
>>       default ARCH_BRCMSTB || BMIPS_GENERIC
>>       help
>>         Adds support for Broadcom Settop Box PCIe host controller.
>> +       To compile this driver as a module, choose m here.
>> +
>> +config PCI_BRCMSTB_MSI
>> +     bool "Broadcom Brcmstb PCIe MSI support"
>> +     depends on ARCH_BRCMSTB || BMIPS_GENERIC
>> +     depends on OF
>> +     depends on PCI_MSI
>> +     default PCI_BRCMSTB
>> +     help
>> +       Say Y here if you want to enable MSI support for Broadcom's iProc
>> +       PCIe controller
>
> Is there any reason *not* to enable MSI?  Most drivers just include
> MSI support in the base driver, in the same file and under the same
> config symbol.
>
CONFIG_PCI_BRCMSTB_MSI is bool, CONFIG_PCI_BRCMSTB is tri-state.  The
reason for this -- and also for the separate msi file -- is that there
is an irq call  that is not exported (I can dig it up if you'd like).
We have had requests that the PCIe RC driver doesn't run at boot, so
we consider the idea of it being a module valuable.  You can see the
same thing going on with PCIE_IPROC_MSI.

>> +
>>  endmenu
>> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
>> index c283321..1026d6f 100644
>> --- a/drivers/pci/host/Makefile
>> +++ b/drivers/pci/host/Makefile
>> @@ -23,6 +23,7 @@ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>>  obj-$(CONFIG_VMD) += vmd.o
>>  obj-$(CONFIG_PCI_BRCMSTB) += brcmstb-pci.o
>>  brcmstb-pci-objs := pci-brcmstb.o pci-brcmstb-dma.o
>> +obj-$(CONFIG_PCI_BRCMSTB_MSI) += pci-brcmstb-msi.o
>>
>>  # The following drivers are for devices that use the generic ACPI
>>  # pci_root.c driver but don't support standard ECAM config access.
>> diff --git a/drivers/pci/host/pci-brcmstb-msi.c b/drivers/pci/host/pci-brcmstb-msi.c
>> new file mode 100644
>> index 0000000..c805e2f
>> --- /dev/null
>> +++ b/drivers/pci/host/pci-brcmstb-msi.c
>> @@ -0,0 +1,318 @@
>> +/*
>> + * Copyright (C) 2015-2017 Broadcom
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + */
>
> Remove last blank line of comment and add a blank line between comment
> and #includes.
Will fix.

>
>> +#include <linux/bitops.h>
>> +#include <linux/compiler.h>
>> +#include <linux/init.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/irqchip/chained_irq.h>
>> +#include <linux/irqdomain.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/msi.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_pci.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/pci.h>
>> +#include <linux/types.h>
>> +
>> +#include "pci-brcmstb.h"
>> +
>> +#define PCIE_MISC_MSI_DATA_CONFIG                    0x404c
>> +#define PCIE_MSI_INTR2_BASE                          0x4500
>> +#define PCIE_MISC_MSI_BAR_CONFIG_LO                  0x4044
>> +#define PCIE_MISC_MSI_BAR_CONFIG_HI                  0x4048
>> +
>> +/* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */
>> +#define STATUS                               0x0
>> +#define SET                          0x4
>> +#define CLR                          0x8
>> +#define MASK_STATUS                  0xc
>> +#define MASK_SET                     0x10
>> +#define MASK_CLR                     0x14
>> +
>> +struct brcm_msi {
>> +     struct irq_domain *msi_domain;
>> +     struct irq_domain *inner_domain;
>> +     struct mutex lock; /* guards the alloc/free operations */
>> +     u64 target_addr;
>> +     int irq;
>> +     /* intr_base is the base pointer for interrupt status/set/clr regs */
>> +     void __iomem *intr_base;
>> +     /* intr_legacy_mask indicates how many bits are MSI interrupts */
>> +     u32 intr_legacy_mask;
>> +     /* intr_legacy_offset indicates bit position of MSI_01. It is
>> +      * to map the register bit position to a hwirq that starts at 0.
>> +      */
>> +     u32 intr_legacy_offset;
>> +     /* used indicates which MSI interrupts have been alloc'd */
>> +     unsigned long used;
>> +
>> +     void __iomem *base;
>> +     struct device *dev;
>> +     struct device_node *dn;
>> +     unsigned int rev;
>> +};
>> +
>> +static struct irq_chip brcm_msi_irq_chip = {
>> +     .name = "Brcm_MSI",
>> +     .irq_mask = pci_msi_mask_irq,
>> +     .irq_unmask = pci_msi_unmask_irq,
>> +};
>> +
>> +static struct msi_domain_info brcm_msi_domain_info = {
>> +     .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
>> +                MSI_FLAG_PCI_MSIX),
>> +     .chip   = &brcm_msi_irq_chip,
>> +};
>> +
>> +static void brcm_pcie_msi_isr(struct irq_desc *desc)
>> +{
>> +     struct irq_chip *chip = irq_desc_get_chip(desc);
>> +     struct brcm_msi *msi;
>> +     unsigned long status, virq;
>> +     u32 mask, bit, hwirq;
>> +
>> +     chained_irq_enter(chip, desc);
>> +     msi = irq_desc_get_handler_data(desc);
>> +     mask = msi->intr_legacy_mask;
>> +
>> +     while ((status = bcm_readl(msi->intr_base + STATUS) & mask)) {
>> +             for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) {
>> +                     /* clear the interrupt */
>> +                     bcm_writel(1 << bit, msi->intr_base + CLR);
>> +
>> +                     /* Account for legacy interrupt offset */
>> +                     hwirq = bit - msi->intr_legacy_offset;
>> +
>> +                     virq = irq_find_mapping(msi->inner_domain, hwirq);
>> +                     if (virq) {
>> +                             if (msi->used & (1 << hwirq))
>> +                                     generic_handle_irq(virq);
>> +                             else
>> +                                     dev_info(msi->dev, "unhandled MSI %d\n",
>> +                                              hwirq);
>> +                     } else {
>> +                             /* Unknown MSI, just clear it */
>> +                             dev_dbg(msi->dev, "unexpected MSI\n");
>
> Use a local "struct device *dev" to avoid repeating the "msi->dev"
> here and elsewhere.
Will fix.

>
>> +                     }
>> +             }
>> +     }
>> +     chained_irq_exit(chip, desc);
>> +}
>> +
>> +static void brcm_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
>> +{
>> +     struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
>> +     u32 temp;
>> +
>> +     msg->address_lo = lower_32_bits(msi->target_addr);
>> +     msg->address_hi = upper_32_bits(msi->target_addr);
>> +     temp = bcm_readl(msi->base + PCIE_MISC_MSI_DATA_CONFIG);
>> +     msg->data = ((temp >> 16) & (temp & 0xffff)) | data->hwirq;
>> +}
>> +
>> +static int brcm_msi_set_affinity(struct irq_data *irq_data,
>> +                              const struct cpumask *mask, bool force)
>> +{
>> +     return -EINVAL;
>> +}
>> +
>> +static struct irq_chip brcm_msi_bottom_irq_chip = {
>> +     .name                   = "Brcm MSI",PCIE_IPROC_MSI
>
> Why the different name from brcm_msi_irq_chip above ("Brcm_MSI" vs
> "Brcm MSI")?  If the "_" signifies something, it should be made more
> explicit.
>
Will fix.

>> +     .irq_compose_msi_msg    = brcm_compose_msi_msg,
>> +     .irq_set_affinity       = brcm_msi_set_affinity,
>> +};
>> +
>> +static int brcm_msi_alloc(struct brcm_msi *msi)
>> +{
>> +     int bit, hwirq;
>> +
>> +     mutex_lock(&msi->lock);
>> +     bit = ~msi->used ? ffz(msi->used) : -1;
>> +
>> +     if (bit >= 0 && bit < BRCM_INT_PCI_MSI_NR) {
>> +             msi->used |= (1 << bit);
>> +             hwirq = bit - msi->intr_legacy_offset;
>> +     } else {
>> +             hwirq = -ENOSPC;
>> +     }
>> +
>> +     mutex_unlock(&msi->lock);
>> +     return hwirq;
>> +}
>> +
>> +static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
>> +{
>> +     mutex_lock(&msi->lock);
>> +     msi->used &= ~(1 << (hwirq + msi->intr_legacy_offset));
>> +     mutex_unlock(&msi->lock);
>> +}
>> +
>> +static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>> +                              unsigned int nr_irqs, void *args)
>> +{
>> +     struct brcm_msi *msi = domain->host_data;
>> +     int hwirq;
>> +
>> +     hwirq = brcm_msi_alloc(msi);
>> +
>> +     if (hwirq < 0)
>> +             return hwirq;
>> +
>> +     irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
>> +                         &brcm_msi_bottom_irq_chip, domain->host_data,
>> +                         handle_simple_irq, NULL, NULL);
>> +     return 0;
>> +}
>> +
>> +static void brcm_irq_domain_free(struct irq_domain *domain,
>> +                              unsigned int virq, unsigned int nr_irqs)
>> +{
>> +     struct irq_data *d = irq_domain_get_irq_data(domain, virq);
>> +     struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
>> +
>> +     brcm_msi_free(msi, d->hwirq);
>> +}
>> +
>> +void brcm_msi_set_regs(struct brcm_msi *msi)
>> +{
>> +     u32 data_val, msi_lo, msi_hi;
>> +
>> +     if (msi->rev >= BRCM_PCIE_HW_REV_33) {PCIE_IPROC_MSI
>> +             /* ffe0 -- least sig 5 bits are 0 indicating 32 msgs
>> +              * 6540 -- this is our arbitrary unique data value
>> +              */PCIE_IPROC_MSI
>
> Multi-line comment style.
>
Will fix.

>> +             data_val = 0xffe06540;
>> +     } else {
>> +             /* fff8 -- least sig 3 bits are 0 indicating 8 msgs
>> +              * 6540 -- this is our arbitrary unique data value
>> +              */
>> +             data_val = 0xfff86540;
>> +     }
>> +
>> +     /* Make sure we are not masking MSIs.  Note that MSIs can be masked,
>> +      * but that occurs on the PCIe EP device
>> +      */
>> +     bcm_writel(0xffffffff & msi->intr_legacy_mask,PCIE_IPROC_MSI
>> +                msi->intr_base + MASK_CLR);
>> +
>> +     msi_lo = lower_32_bits(msi->target_addr);
>> +     msi_hi = upper_32_bits(msi->target_addr);
>> +     /* The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
>> +      * enable, which we set to 1.
>> +      */
>> +     bcm_writel(msi_lo | 1, msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
>> +     bcm_writel(msi_hi, msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
>> +     bcm_writel(data_val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
>> +}
>> +EXPORT_SYMBOL(brcm_msi_set_regs);
>> +
>> +static const struct irq_domain_ops msi_domain_ops = {
>> +     .alloc  = brcm_irq_domain_alloc,
>> +     .free   = brcm_irq_domain_free,
>> +};
>> +
>> +static int brcm_allocate_domains(struct brcm_msi *msi)
>> +{
>> +     struct fwnode_handle *fwnode = of_node_to_fwnode(msi->dn);
>> +
>> +     msi->inner_domain = irq_domain_add_linear(NULL, BRCM_INT_PCI_MSI_NR,
>> +                                               &msi_domain_ops, msi);
>> +     if (!msi->inner_domain) {
>> +             dev_err(msi->dev, "failed to create IRQ domain\n");
>> +             return -ENOMEM;
>> +     }
>> +
>> +     msi->msi_domain = pci_msi_create_irq_domain(fwnode,
>> +                                                 &brcm_msi_domain_info,
>> +                                                 msi->inner_domain);
>> +     if (!msi->msi_domain) {
>> +             dev_err(msi->dev, "failed to create MSI domain\n");
>> +             irq_domain_remove(msi->inner_domain);
>> +             return -ENOMEM;
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +static void brcm_free_domains(struct brcm_msi *msi)
>> +{
>> +     irq_domain_remove(msi->msi_domain);
>> +     irq_domain_remove(msi->inner_domain);
>> +}
>> +
>> +void brcm_msi_remove(struct brcm_msi *msi)
>> +{
>> +     if (!msi)
>> +             return;
>> +     irq_set_chained_handler(msi->irq, NULL);
>> +     irq_set_handler_data(msi->irq, NULL);
>> +     brcm_free_domains(msi);
>> +}
>> +EXPORT_SYMBOL(brcm_msi_remove);
>> +
>> +int brcm_msi_probe(struct platform_device *pdev, struct brcm_info *info)
>> +{
>> +     struct brcm_msi *msi;
>> +     int irq, ret;
>> +
>> +     irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
>> +     if (irq <= 0) {
>> +             dev_err(&pdev->dev, "cannot map msi intr\n");
>> +             return -ENODEV;
>> +     }
>> +
>> +     msi = devm_kzalloc(&pdev->dev, sizeof(struct brcm_msi), GFP_KERNEL);
>> +     if (!msi)
>> +             return -ENOMEM;
>> +
>> +     msi->dev = &pdev->dev;
>> +     msi->base = info->base;
>> +     msi->rev =  info->rev;
>> +     msi->dn = pdev->dev.of_node;
>> +     msi->target_addr = info->msi_target_addr;
>> +     msi->irq = irq;
>> +
>> +     ret = brcm_allocate_domains(msi);
>> +     if (ret)
>> +             return ret;
>> +
>> +     irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
>> +
>> +     if (msi->rev >= BRCM_PCIE_HW_REV_33) {PCIE_IPROC_MSI
>> +             msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
>> +             /* This version of PCIe hw has only 32 intr bits
>> +              * starting at bit position 0.
>> +              */
>> +             msi->intr_legacy_mask = 0xffffffff;
>> +             msi->intr_legacy_offset = 0x0;
>> +             msi->used = 0x0;
>> +
>> +     } else {
>> +             msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
>> +             /* This version of PCIe hw has only 8 intr bits starting
>> +              * at bit position 24.
>> +              */
>> +             msi->intr_legacy_mask = 0xff000000;
>> +             msi->intr_legacy_offset = 24;
>> +             msi->used = 0x00ffffff;
>> +     }PCIE_IPROC_MSI
>> +
>> +     brcm_msi_set_regs(msi);
>> +     info->msi = msi;
>> +
>> +     return 0;
>> +}
>> +EXPORT_SYMBOL(brcm_msi_probe);
>> diff --git a/drivers/pci/host/pci-brcmstb.c b/drivers/pci/host/pci-brcmstb.c
>> index f5d80e6..99900d9 100644
>> --- a/drivers/pci/host/pci-brcmstb.c
>> +++ b/drivers/pci/host/pci-brcmstb.c
>> @@ -22,6 +22,7 @@
>>  #include <linux/list.h>
>>  #include <linux/log2.h>
>>  #include <linux/module.h>
>> +#include <linux/msi.h>
>>  #include <linux/of_address.h>
>>  #include <linux/of_irq.h>
>>  #include <linux/of_pci.h>
>> @@ -327,10 +328,13 @@ struct brcm_pcie {
>>       int                     num_out_wins;
>>       bool                    ssc;
>>       int                     gen;
>> +     u64                     msi_target_addr;
>>       struct brcm_window      out_wins[BRCM_NUM_PCI_OUT_WINS];
>>       struct list_head        resources;
>>       struct device           *dev;
>>       struct list_head        pwr_supplies;
>> +     struct brcm_msi         *msi;
>> +     bool                    msi_internal;
>>       unsigned int            rev;
>>       unsigned int            num;
>>       bool                    bridge_setup_done;
>> @@ -763,6 +767,7 @@ static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
>>       void __iomem *base = pcie->base;
>>       unsigned int scb_size_val;
>>       u64 rc_bar2_size = 0, rc_bar2_offset = 0, total_mem_size = 0;
>> +     u64 msi_target_addr;
>>       u32 tmp, burst;
>>       int i;
>>
>> @@ -806,14 +811,17 @@ static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
>>       /* The PCI host controller by design must set the inbound
>>        * viewport to be a contiguous arrangement of all of the
>>        * system's memory.  In addition, its size mut be a power of
>> -      * two.  To further complicate matters, the viewport must
>> -      * start on a pci-address that is aligned on a multiple of its
>> -      * size.  If a portion of the viewport does not represent
>> -      * system memory -- e.g. 3GB of memory requires a 4GB viewport
>> -      * -- we can map the outbound memory in or after 3GB and even
>> -      * though the viewport will overlap the outbound memory the
>> -      * controller will know to send outbound memory downstream and
>> -      * everything else upstream.
>> +      * two.  Further, the MSI target address must NOT be placed
>> +      * inside this region, as the decoding logic will consider its
>> +      * address to be inbound memory traffic.  To further
>> +      * complicate matters, the viewport must start on a
>> +      * pci-address that is aligned on a multiple of its size.
>> +      * If a portion of the viewport does not represent system
>> +      * memory -- e.g. 3GB of memory requires a 4GB viewport --
>> +      * we can map the outbound memory in or after 3GB and even
>> +      * though the viewport will overlap the outbound memory
>> +      * the controller will know to send outbound memory downstream
>> +      * and everything else upstream.
>>        */
>>       rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
>>
>> @@ -828,6 +836,14 @@ static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
>>               if (total_mem_size <= 0xc0000000ULL &&
>>                   rc_bar2_size <= 0x100000000ULL) {
>>                       rc_bar2_offset = 0;
>> +                     /* If the viewport is less then 4GB we can fit
>> +                      * the MSI target address under 4GB. Otherwise
>> +                      * put it right below 64GB.
>> +                      */
>> +                     msi_target_addr =
>> +                             (rc_bar2_size == 0x100000000ULL)
>> +                             ? BRCM_MSI_TARGET_ADDR_GT_4GB
>> +                             : BRCM_MSI_TARGET_ADDR_LT_4GB;
>>               } else {
>>                       /* The system memory is 4GB or larger so we
>>                        * cannot start the inbound region at location
>> @@ -836,15 +852,24 @@ static void brcm_pcie_setup_prep(struct brcm_pcie *pcie)
>>                        * start it at the 1x multiple of its size
>>                        */
>>                       rc_bar2_offset = rc_bar2_size;
>> -             }
>>
>> +                     /* Since we are starting the viewport at 4GB or
>> +                      * higher, put the MSI target address below 4GB
>> +                      */
>> +                     msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
>> +             }
>>       } else {
>>               /* Set simple configuration based on memory sizes
>>                * only.  We always start the viewport at address 0,
>>                * and set the MSI target address accordingly.
>>                */
>>               rc_bar2_offset = 0;
>> +
>> +             msi_target_addr = (rc_bar2_size >= 0x100000000ULL)
>> +                     ? BRCM_MSI_TARGET_ADDR_GT_4GB
>> +                     : BRCM_MSI_TARGET_ADDR_LT_4GB;
>>       }
>> +     pcie->msi_target_addr = msi_target_addr;
>>
>>       tmp = lower_32_bits(rc_bar2_offset);
>>       tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
>> @@ -1053,6 +1078,9 @@ static int brcm_pcie_resume(struct device *dev)
>>       if (ret)
>>               return ret;
>>
>> +     if (pcie->msi && pcie->msi_internal)
>> +             brcm_msi_set_regs(pcie->msi);
>> +
>>       pcie->suspended = false;
>>
>>       return 0;
>> @@ -1116,6 +1144,7 @@ static void __attribute__((__section__("pci_fixup_early")))
>>
>>  static void _brcm_pcie_remove(struct brcm_pcie *pcie)
>>  {
>> +     brcm_msi_remove(pcie->msi);
>>       turn_off(pcie);
>>       clk_disable_unprepare(pcie->clk);
>>       clk_put(pcie->clk);PCIE_IPROC_MSI
>> @@ -1125,7 +1154,7 @@ static void _brcm_pcie_remove(struct brcm_pcie *pcie)
>>
>>  static int brcm_pcie_probe(struct platform_device *pdev)
>>  {
>> -     struct device_node *dn = pdev->dev.of_node;
>> +     struct device_node *dn = pdev->dev.of_node, *msi_dn;
>>       struct property *pp;
>>       const struct of_device_id *of_id;
>>       const struct pcie_cfg_data *data;
>> @@ -1244,6 +1273,29 @@ static int brcm_pcie_probe(struct platform_device *pdev)
>>       if (ret)
>>               goto fail;
>>
>> +     msi_dn = of_parse_phandle(pcie->dn, "msi-parent", 0);
>> +     /* Use the internal MSI if no msi-parent property */
>> +     if (!msi_dn)
>> +             msi_dn = pcie->dn;
>> +
>> +     if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_enabled()
>> +         && msi_dn == pcie->dn) {
>> +             struct brcm_info info;
>> +
>> +             info.rev = pcie->rev;
>> +             info.msi_target_addr = pcie->msi_target_addr;
>> +             info.base = pcie->base;
>> +
>> +             ret = brcm_msi_probe(pdev, &info);
>> +             if (ret)
>> +                     dev_err(pcie->dev,
>> +                             "probe of internal MSI failed: %d)", ret);
>> +             else
>> +                     pcie->msi_internal = true;
>> +
>> +             pcie->msi = info.msi;
>> +     }
>> +
>>       list_splice_init(&pcie->resources, &bridge->windows);
>>       bridge->dev.parent = &pdev->dev;
>>       bridge->busnr = 0;
>> diff --git a/drivers/pci/host/pci-brcmstb.h b/drivers/pci/host/pci-brcmstb.h
>> index c3b148a..f969c2a 100644
>> --- a/drivers/pci/host/pci-brcmstb.h
>> +++ b/drivers/pci/host/pci-brcmstb.h
>> @@ -27,6 +27,32 @@
>>  extern struct of_pci_range *dma_ranges;
>>  extern int num_dma_ranges;
>>
>> +struct brcm_msi;
>> +struct brcm_info;
>> +struct platform_device;
>> +
>> +#ifdef CONFIG_PCI_BRCMSTB_MSI
>> +int brcm_msi_probe(struct platform_device *pdev, struct brcm_info *info);
>> +void brcm_msi_set_regs(struct brcm_msi *chip);
>> +void brcm_msi_remove(struct brcm_msi *chip);
>> +#else
>> +static inline int brcm_msi_probe(struct platform_device *pdev,
>> +                              struct brcm_info *info)
>> +{
>> +     return -ENODEV;
>> +}
>> +
>> +static inline void brcm_msi_set_regs(struct brcm_msi *chip) {}
>> +static inline void brcm_msi_remove(struct brcm_msi *chip) {}
>> +#endif /* CONFIG_PCI_BRCMSTB_MSI */
>> +
>> +struct brcm_info {PCIE_IPROC_MSI
>> +     int rev;
>> +     u64 msi_target_addr;
>> +     void __iomem *base;
>> +     struct brcm_msi *msi;
>> +};
>> +
>>  #if defined(CONFIG_MIPS)PCIE_IPROC_MSI
>>  /* Broadcom MIPs HW implicitly does the swapping if necessary */
>>  #define bcm_readl(a)         __raw_readl(a)
>> --
>> 1.9.0.138.g2de3478
>>
--
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[PATCH 7/8] MIPS: BMIPS: add PCI bindings for 7425, 7435

[Jim Quinlan]

Adds the PCIe nodes for the Broadcom STB PCIe root complex.

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 arch/mips/boot/dts/brcm/bcm7425.dtsi     | 25 +++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm7435.dtsi     | 26 ++++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm97425svmb.dts |  4 ++++
 arch/mips/boot/dts/brcm/bcm97435svmb.dts |  4 ++++
 4 files changed, 59 insertions(+)

diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
index f56fb25..2c416f6 100644
--- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -494,4 +494,29 @@
 			status = "disabled";
 		};
 	};
+
+	pcie: pcie@10410000 {
+		reg = <0x10410000 0x830c>;
+		compatible = "brcm,bcm7425-pcie", "brcm,pci-plat-dev";
+		interrupts = <37>, <37>;
+		interrupt-names = "pcie", "msi";
+		interrupt-parent = <&periph_intc>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		linux,pci-domain = <0>;
+		brcm,ssc;
+		msi-controller;
+		#interrupt-cells = <1>;
+		/* 4x128mb windows */
+		ranges = <0x2000000 0x0 0xd0000000 0xd0000000 0 0x08000000>,
+			 <0x2000000 0x0 0xd8000000 0xd8000000 0 0x08000000>,
+			 <0x2000000 0x0 0xe0000000 0xe0000000 0 0x08000000>,
+			 <0x2000000 0x0 0xe8000000 0xe8000000 0 0x08000000>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &periph_intc 33
+				 0 0 0 2 &periph_intc 34
+				 0 0 0 3 &periph_intc 35
+				 0 0 0 4 &periph_intc 36>;
+	};
+
 };
diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi
index f2cead2..2f869e5 100644
--- a/arch/mips/boot/dts/brcm/bcm7435.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -509,4 +509,30 @@
 			status = "disabled";
 		};
 	};
+
+	pcie: pcie@10410000 {
+		reg = <0x10410000 0x930c>;
+		interrupts = <0x27>, <0x27>;
+		interrupt-names = "pcie", "msi";
+		interrupt-parent = <&periph_intc>;
+		compatible = "brcm,bcm7435-pcie", "brcm,pci-plat-dev";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		linux,pci-domain = <0>;
+		brcm,ssc;
+		msi-controller;
+		#interrupt-cells = <1>;
+		/* 4x128mb windows */
+		ranges = <0x2000000 0x0 0xd0000000 0xd0000000 0 0x08000000>,
+			 <0x2000000 0x0 0xd8000000 0xd8000000 0 0x08000000>,
+			 <0x2000000 0x0 0xe0000000 0xe0000000 0 0x08000000>,
+			 <0x2000000 0x0 0xe8000000 0xe8000000 0 0x08000000>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &periph_intc 35
+				 0 0 0 2 &periph_intc 36
+				 0 0 0 3 &periph_intc 37
+				 0 0 0 4 &periph_intc 38>;
+		status = "disabled";
+	};
+
 };
diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
index 73aa006..3a87ac5 100644
--- a/arch/mips/boot/dts/brcm/bcm97425svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
@@ -143,3 +143,7 @@
 &mspi {
 	status = "okay";
 };
+
+&pcie {
+	status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97435svmb.dts b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
index 0a915f3..456d024 100644
--- a/arch/mips/boot/dts/brcm/bcm97435svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
@@ -119,3 +119,7 @@
 &mspi {
 	status = "okay";
 };
+
+&pcie {
+	status = "okay";
+};
-- 
1.9.0.138.g2de3478

[PATCH 8/8] MIPS: BMIPS: enable PCI

[Jim Quinlan]

Adds the Kconfig hooks to enable the Broadcom STB PCIe root complex
driver for Broadcom MIPS systems.

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 arch/mips/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cb7fcc4..83ba54d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -209,6 +209,9 @@ config BMIPS_GENERIC
 	select BOOT_RAW
 	select NO_EXCEPT_FILL
 	select USE_OF
+	select HW_HAS_PCI
+	select PCI_DRIVERS_GENERIC
+	select PCI
 	select CEVT_R4K
 	select CSRC_R4K
 	select SYNC_R4K
-- 
1.9.0.138.g2de3478