From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1870DC77B7A for ; Tue, 16 May 2023 16:32:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230473AbjEPQcc (ORCPT ); Tue, 16 May 2023 12:32:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231272AbjEPQcU (ORCPT ); Tue, 16 May 2023 12:32:20 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E0FBAD34 for ; Tue, 16 May 2023 09:31:05 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-96aadfb19d7so958569166b.2 for ; Tue, 16 May 2023 09:31:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684254656; x=1686846656; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=xJWf/O6/bgY/LqCBnoW2lN4/EkslAxW6EAY6k6YXlL8=; b=Ojeg6VooufgIF0uisRWw0Cvxmi9BoTMv0rTldrBVrDfibSPOWTVVV+qXKhBSBkzpgz nPTcYzCg5yFNqh0d6x/w6WCnlAQhywQKvRMRChKYzlWR2NaCWvXkhx4xWPlYlFou/gJ/ k6ysIyLXLZ1BrjvOdSw/VkJlBfsEMQaX38VKbn3GnTPdQ89W+BQuOmEB4qYrYRztJ/sC EuKyP0ZN3yN7ZWC3uGdglk+AK+QGL98mJLAJD+WWKOcHxCLFqdbM+6xCUFx0ZkDxFZ6y 8PRamJbrerfVoyFekhqEBU8O+0cUdN7y3yuFEk+EM9RR/OaT751/rxb6Q1tlagp2txb4 KYqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684254656; x=1686846656; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=xJWf/O6/bgY/LqCBnoW2lN4/EkslAxW6EAY6k6YXlL8=; b=irjgPLG73cRdAp/vk0flGGWBR6Ym/+JCzKctWahINIMurzLUtaiIY60lqcNVXqPfzB fVeuOjcy8p5/nQ3Bzry5+XjsnXNyhVPJ3YNLT/cZO7O9OmxQSFUiPApQbKj4xQ6EUVVr 3B6CSEYy0mKZivSh0e9l1RwtEulCRDoBEe6MS9SHi0AKLsVo43vLmy6XmBv/BvWc2p4H 39L36yU6oy7ZFDW3Pyy5CRs3yc9r8Vh0DLjQa0dHX9OIGqTS+YJbIQY1F5R4E7D3jZXT o7Da8H4aGbKSSgNLhKhTICD5unKruXm1ttAI8KtF2eA/PgHnf484tkatAZ7wYNXMNkWb sJ2g== X-Gm-Message-State: AC+VfDz8HRL3GmygC3IGuN201mCoUD8u7WXbfJirajsSWtH7j5dFSivE FzUw9a51oCgh6+P/x7nr95rwtw== X-Google-Smtp-Source: ACHHUZ57Vra5TMrVsJpXvtgUTL/v2nF0I/s2y4tc2DOPScDQfuheRUVuNWcYvR1rvkgwwWSFcJpyvA== X-Received: by 2002:a17:906:db08:b0:965:fa80:bf1 with SMTP id xj8-20020a170906db0800b00965fa800bf1mr36026771ejb.32.1684254656537; Tue, 16 May 2023 09:30:56 -0700 (PDT) Received: from ?IPV6:2a02:810d:15c0:828:77d1:16a1:abe1:84fc? ([2a02:810d:15c0:828:77d1:16a1:abe1:84fc]) by smtp.gmail.com with ESMTPSA id hx7-20020a170906846700b00965a4350411sm11018102ejc.9.2023.05.16.09.30.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 May 2023 09:30:56 -0700 (PDT) Message-ID: <151169f7-dcdb-47f1-9616-67c3c388a233@linaro.org> Date: Tue, 16 May 2023 18:30:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH] arm64: dts: microchip: add missing cache properties Content-Language: en-US To: Rob Herring , Krzysztof Kozlowski , Lars Povlsen , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20230421223155.115339-1-krzysztof.kozlowski@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20230421223155.115339-1-krzysztof.kozlowski@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 22/04/2023 00:31, Krzysztof Kozlowski wrote: > As all level 2 and level 3 caches are unified, add required > cache-unified and cache-level properties to fix warnings like: > > sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property > > Signed-off-by: Krzysztof Kozlowski > > --- Anyone from Microchip picking this up? Best regards, Krzysztof