From: Jerome Brunet <jbrunet@baylibre.com>
To: Yixun Lan <yixun.lan@amlogic.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Carlo Caione <carlo@caione.org>,
Qiufang Dai <qiufang.dai@amlogic.com>,
Jian Hu <jian.hu@amlogic.com>,
linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 3/6] clk: meson-axg: add clock controller drivers
Date: Mon, 11 Dec 2017 11:21:42 +0100 [thread overview]
Message-ID: <1512987702.334.25.camel@baylibre.com> (raw)
In-Reply-To: <a6a9454f-be94-4fee-9083-f37eae2c1749@amlogic.com>
On Mon, 2017-12-11 at 18:16 +0800, Yixun Lan wrote:
> > Overall, the changes looks good to me.
> > I still have a few comments which I'd like to see addressed quickly after this
> > series is merged
>
> did you say that:
> you will merge these patches now, then I could send fixes later?
>
> or I can send another version (v7) to address this..
I'm OK taking this as it is but I'd like to see the comments addressed quickly.
Of course, If you prefer to make a v7, no one is stopping you.
Jerome
next prev parent reply other threads:[~2017-12-11 10:21 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-11 6:48 [PATCH v6 0/6] add clk controller driver for Meson-AXG SoC Yixun Lan
2017-12-11 6:48 ` [PATCH v6 1/6] dt-bindings: clock: add compatible variant for the Meson-AXG Yixun Lan
2017-12-11 6:48 ` [PATCH v6 2/6] clk: meson-axg: add clocks dt-bindings required header Yixun Lan
2017-12-11 6:48 ` [PATCH v6 3/6] clk: meson-axg: add clock controller drivers Yixun Lan
2017-12-11 9:46 ` Jerome Brunet
2017-12-11 10:16 ` Yixun Lan
2017-12-11 10:21 ` Jerome Brunet [this message]
2017-12-11 6:48 ` [PATCH v6 4/6] clk: meson: make the spinlock naming more specific Yixun Lan
[not found] ` <20171211064853.32111-5-yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
2017-12-11 9:26 ` Jerome Brunet
2017-12-11 11:27 ` Jerome Brunet
[not found] ` <20171211064853.32111-1-yixun.lan-LpR1jeaWuhtBDgjK7y7TUQ@public.gmane.org>
2017-12-11 6:48 ` [PATCH v6 5/6] arm64: dts: meson-axg: add clock DT info for Meson AXG SoC Yixun Lan
2017-12-11 6:48 ` [PATCH v6 6/6] arm64: dts: meson-axg: switch uart_ao clock to CLK81 Yixun Lan
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