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From: Abhishek Sahu <absahu@codeaurora.org>
To: Stephen Boyd <sboyd@codeaurora.org>,
	Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Andy Gross <andy.gross@linaro.org>,
	David Brown <david.brown@linaro.org>,
	Mark Rutland <mark.rutland@arm.com>,
	linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Abhishek Sahu <absahu@codeaurora.org>
Subject: [PATCH v2 03/11] clk: qcom: ipq8074: fix missing GPLL0 divider width
Date: Wed, 13 Dec 2017 19:55:34 +0530	[thread overview]
Message-ID: <1513175142-3702-4-git-send-email-absahu@codeaurora.org> (raw)
In-Reply-To: <1513175142-3702-1-git-send-email-absahu@codeaurora.org>

GPLL0 uses 4 bits post divider which should be specified
in clock driver structure.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq8074.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index ed2d00f..99906f6 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -84,6 +84,7 @@ enum {
 static struct clk_alpha_pll_postdiv gpll0 = {
 	.offset = 0x21000,
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+	.width = 4,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gpll0",
 		.parent_names = (const char *[]){
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


  parent reply	other threads:[~2017-12-13 14:25 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-13 14:25 [PATCH v2 00/11] Add remaining clocks for QCOM IPQ8074 Abhishek Sahu
     [not found] ` <1513175142-3702-1-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-12-13 14:25   ` [PATCH v2 01/11] clk: qcom: add read-only divider operations Abhishek Sahu
2017-12-22  0:23     ` Stephen Boyd
2017-12-13 14:25   ` [PATCH v2 05/11] clk: qcom: ipq8074: add remaining PLL’s Abhishek Sahu
2017-12-22  0:23     ` Stephen Boyd
2017-12-13 14:25   ` [PATCH v2 06/11] clk: qcom: ipq8074: add PCIE, USB and SDCC clocks Abhishek Sahu
2017-12-22  0:24     ` Stephen Boyd
2017-12-13 14:25   ` [PATCH v2 07/11] clk: qcom: ipq8074: add NSS clocks Abhishek Sahu
2017-12-22  0:24     ` Stephen Boyd
2017-12-13 14:25   ` [PATCH v2 09/11] clk: qcom: ipq8074: add GP and Crypto clocks Abhishek Sahu
2017-12-22  0:24     ` Stephen Boyd
2017-12-13 14:25 ` [PATCH v2 02/11] clk: qcom: add parent map for regmap mux Abhishek Sahu
2017-12-22  0:23   ` Stephen Boyd
2017-12-13 14:25 ` Abhishek Sahu [this message]
2017-12-22  0:23   ` [PATCH v2 03/11] clk: qcom: ipq8074: fix missing GPLL0 divider width Stephen Boyd
2017-12-13 14:25 ` [PATCH v2 04/11] dt-bindings: clock: qcom: add remaining clocks for IPQ8074 Abhishek Sahu
2017-12-15 23:09   ` Rob Herring
2017-12-22  0:24   ` Stephen Boyd
2017-12-13 14:25 ` [PATCH v2 08/11] clk: qcom: ipq8074: add NSS ethernet port clocks Abhishek Sahu
     [not found]   ` <1513175142-3702-9-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-12-22  0:24     ` Stephen Boyd
2017-12-13 14:25 ` [PATCH v2 10/11] dt-bindings: clock: qcom: add misc resets for PCIE and NSS Abhishek Sahu
     [not found]   ` <1513175142-3702-11-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-12-15 23:10     ` Rob Herring
2017-12-22  0:24     ` Stephen Boyd
2017-12-13 14:25 ` [PATCH v2 11/11] clk: qcom: ipq8074: " Abhishek Sahu
2017-12-22  0:24   ` Stephen Boyd

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