From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kieran Bingham Subject: [PATCH v2 3/4] arm64: dts: renesas: r8a7795: Fix register mappings on VSPs Date: Tue, 13 Feb 2018 19:30:36 +0000 Message-ID: <1518550237-16753-4-git-send-email-kbingham@kernel.org> References: <1518550237-16753-1-git-send-email-kbingham@kernel.org> Return-path: In-Reply-To: <1518550237-16753-1-git-send-email-kbingham@kernel.org> Sender: linux-renesas-soc-owner@vger.kernel.org To: linux-renesas-soc@vger.kernel.org, Simon Horman , Laurent Pinchart , Kieran Bingham Cc: Kieran Bingham , Magnus Damm , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM64 PORT AARCH64 ARCHITECTURE" , open list List-Id: devicetree@vger.kernel.org From: Kieran Bingham The VSPD includes a CLUT on RPF2. Ensure that the register space is mapped correctly to support this. Signed-off-by: Kieran Bingham --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 1f32340af2d1..772991db8820 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -2607,7 +2607,7 @@ vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x4000>; + reg = <0 0xfea20000 0 0x8000>; interrupts = ; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2627,7 +2627,7 @@ vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x4000>; + reg = <0 0xfea28000 0 0x8000>; interrupts = ; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2647,7 +2647,7 @@ vspd2: vsp@fea30000 { compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x4000>; + reg = <0 0xfea30000 0 0x8000>; interrupts = ; clocks = <&cpg CPG_MOD 621>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; -- 2.7.4