From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kieran Bingham Subject: [PATCH v3 3/5] arm64: dts: renesas: r8a7795-es1: Fix register mappings on VSPs Date: Wed, 14 Feb 2018 09:55:06 +0000 Message-ID: <1518602108-1724-4-git-send-email-kbingham@kernel.org> References: <1518602108-1724-1-git-send-email-kbingham@kernel.org> Return-path: In-Reply-To: <1518602108-1724-1-git-send-email-kbingham@kernel.org> Sender: linux-kernel-owner@vger.kernel.org To: linux-renesas-soc@vger.kernel.org, Simon Horman , Laurent Pinchart , Kieran Bingham Cc: Kieran Bingham , Magnus Damm , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM64 PORT AARCH64 ARCHITECTURE" , open list List-Id: devicetree@vger.kernel.org From: Kieran Bingham The VSPD includes a CLUT on RPF2. Ensure that the register space is mapped correctly to support this. Signed-off-by: Kieran Bingham --- arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index ed553338b4d4..1adfe6cad268 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi @@ -80,7 +80,7 @@ vspd3: vsp@fea38000 { compatible = "renesas,vsp2"; - reg = <0 0xfea38000 0 0x4000>; + reg = <0 0xfea38000 0 0x8000>; interrupts = ; clocks = <&cpg CPG_MOD 620>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; -- 2.7.4