* [PATCH v2 0/6] Add endpoint driver for Rockchip PCIe controller
@ 2018-02-23 1:15 Shawn Lin
[not found] ` <1519348503-243259-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
0 siblings, 1 reply; 15+ messages in thread
From: Shawn Lin @ 2018-02-23 1:15 UTC (permalink / raw)
To: Bjorn Helgaas, Lorenzo Pieralisi
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner,
linux-pci-u79uwXL29TY76Z2rM5mHXA, Shawn Lin,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring
Patch 1 firstly move the whole Rockchip PCIe host driver from
drivers/pci/host to a new folder, driver/pci/rockchip/, and rename
pcie-rockchip.c to pcie-rockchip-host.c. It also update the
Kconfig/Makefile etc to repect this change.
Then patch 2 and patch 3 are trying to spilt out some common code in
preparation for adding endponit controller driver support.
Patch 4 rename rockchip-pcie.txt to rockchip-pcie-host.txt.
Patch 5 adds endpoint controller driver support as well as the new
documentation, rockchip-pcie-ep.txt, introduced by patch 6.
Changes in v2:
- remove rockchip,rk3399-pcie-host compatible(Suggested by Rob)
- fix some error handling
Shawn Lin (6):
PCI: rockchip: Create individual folder for rockchip drivers
PCI: rockchip: Split out common function to parse DT
PCI: rockchip: Spilt out common function to init controller
dt-bindings: PCI: rockchip: Rename rockchip-pcie.txt to
rockchip-pcie-host.txt
PCI: rockchip: Add Endpoint controller driver for Rockchip PCIe
controller
dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe endpoint
controller
.../devicetree/bindings/pci/rockchip-pcie-ep.txt | 62 ++
.../{rockchip-pcie.txt => rockchip-pcie-host.txt} | 0
MAINTAINERS | 4 +-
drivers/pci/Kconfig | 1 +
drivers/pci/Makefile | 2 +
drivers/pci/host/Kconfig | 11 -
drivers/pci/host/Makefile | 1 -
drivers/pci/rockchip/Kconfig | 32 +
drivers/pci/rockchip/Makefile | 4 +
drivers/pci/rockchip/pcie-rockchip-ep.c | 641 +++++++++++++++++++++
.../pcie-rockchip-host.c} | 594 +------------------
drivers/pci/rockchip/pcie-rockchip.c | 417 ++++++++++++++
drivers/pci/rockchip/pcie-rockchip.h | 343 +++++++++++
13 files changed, 1517 insertions(+), 595 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt
rename Documentation/devicetree/bindings/pci/{rockchip-pcie.txt => rockchip-pcie-host.txt} (100%)
create mode 100644 drivers/pci/rockchip/Kconfig
create mode 100644 drivers/pci/rockchip/Makefile
create mode 100644 drivers/pci/rockchip/pcie-rockchip-ep.c
rename drivers/pci/{host/pcie-rockchip.c => rockchip/pcie-rockchip-host.c} (61%)
create mode 100644 drivers/pci/rockchip/pcie-rockchip.c
create mode 100644 drivers/pci/rockchip/pcie-rockchip.h
--
1.9.1
^ permalink raw reply [flat|nested] 15+ messages in thread[parent not found: <1519348503-243259-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* [PATCH v2 1/6] PCI: rockchip: Create individual folder for rockchip drivers [not found] ` <1519348503-243259-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> @ 2018-02-23 1:15 ` Shawn Lin 2018-02-23 1:16 ` [PATCH v2 2/6] PCI: rockchip: Split out common function to parse DT Shawn Lin ` (4 subsequent siblings) 5 siblings, 0 replies; 15+ messages in thread From: Shawn Lin @ 2018-02-23 1:15 UTC (permalink / raw) To: Bjorn Helgaas, Lorenzo Pieralisi Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA, Shawn Lin, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring In preparation for introducing End-Point driver for Rockchip PCIe controller, we create a new folder to follow the convention of dwc and cadence. Then we rename the host driver from pcie-rockchip.c to pcie-rockchip-host.c, and only leave some common functions in pcie-rockchip.c in order to be reused for both of host and EP drivers. Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- Changes in v2: None MAINTAINERS | 4 +- drivers/pci/Kconfig | 1 + drivers/pci/Makefile | 2 + drivers/pci/host/Kconfig | 11 - drivers/pci/host/Makefile | 1 - drivers/pci/rockchip/Kconfig | 20 ++ drivers/pci/rockchip/Makefile | 3 + .../pcie-rockchip-host.c} | 344 +-------------------- drivers/pci/rockchip/pcie-rockchip.c | 141 +++++++++ drivers/pci/rockchip/pcie-rockchip.h | 246 +++++++++++++++ 10 files changed, 416 insertions(+), 357 deletions(-) create mode 100644 drivers/pci/rockchip/Kconfig create mode 100644 drivers/pci/rockchip/Makefile rename drivers/pci/{host/pcie-rockchip.c => rockchip/pcie-rockchip-host.c} (75%) create mode 100644 drivers/pci/rockchip/pcie-rockchip.c create mode 100644 drivers/pci/rockchip/pcie-rockchip.h diff --git a/MAINTAINERS b/MAINTAINERS index 3df0e47..e01d2b8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10831,8 +10831,8 @@ M: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> L: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org L: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org S: Maintained -F: Documentation/devicetree/bindings/pci/rockchip-pcie.txt -F: drivers/pci/host/pcie-rockchip.c +F: Documentation/devicetree/bindings/pci/rockchip-pcie* +F: drivers/pci/rockchip/* PCI DRIVER FOR V3 SEMICONDUCTOR V360EPC M: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 34b56a8..b85ad40 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -141,4 +141,5 @@ source "drivers/pci/cadence/Kconfig" source "drivers/pci/dwc/Kconfig" source "drivers/pci/host/Kconfig" source "drivers/pci/endpoint/Kconfig" +source "drivers/pci/rockchip/Kconfig" source "drivers/pci/switch/Kconfig" diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 9419709..8434afb 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -55,6 +55,8 @@ obj-y += switch/ obj-$(CONFIG_PCI_ENDPOINT) += endpoint/ +obj-$(CONFIG_PCIE_ROCKCHIP) += rockchip/ + # Endpoint library must be initialized before its users obj-$(CONFIG_PCIE_CADENCE) += cadence/ # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index a4ed748..05b4d3b 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -177,17 +177,6 @@ config PCI_HOST_THUNDER_ECAM help Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs. -config PCIE_ROCKCHIP - tristate "Rockchip PCIe controller" - depends on ARCH_ROCKCHIP || COMPILE_TEST - depends on OF - depends on PCI_MSI_IRQ_DOMAIN - select MFD_SYSCON - help - Say Y here if you want internal PCI support on Rockchip SoC. - There is 1 internal PCIe port available to support GEN2 with - 4 slots. - config PCIE_MEDIATEK bool "MediaTek PCIe controller" depends on (ARM || ARM64) && (ARCH_MEDIATEK || COMPILE_TEST) diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile index 3b10591..ceab86a 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile @@ -19,7 +19,6 @@ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o -obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o obj-$(CONFIG_VMD) += vmd.o diff --git a/drivers/pci/rockchip/Kconfig b/drivers/pci/rockchip/Kconfig new file mode 100644 index 0000000..d655b77 --- /dev/null +++ b/drivers/pci/rockchip/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0 + +menu "Rockchip PCIe controllers support" + +config PCIE_ROCKCHIP + bool + +config PCIE_ROCKCHIP_HOST + tristate "Rockchip PCIe host controller" + depends on ARCH_ROCKCHIP || COMPILE_TEST + depends on OF + depends on PCI_MSI_IRQ_DOMAIN + select MFD_SYSCON + select PCIE_ROCKCHIP + help + Say Y here if you want internal PCI support on Rockchip SoC. + There is 1 internal PCIe port available to support GEN2 with + 4 slots. + +endmenu diff --git a/drivers/pci/rockchip/Makefile b/drivers/pci/rockchip/Makefile new file mode 100644 index 0000000..0af40db --- /dev/null +++ b/drivers/pci/rockchip/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o +obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/rockchip/pcie-rockchip-host.c similarity index 75% rename from drivers/pci/host/pcie-rockchip.c rename to drivers/pci/rockchip/pcie-rockchip-host.c index f1e8f97..563f696 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/rockchip/pcie-rockchip-host.c @@ -36,226 +36,7 @@ #include <linux/reset.h> #include <linux/regmap.h> -/* - * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16 - * bits. This allows atomic updates of the register without locking. - */ -#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) -#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) - -#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4) -#define MAX_LANE_NUM 4 - -#define PCIE_CLIENT_BASE 0x0 -#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) -#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001) -#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002) -#define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008) -#define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x)) -#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) -#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) -#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) -#define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) -#define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0) -#define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18 -#define PCIE_CLIENT_DEBUG_LTSSM_L2 0x19 -#define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48) -#define PCIE_CLIENT_LINK_STATUS_UP 0x00300000 -#define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000 -#define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c) -#define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50) -#define PCIE_CLIENT_INTR_MASK GENMASK(8, 5) -#define PCIE_CLIENT_INTR_SHIFT 5 -#define PCIE_CLIENT_INT_LEGACY_DONE BIT(15) -#define PCIE_CLIENT_INT_MSG BIT(14) -#define PCIE_CLIENT_INT_HOT_RST BIT(13) -#define PCIE_CLIENT_INT_DPA BIT(12) -#define PCIE_CLIENT_INT_FATAL_ERR BIT(11) -#define PCIE_CLIENT_INT_NFATAL_ERR BIT(10) -#define PCIE_CLIENT_INT_CORR_ERR BIT(9) -#define PCIE_CLIENT_INT_INTD BIT(8) -#define PCIE_CLIENT_INT_INTC BIT(7) -#define PCIE_CLIENT_INT_INTB BIT(6) -#define PCIE_CLIENT_INT_INTA BIT(5) -#define PCIE_CLIENT_INT_LOCAL BIT(4) -#define PCIE_CLIENT_INT_UDMA BIT(3) -#define PCIE_CLIENT_INT_PHY BIT(2) -#define PCIE_CLIENT_INT_HOT_PLUG BIT(1) -#define PCIE_CLIENT_INT_PWR_STCG BIT(0) - -#define PCIE_CLIENT_INT_LEGACY \ - (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \ - PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD) - -#define PCIE_CLIENT_INT_CLI \ - (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \ - PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \ - PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \ - PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \ - PCIE_CLIENT_INT_PHY) - -#define PCIE_CORE_CTRL_MGMT_BASE 0x900000 -#define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000) -#define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008 -#define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018 -#define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006 -#define PCIE_CORE_PL_CONF_LANE_SHIFT 1 -#define PCIE_CORE_CTRL_PLC1 (PCIE_CORE_CTRL_MGMT_BASE + 0x004) -#define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8) -#define PCIE_CORE_CTRL_PLC1_FTS_SHIFT 8 -#define PCIE_CORE_CTRL_PLC1_FTS_CNT 0xffff -#define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020) -#define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000 -#define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16 -#define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \ - (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT) -#define PCIE_CORE_LANE_MAP (PCIE_CORE_CTRL_MGMT_BASE + 0x200) -#define PCIE_CORE_LANE_MAP_MASK 0x0000000f -#define PCIE_CORE_LANE_MAP_REVERSE BIT(16) -#define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c) -#define PCIE_CORE_INT_PRFPE BIT(0) -#define PCIE_CORE_INT_CRFPE BIT(1) -#define PCIE_CORE_INT_RRPE BIT(2) -#define PCIE_CORE_INT_PRFO BIT(3) -#define PCIE_CORE_INT_CRFO BIT(4) -#define PCIE_CORE_INT_RT BIT(5) -#define PCIE_CORE_INT_RTR BIT(6) -#define PCIE_CORE_INT_PE BIT(7) -#define PCIE_CORE_INT_MTR BIT(8) -#define PCIE_CORE_INT_UCR BIT(9) -#define PCIE_CORE_INT_FCE BIT(10) -#define PCIE_CORE_INT_CT BIT(11) -#define PCIE_CORE_INT_UTC BIT(18) -#define PCIE_CORE_INT_MMVC BIT(19) -#define PCIE_CORE_CONFIG_VENDOR (PCIE_CORE_CTRL_MGMT_BASE + 0x44) -#define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210) -#define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300) - -#define PCIE_CORE_INT \ - (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \ - PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \ - PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \ - PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \ - PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \ - PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \ - PCIE_CORE_INT_MMVC) - -#define PCIE_RC_CONFIG_NORMAL_BASE 0x800000 -#define PCIE_RC_CONFIG_BASE 0xa00000 -#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) -#define PCIE_RC_CONFIG_SCC_SHIFT 16 -#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) -#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 -#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff -#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 -#define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) -#define PCIE_RC_CONFIG_DCSR_MPS_MASK GENMASK(7, 5) -#define PCIE_RC_CONFIG_DCSR_MPS_256 (0x1 << 5) -#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) -#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) -#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) -#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) -#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) -#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20) - -#define PCIE_CORE_AXI_CONF_BASE 0xc00000 -#define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0) -#define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f -#define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00 -#define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4) -#define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8) -#define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc) - -#define PCIE_CORE_AXI_INBOUND_BASE 0xc00800 -#define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0) -#define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f -#define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00 -#define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4) - -/* Size of one AXI Region (not Region 0) */ -#define AXI_REGION_SIZE BIT(20) -/* Size of Region 0, equal to sum of sizes of other regions */ -#define AXI_REGION_0_SIZE (32 * (0x1 << 20)) -#define OB_REG_SIZE_SHIFT 5 -#define IB_ROOT_PORT_REG_SIZE_SHIFT 3 -#define AXI_WRAPPER_IO_WRITE 0x6 -#define AXI_WRAPPER_MEM_WRITE 0x2 -#define AXI_WRAPPER_TYPE0_CFG 0xa -#define AXI_WRAPPER_TYPE1_CFG 0xb -#define AXI_WRAPPER_NOR_MSG 0xc - -#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3 -#define MIN_AXI_ADDR_BITS_PASSED 8 -#define PCIE_RC_SEND_PME_OFF 0x11960 -#define ROCKCHIP_VENDOR_ID 0x1d87 -#define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20) -#define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15) -#define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12) -#define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0) -#define PCIE_ECAM_ADDR(bus, dev, func, reg) \ - (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \ - PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg)) -#define PCIE_LINK_IS_L2(x) \ - (((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2) -#define PCIE_LINK_UP(x) \ - (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP) -#define PCIE_LINK_IS_GEN2(x) \ - (((x) & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) - -#define RC_REGION_0_ADDR_TRANS_H 0x00000000 -#define RC_REGION_0_ADDR_TRANS_L 0x00000000 -#define RC_REGION_0_PASS_BITS (25 - 1) -#define RC_REGION_0_TYPE_MASK GENMASK(3, 0) -#define MAX_AXI_WRAPPER_REGION_NUM 33 - -struct rockchip_pcie { - void __iomem *reg_base; /* DT axi-base */ - void __iomem *apb_base; /* DT apb-base */ - bool legacy_phy; - struct phy *phys[MAX_LANE_NUM]; - struct reset_control *core_rst; - struct reset_control *mgmt_rst; - struct reset_control *mgmt_sticky_rst; - struct reset_control *pipe_rst; - struct reset_control *pm_rst; - struct reset_control *aclk_rst; - struct reset_control *pclk_rst; - struct clk *aclk_pcie; - struct clk *aclk_perf_pcie; - struct clk *hclk_pcie; - struct clk *clk_pcie_pm; - struct regulator *vpcie12v; /* 12V power supply */ - struct regulator *vpcie3v3; /* 3.3V power supply */ - struct regulator *vpcie1v8; /* 1.8V power supply */ - struct regulator *vpcie0v9; /* 0.9V power supply */ - struct gpio_desc *ep_gpio; - u32 lanes; - u8 lanes_map; - u8 root_bus_nr; - int link_gen; - struct device *dev; - struct irq_domain *irq_domain; - int offset; - struct pci_bus *root_bus; - struct resource *io; - phys_addr_t io_bus_addr; - u32 io_size; - void __iomem *msg_region; - u32 mem_size; - phys_addr_t msg_bus_addr; - phys_addr_t mem_bus_addr; -}; - -static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg) -{ - return readl(rockchip->apb_base + reg); -} - -static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, - u32 reg) -{ - writel(val, rockchip->apb_base + reg); -} +#include "pcie-rockchip.h" static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip) { @@ -374,26 +155,6 @@ static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip, return PCIBIOS_SUCCESSFUL; } -static void rockchip_pcie_cfg_configuration_accesses( - struct rockchip_pcie *rockchip, u32 type) -{ - u32 ob_desc_0; - - /* Configuration Accesses for region 0 */ - rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF); - - rockchip_pcie_write(rockchip, - (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS), - PCIE_CORE_OB_REGION_ADDR0); - rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H, - PCIE_CORE_OB_REGION_ADDR1); - ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0); - ob_desc_0 &= ~(RC_REGION_0_TYPE_MASK); - ob_desc_0 |= (type | (0x1 << 23)); - rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0); - rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1); -} - static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) @@ -760,18 +521,6 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) return err; } -static void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip) -{ - int i; - - for (i = 0; i < MAX_LANE_NUM; i++) { - /* inactive lanes are already powered off */ - if (rockchip->lanes_map & BIT(i)) - phy_power_off(rockchip->phys[i]); - phy_exit(rockchip->phys[i]); - } -} - static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg) { struct rockchip_pcie *rockchip = arg; @@ -908,47 +657,6 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) chained_irq_exit(chip, desc); } -static int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip) -{ - struct device *dev = rockchip->dev; - struct phy *phy; - char *name; - u32 i; - - phy = devm_phy_get(dev, "pcie-phy"); - if (!IS_ERR(phy)) { - rockchip->legacy_phy = true; - rockchip->phys[0] = phy; - dev_warn(dev, "legacy phy model is deprecated!\n"); - return 0; - } - - if (PTR_ERR(phy) == -EPROBE_DEFER) - return PTR_ERR(phy); - - dev_dbg(dev, "missing legacy phy; search for per-lane PHY\n"); - - for (i = 0; i < MAX_LANE_NUM; i++) { - name = kasprintf(GFP_KERNEL, "pcie-phy-%u", i); - if (!name) - return -ENOMEM; - - phy = devm_of_phy_get(dev, dev->of_node, name); - kfree(name); - - if (IS_ERR(phy)) { - if (PTR_ERR(phy) != -EPROBE_DEFER) - dev_err(dev, "missing phy for lane %d: %ld\n", - i, PTR_ERR(phy)); - return PTR_ERR(phy); - } - - rockchip->phys[i] = phy; - } - - return 0; -} - static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip) { int irq, err; @@ -1393,56 +1101,6 @@ static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip) return 0; } -static int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) -{ - struct device *dev = rockchip->dev; - int err; - - err = clk_prepare_enable(rockchip->aclk_pcie); - if (err) { - dev_err(dev, "unable to enable aclk_pcie clock\n"); - return err; - } - - err = clk_prepare_enable(rockchip->aclk_perf_pcie); - if (err) { - dev_err(dev, "unable to enable aclk_perf_pcie clock\n"); - goto err_aclk_perf_pcie; - } - - err = clk_prepare_enable(rockchip->hclk_pcie); - if (err) { - dev_err(dev, "unable to enable hclk_pcie clock\n"); - goto err_hclk_pcie; - } - - err = clk_prepare_enable(rockchip->clk_pcie_pm); - if (err) { - dev_err(dev, "unable to enable clk_pcie_pm clock\n"); - goto err_clk_pcie_pm; - } - - return 0; - -err_clk_pcie_pm: - clk_disable_unprepare(rockchip->hclk_pcie); -err_hclk_pcie: - clk_disable_unprepare(rockchip->aclk_perf_pcie); -err_aclk_perf_pcie: - clk_disable_unprepare(rockchip->aclk_pcie); - return err; -} - -static void rockchip_pcie_disable_clocks(void *data) -{ - struct rockchip_pcie *rockchip = data; - - clk_disable_unprepare(rockchip->clk_pcie_pm); - clk_disable_unprepare(rockchip->hclk_pcie); - clk_disable_unprepare(rockchip->aclk_perf_pcie); - clk_disable_unprepare(rockchip->aclk_pcie); -} - static int __maybe_unused rockchip_pcie_suspend_noirq(struct device *dev) { struct rockchip_pcie *rockchip = dev_get_drvdata(dev); diff --git a/drivers/pci/rockchip/pcie-rockchip.c b/drivers/pci/rockchip/pcie-rockchip.c new file mode 100644 index 0000000..c7614f9 --- /dev/null +++ b/drivers/pci/rockchip/pcie-rockchip.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Rockchip AXI PCIe host controller driver + * + * Copyright (c) 2016 Rockchip, Inc. + * + * Author: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> + * Wenrui Li <wenrui.li-TNX95d0MmH7DzftRWevZcw@public.gmane.org> + * + * Bits taken from Synopsys DesignWare Host controller driver and + * ARM PCI Host generic driver. + */ + +#include <linux/clk.h> +#include <linux/phy/phy.h> + +#include "pcie-rockchip.h" + +int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip) +{ + struct device *dev = rockchip->dev; + struct phy *phy; + char *name; + u32 i; + + phy = devm_phy_get(dev, "pcie-phy"); + if (!IS_ERR(phy)) { + rockchip->legacy_phy = true; + rockchip->phys[0] = phy; + dev_warn(dev, "legacy phy model is deprecated!\n"); + return 0; + } + + if (PTR_ERR(phy) == -EPROBE_DEFER) + return PTR_ERR(phy); + + dev_dbg(dev, "missing legacy phy; search for per-lane PHY\n"); + + for (i = 0; i < MAX_LANE_NUM; i++) { + name = kasprintf(GFP_KERNEL, "pcie-phy-%u", i); + if (!name) + return -ENOMEM; + + phy = devm_of_phy_get(dev, dev->of_node, name); + kfree(name); + + if (IS_ERR(phy)) { + if (PTR_ERR(phy) != -EPROBE_DEFER) + dev_err(dev, "missing phy for lane %d: %ld\n", + i, PTR_ERR(phy)); + return PTR_ERR(phy); + } + + rockchip->phys[i] = phy; + } + + return 0; +} + + +void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip) +{ + int i; + + for (i = 0; i < MAX_LANE_NUM; i++) { + /* inactive lanes are already powered off */ + if (rockchip->lanes_map & BIT(i)) + phy_power_off(rockchip->phys[i]); + phy_exit(rockchip->phys[i]); + } +} + +int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) +{ + struct device *dev = rockchip->dev; + int err; + + err = clk_prepare_enable(rockchip->aclk_pcie); + if (err) { + dev_err(dev, "unable to enable aclk_pcie clock\n"); + return err; + } + + err = clk_prepare_enable(rockchip->aclk_perf_pcie); + if (err) { + dev_err(dev, "unable to enable aclk_perf_pcie clock\n"); + goto err_aclk_perf_pcie; + } + + err = clk_prepare_enable(rockchip->hclk_pcie); + if (err) { + dev_err(dev, "unable to enable hclk_pcie clock\n"); + goto err_hclk_pcie; + } + + err = clk_prepare_enable(rockchip->clk_pcie_pm); + if (err) { + dev_err(dev, "unable to enable clk_pcie_pm clock\n"); + goto err_clk_pcie_pm; + } + + return 0; + +err_clk_pcie_pm: + clk_disable_unprepare(rockchip->hclk_pcie); +err_hclk_pcie: + clk_disable_unprepare(rockchip->aclk_perf_pcie); +err_aclk_perf_pcie: + clk_disable_unprepare(rockchip->aclk_pcie); + return err; +} + +void rockchip_pcie_disable_clocks(void *data) +{ + struct rockchip_pcie *rockchip = data; + + clk_disable_unprepare(rockchip->clk_pcie_pm); + clk_disable_unprepare(rockchip->hclk_pcie); + clk_disable_unprepare(rockchip->aclk_perf_pcie); + clk_disable_unprepare(rockchip->aclk_pcie); +} + +void rockchip_pcie_cfg_configuration_accesses( + struct rockchip_pcie *rockchip, u32 type) +{ + u32 ob_desc_0; + + /* Configuration Accesses for region 0 */ + rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF); + + rockchip_pcie_write(rockchip, + (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS), + PCIE_CORE_OB_REGION_ADDR0); + rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H, + PCIE_CORE_OB_REGION_ADDR1); + ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0); + ob_desc_0 &= ~(RC_REGION_0_TYPE_MASK); + ob_desc_0 |= (type | (0x1 << 23)); + rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0); + rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1); +} diff --git a/drivers/pci/rockchip/pcie-rockchip.h b/drivers/pci/rockchip/pcie-rockchip.h new file mode 100644 index 0000000..9e0cf2e --- /dev/null +++ b/drivers/pci/rockchip/pcie-rockchip.h @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Rockchip AXI PCIe controller driver + * + * Copyright (c) 2018 Rockchip, Inc. + * + * Author: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> + * + */ + +#ifndef _PCIE_ROCKCHIP_H +#define _PCIE_ROCKCHIP_H + +#include <linux/kernel.h> +#include <linux/pci.h> + +/* + * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16 + * bits. This allows atomic updates of the register without locking. + */ +#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) +#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) + +#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4) +#define MAX_LANE_NUM 4 + +#define PCIE_CLIENT_BASE 0x0 +#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) +#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001) +#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002) +#define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008) +#define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x)) +#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) +#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) +#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) +#define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) +#define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0) +#define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18 +#define PCIE_CLIENT_DEBUG_LTSSM_L2 0x19 +#define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48) +#define PCIE_CLIENT_LINK_STATUS_UP 0x00300000 +#define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000 +#define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c) +#define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50) +#define PCIE_CLIENT_INTR_MASK GENMASK(8, 5) +#define PCIE_CLIENT_INTR_SHIFT 5 +#define PCIE_CLIENT_INT_LEGACY_DONE BIT(15) +#define PCIE_CLIENT_INT_MSG BIT(14) +#define PCIE_CLIENT_INT_HOT_RST BIT(13) +#define PCIE_CLIENT_INT_DPA BIT(12) +#define PCIE_CLIENT_INT_FATAL_ERR BIT(11) +#define PCIE_CLIENT_INT_NFATAL_ERR BIT(10) +#define PCIE_CLIENT_INT_CORR_ERR BIT(9) +#define PCIE_CLIENT_INT_INTD BIT(8) +#define PCIE_CLIENT_INT_INTC BIT(7) +#define PCIE_CLIENT_INT_INTB BIT(6) +#define PCIE_CLIENT_INT_INTA BIT(5) +#define PCIE_CLIENT_INT_LOCAL BIT(4) +#define PCIE_CLIENT_INT_UDMA BIT(3) +#define PCIE_CLIENT_INT_PHY BIT(2) +#define PCIE_CLIENT_INT_HOT_PLUG BIT(1) +#define PCIE_CLIENT_INT_PWR_STCG BIT(0) + +#define PCIE_CLIENT_INT_LEGACY \ + (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \ + PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD) + +#define PCIE_CLIENT_INT_CLI \ + (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \ + PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \ + PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \ + PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \ + PCIE_CLIENT_INT_PHY) + +#define PCIE_CORE_CTRL_MGMT_BASE 0x900000 +#define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000) +#define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008 +#define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018 +#define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006 +#define PCIE_CORE_PL_CONF_LANE_SHIFT 1 +#define PCIE_CORE_CTRL_PLC1 (PCIE_CORE_CTRL_MGMT_BASE + 0x004) +#define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8) +#define PCIE_CORE_CTRL_PLC1_FTS_SHIFT 8 +#define PCIE_CORE_CTRL_PLC1_FTS_CNT 0xffff +#define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020) +#define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000 +#define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16 +#define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \ + (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT) +#define PCIE_CORE_LANE_MAP (PCIE_CORE_CTRL_MGMT_BASE + 0x200) +#define PCIE_CORE_LANE_MAP_MASK 0x0000000f +#define PCIE_CORE_LANE_MAP_REVERSE BIT(16) +#define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c) +#define PCIE_CORE_INT_PRFPE BIT(0) +#define PCIE_CORE_INT_CRFPE BIT(1) +#define PCIE_CORE_INT_RRPE BIT(2) +#define PCIE_CORE_INT_PRFO BIT(3) +#define PCIE_CORE_INT_CRFO BIT(4) +#define PCIE_CORE_INT_RT BIT(5) +#define PCIE_CORE_INT_RTR BIT(6) +#define PCIE_CORE_INT_PE BIT(7) +#define PCIE_CORE_INT_MTR BIT(8) +#define PCIE_CORE_INT_UCR BIT(9) +#define PCIE_CORE_INT_FCE BIT(10) +#define PCIE_CORE_INT_CT BIT(11) +#define PCIE_CORE_INT_UTC BIT(18) +#define PCIE_CORE_INT_MMVC BIT(19) +#define PCIE_CORE_CONFIG_VENDOR (PCIE_CORE_CTRL_MGMT_BASE + 0x44) +#define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210) +#define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300) + +#define PCIE_CORE_INT \ + (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \ + PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \ + PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \ + PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \ + PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \ + PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \ + PCIE_CORE_INT_MMVC) + +#define PCIE_RC_CONFIG_NORMAL_BASE 0x800000 +#define PCIE_RC_CONFIG_BASE 0xa00000 +#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) +#define PCIE_RC_CONFIG_SCC_SHIFT 16 +#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) +#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 +#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff +#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 +#define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) +#define PCIE_RC_CONFIG_DCSR_MPS_MASK GENMASK(7, 5) +#define PCIE_RC_CONFIG_DCSR_MPS_256 (0x1 << 5) +#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) +#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) +#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) +#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) +#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) +#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20) + +#define PCIE_CORE_AXI_CONF_BASE 0xc00000 +#define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0) +#define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f +#define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00 +#define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4) +#define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8) +#define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc) + +#define PCIE_CORE_AXI_INBOUND_BASE 0xc00800 +#define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0) +#define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f +#define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00 +#define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4) + +/* Size of one AXI Region (not Region 0) */ +#define AXI_REGION_SIZE BIT(20) +/* Size of Region 0, equal to sum of sizes of other regions */ +#define AXI_REGION_0_SIZE (32 * (0x1 << 20)) +#define OB_REG_SIZE_SHIFT 5 +#define IB_ROOT_PORT_REG_SIZE_SHIFT 3 +#define AXI_WRAPPER_IO_WRITE 0x6 +#define AXI_WRAPPER_MEM_WRITE 0x2 +#define AXI_WRAPPER_TYPE0_CFG 0xa +#define AXI_WRAPPER_TYPE1_CFG 0xb +#define AXI_WRAPPER_NOR_MSG 0xc + +#define MAX_AXI_IB_ROOTPORT_REGION_NUM 3 +#define MIN_AXI_ADDR_BITS_PASSED 8 +#define PCIE_RC_SEND_PME_OFF 0x11960 +#define ROCKCHIP_VENDOR_ID 0x1d87 +#define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20) +#define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15) +#define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12) +#define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0) +#define PCIE_ECAM_ADDR(bus, dev, func, reg) \ + (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \ + PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg)) +#define PCIE_LINK_IS_L2(x) \ + (((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2) +#define PCIE_LINK_UP(x) \ + (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP) +#define PCIE_LINK_IS_GEN2(x) \ + (((x) & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) + +#define RC_REGION_0_ADDR_TRANS_H 0x00000000 +#define RC_REGION_0_ADDR_TRANS_L 0x00000000 +#define RC_REGION_0_PASS_BITS (25 - 1) +#define RC_REGION_0_TYPE_MASK GENMASK(3, 0) +#define MAX_AXI_WRAPPER_REGION_NUM 33 + +struct rockchip_pcie { + void __iomem *reg_base; /* DT axi-base */ + void __iomem *apb_base; /* DT apb-base */ + bool legacy_phy; + struct phy *phys[MAX_LANE_NUM]; + struct reset_control *core_rst; + struct reset_control *mgmt_rst; + struct reset_control *mgmt_sticky_rst; + struct reset_control *pipe_rst; + struct reset_control *pm_rst; + struct reset_control *aclk_rst; + struct reset_control *pclk_rst; + struct clk *aclk_pcie; + struct clk *aclk_perf_pcie; + struct clk *hclk_pcie; + struct clk *clk_pcie_pm; + struct regulator *vpcie12v; /* 12V power supply */ + struct regulator *vpcie3v3; /* 3.3V power supply */ + struct regulator *vpcie1v8; /* 1.8V power supply */ + struct regulator *vpcie0v9; /* 0.9V power supply */ + struct gpio_desc *ep_gpio; + u32 lanes; + u8 lanes_map; + u8 root_bus_nr; + int link_gen; + struct device *dev; + struct irq_domain *irq_domain; + int offset; + struct pci_bus *root_bus; + struct resource *io; + phys_addr_t io_bus_addr; + u32 io_size; + void __iomem *msg_region; + u32 mem_size; + phys_addr_t msg_bus_addr; + phys_addr_t mem_bus_addr; +}; + + +static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg) +{ + return readl(rockchip->apb_base + reg); +} + +static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, + u32 reg) +{ + writel(val, rockchip->apb_base + reg); +} + +int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip); +void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip); +int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip); +void rockchip_pcie_disable_clocks(void *data); +void rockchip_pcie_cfg_configuration_accesses( + struct rockchip_pcie *rockchip, u32 type); + +#endif /* _PCIE_ROCKCHIP_H */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/6] PCI: rockchip: Split out common function to parse DT [not found] ` <1519348503-243259-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2018-02-23 1:15 ` [PATCH v2 1/6] PCI: rockchip: Create individual folder for rockchip drivers Shawn Lin @ 2018-02-23 1:16 ` Shawn Lin 2018-02-23 1:16 ` [PATCH v2 3/6] PCI: rockchip: Spilt out common function to init controller Shawn Lin ` (3 subsequent siblings) 5 siblings, 0 replies; 15+ messages in thread From: Shawn Lin @ 2018-02-23 1:16 UTC (permalink / raw) To: Bjorn Helgaas, Lorenzo Pieralisi Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA, Shawn Lin, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring Most of the DT properties are used for both of host and EP drivrs, so this patch spilt them out to new function, rockchip_pcie_parse_dt in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- Changes in v2: None drivers/pci/rockchip/pcie-rockchip-host.c | 119 ++------------------------- drivers/pci/rockchip/pcie-rockchip.c | 128 ++++++++++++++++++++++++++++++ drivers/pci/rockchip/pcie-rockchip.h | 2 + 3 files changed, 135 insertions(+), 114 deletions(-) diff --git a/drivers/pci/rockchip/pcie-rockchip-host.c b/drivers/pci/rockchip/pcie-rockchip-host.c index 563f696..079949c 100644 --- a/drivers/pci/rockchip/pcie-rockchip-host.c +++ b/drivers/pci/rockchip/pcie-rockchip-host.c @@ -703,130 +703,20 @@ static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip) } /** - * rockchip_pcie_parse_dt - Parse Device Tree + * rockchip_pcie_parse_host_dt - Parse Device Tree * @rockchip: PCIe port information * * Return: '0' on success and error value on failure */ -static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) +static int rockchip_pcie_parse_host_dt(struct rockchip_pcie *rockchip) { struct device *dev = rockchip->dev; - struct platform_device *pdev = to_platform_device(dev); - struct device_node *node = dev->of_node; - struct resource *regs; int err; - regs = platform_get_resource_byname(pdev, - IORESOURCE_MEM, - "axi-base"); - rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); - if (IS_ERR(rockchip->reg_base)) - return PTR_ERR(rockchip->reg_base); - - regs = platform_get_resource_byname(pdev, - IORESOURCE_MEM, - "apb-base"); - rockchip->apb_base = devm_ioremap_resource(dev, regs); - if (IS_ERR(rockchip->apb_base)) - return PTR_ERR(rockchip->apb_base); - - err = rockchip_pcie_get_phys(rockchip); + err = rockchip_pcie_parse_dt(rockchip); if (err) return err; - rockchip->lanes = 1; - err = of_property_read_u32(node, "num-lanes", &rockchip->lanes); - if (!err && (rockchip->lanes == 0 || - rockchip->lanes == 3 || - rockchip->lanes > 4)) { - dev_warn(dev, "invalid num-lanes, default to use one lane\n"); - rockchip->lanes = 1; - } - - rockchip->link_gen = of_pci_get_max_link_speed(node); - if (rockchip->link_gen < 0 || rockchip->link_gen > 2) - rockchip->link_gen = 2; - - rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core"); - if (IS_ERR(rockchip->core_rst)) { - if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER) - dev_err(dev, "missing core reset property in node\n"); - return PTR_ERR(rockchip->core_rst); - } - - rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt"); - if (IS_ERR(rockchip->mgmt_rst)) { - if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER) - dev_err(dev, "missing mgmt reset property in node\n"); - return PTR_ERR(rockchip->mgmt_rst); - } - - rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev, - "mgmt-sticky"); - if (IS_ERR(rockchip->mgmt_sticky_rst)) { - if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER) - dev_err(dev, "missing mgmt-sticky reset property in node\n"); - return PTR_ERR(rockchip->mgmt_sticky_rst); - } - - rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe"); - if (IS_ERR(rockchip->pipe_rst)) { - if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER) - dev_err(dev, "missing pipe reset property in node\n"); - return PTR_ERR(rockchip->pipe_rst); - } - - rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm"); - if (IS_ERR(rockchip->pm_rst)) { - if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER) - dev_err(dev, "missing pm reset property in node\n"); - return PTR_ERR(rockchip->pm_rst); - } - - rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk"); - if (IS_ERR(rockchip->pclk_rst)) { - if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER) - dev_err(dev, "missing pclk reset property in node\n"); - return PTR_ERR(rockchip->pclk_rst); - } - - rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk"); - if (IS_ERR(rockchip->aclk_rst)) { - if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER) - dev_err(dev, "missing aclk reset property in node\n"); - return PTR_ERR(rockchip->aclk_rst); - } - - rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH); - if (IS_ERR(rockchip->ep_gpio)) { - dev_err(dev, "missing ep-gpios property in node\n"); - return PTR_ERR(rockchip->ep_gpio); - } - - rockchip->aclk_pcie = devm_clk_get(dev, "aclk"); - if (IS_ERR(rockchip->aclk_pcie)) { - dev_err(dev, "aclk clock not found\n"); - return PTR_ERR(rockchip->aclk_pcie); - } - - rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf"); - if (IS_ERR(rockchip->aclk_perf_pcie)) { - dev_err(dev, "aclk_perf clock not found\n"); - return PTR_ERR(rockchip->aclk_perf_pcie); - } - - rockchip->hclk_pcie = devm_clk_get(dev, "hclk"); - if (IS_ERR(rockchip->hclk_pcie)) { - dev_err(dev, "hclk clock not found\n"); - return PTR_ERR(rockchip->hclk_pcie); - } - - rockchip->clk_pcie_pm = devm_clk_get(dev, "pm"); - if (IS_ERR(rockchip->clk_pcie_pm)) { - dev_err(dev, "pm clock not found\n"); - return PTR_ERR(rockchip->clk_pcie_pm); - } - err = rockchip_pcie_setup_irq(rockchip); if (err) return err; @@ -1193,8 +1083,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev) platform_set_drvdata(pdev, rockchip); rockchip->dev = dev; + rockchip->is_rc = true; - err = rockchip_pcie_parse_dt(rockchip); + err = rockchip_pcie_parse_host_dt(rockchip); if (err) return err; diff --git a/drivers/pci/rockchip/pcie-rockchip.c b/drivers/pci/rockchip/pcie-rockchip.c index c7614f9..6c0063d 100644 --- a/drivers/pci/rockchip/pcie-rockchip.c +++ b/drivers/pci/rockchip/pcie-rockchip.c @@ -12,10 +12,138 @@ */ #include <linux/clk.h> +#include <linux/gpio/consumer.h> +#include <linux/of_pci.h> #include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/reset.h> #include "pcie-rockchip.h" +int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) +{ + struct device *dev = rockchip->dev; + struct platform_device *pdev = to_platform_device(dev); + struct device_node *node = dev->of_node; + struct resource *regs; + int err; + + regs = platform_get_resource_byname(pdev, + IORESOURCE_MEM, + "axi-base"); + rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); + if (IS_ERR(rockchip->reg_base)) + return PTR_ERR(rockchip->reg_base); + + regs = platform_get_resource_byname(pdev, + IORESOURCE_MEM, + "apb-base"); + rockchip->apb_base = devm_ioremap_resource(dev, regs); + if (IS_ERR(rockchip->apb_base)) + return PTR_ERR(rockchip->apb_base); + + err = rockchip_pcie_get_phys(rockchip); + if (err) + return err; + + rockchip->lanes = 1; + err = of_property_read_u32(node, "num-lanes", &rockchip->lanes); + if (!err && (rockchip->lanes == 0 || + rockchip->lanes == 3 || + rockchip->lanes > 4)) { + dev_warn(dev, "invalid num-lanes, default to use one lane\n"); + rockchip->lanes = 1; + } + + rockchip->link_gen = of_pci_get_max_link_speed(node); + if (rockchip->link_gen < 0 || rockchip->link_gen > 2) + rockchip->link_gen = 2; + + rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core"); + if (IS_ERR(rockchip->core_rst)) { + if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER) + dev_err(dev, "missing core reset property in node\n"); + return PTR_ERR(rockchip->core_rst); + } + + rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt"); + if (IS_ERR(rockchip->mgmt_rst)) { + if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER) + dev_err(dev, "missing mgmt reset property in node\n"); + return PTR_ERR(rockchip->mgmt_rst); + } + + rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev, + "mgmt-sticky"); + if (IS_ERR(rockchip->mgmt_sticky_rst)) { + if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER) + dev_err(dev, "missing mgmt-sticky reset property in node\n"); + return PTR_ERR(rockchip->mgmt_sticky_rst); + } + + rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe"); + if (IS_ERR(rockchip->pipe_rst)) { + if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER) + dev_err(dev, "missing pipe reset property in node\n"); + return PTR_ERR(rockchip->pipe_rst); + } + + rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm"); + if (IS_ERR(rockchip->pm_rst)) { + if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER) + dev_err(dev, "missing pm reset property in node\n"); + return PTR_ERR(rockchip->pm_rst); + } + + rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk"); + if (IS_ERR(rockchip->pclk_rst)) { + if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER) + dev_err(dev, "missing pclk reset property in node\n"); + return PTR_ERR(rockchip->pclk_rst); + } + + rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk"); + if (IS_ERR(rockchip->aclk_rst)) { + if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER) + dev_err(dev, "missing aclk reset property in node\n"); + return PTR_ERR(rockchip->aclk_rst); + } + + if (rockchip->is_rc) { + rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH); + if (IS_ERR(rockchip->ep_gpio)) { + dev_err(dev, "missing ep-gpios property in node\n"); + return PTR_ERR(rockchip->ep_gpio); + } + } + + rockchip->aclk_pcie = devm_clk_get(dev, "aclk"); + if (IS_ERR(rockchip->aclk_pcie)) { + dev_err(dev, "aclk clock not found\n"); + return PTR_ERR(rockchip->aclk_pcie); + } + + rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf"); + if (IS_ERR(rockchip->aclk_perf_pcie)) { + dev_err(dev, "aclk_perf clock not found\n"); + return PTR_ERR(rockchip->aclk_perf_pcie); + } + + rockchip->hclk_pcie = devm_clk_get(dev, "hclk"); + if (IS_ERR(rockchip->hclk_pcie)) { + dev_err(dev, "hclk clock not found\n"); + return PTR_ERR(rockchip->hclk_pcie); + } + + rockchip->clk_pcie_pm = devm_clk_get(dev, "pm"); + if (IS_ERR(rockchip->clk_pcie_pm)) { + dev_err(dev, "pm clock not found\n"); + return PTR_ERR(rockchip->clk_pcie_pm); + } + + return 0; +} + int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip) { struct device *dev = rockchip->dev; diff --git a/drivers/pci/rockchip/pcie-rockchip.h b/drivers/pci/rockchip/pcie-rockchip.h index 9e0cf2e..c0f84d9 100644 --- a/drivers/pci/rockchip/pcie-rockchip.h +++ b/drivers/pci/rockchip/pcie-rockchip.h @@ -222,6 +222,7 @@ struct rockchip_pcie { u32 mem_size; phys_addr_t msg_bus_addr; phys_addr_t mem_bus_addr; + bool is_rc; }; @@ -236,6 +237,7 @@ static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, writel(val, rockchip->apb_base + reg); } +int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip); int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip); void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip); int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip); -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 3/6] PCI: rockchip: Spilt out common function to init controller [not found] ` <1519348503-243259-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2018-02-23 1:15 ` [PATCH v2 1/6] PCI: rockchip: Create individual folder for rockchip drivers Shawn Lin 2018-02-23 1:16 ` [PATCH v2 2/6] PCI: rockchip: Split out common function to parse DT Shawn Lin @ 2018-02-23 1:16 ` Shawn Lin [not found] ` <1519348606-243485-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2018-02-23 1:17 ` [PATCH v2 4/6] dt-bindings: PCI: rockchip: Rename rockchip-pcie.txt to rockchip-pcie-host.txt Shawn Lin ` (2 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Shawn Lin @ 2018-02-23 1:16 UTC (permalink / raw) To: Bjorn Helgaas, Lorenzo Pieralisi Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA, Shawn Lin, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring Most of the operations are used for both of host and EP driver, so this patch spilt them out to a new function, rockchip_pcie_init_port in pcie-rockchip.c and rename the original function to rockchip_pcie_host_init_port to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- Changes in v2: None drivers/pci/rockchip/pcie-rockchip-host.c | 131 ++------------------------- drivers/pci/rockchip/pcie-rockchip.c | 141 ++++++++++++++++++++++++++++++ drivers/pci/rockchip/pcie-rockchip.h | 3 + 3 files changed, 151 insertions(+), 124 deletions(-) diff --git a/drivers/pci/rockchip/pcie-rockchip-host.c b/drivers/pci/rockchip/pcie-rockchip-host.c index 079949c..f5b0492 100644 --- a/drivers/pci/rockchip/pcie-rockchip-host.c +++ b/drivers/pci/rockchip/pcie-rockchip-host.c @@ -294,134 +294,17 @@ static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip) * rockchip_pcie_init_port - Initialize hardware * @rockchip: PCIe port information */ -static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) +static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) { struct device *dev = rockchip->dev; - int err, i; + int err, i = MAX_LANE_NUM; u32 status; gpiod_set_value_cansleep(rockchip->ep_gpio, 0); - err = reset_control_assert(rockchip->aclk_rst); - if (err) { - dev_err(dev, "assert aclk_rst err %d\n", err); - return err; - } - - err = reset_control_assert(rockchip->pclk_rst); - if (err) { - dev_err(dev, "assert pclk_rst err %d\n", err); - return err; - } - - err = reset_control_assert(rockchip->pm_rst); - if (err) { - dev_err(dev, "assert pm_rst err %d\n", err); + err = rockchip_pcie_init_port(rockchip); + if (err) return err; - } - - for (i = 0; i < MAX_LANE_NUM; i++) { - err = phy_init(rockchip->phys[i]); - if (err) { - dev_err(dev, "init phy%d err %d\n", i, err); - goto err_exit_phy; - } - } - - err = reset_control_assert(rockchip->core_rst); - if (err) { - dev_err(dev, "assert core_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_assert(rockchip->mgmt_rst); - if (err) { - dev_err(dev, "assert mgmt_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_assert(rockchip->mgmt_sticky_rst); - if (err) { - dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_assert(rockchip->pipe_rst); - if (err) { - dev_err(dev, "assert pipe_rst err %d\n", err); - goto err_exit_phy; - } - - udelay(10); - - err = reset_control_deassert(rockchip->pm_rst); - if (err) { - dev_err(dev, "deassert pm_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_deassert(rockchip->aclk_rst); - if (err) { - dev_err(dev, "deassert aclk_rst err %d\n", err); - goto err_exit_phy; - } - - err = reset_control_deassert(rockchip->pclk_rst); - if (err) { - dev_err(dev, "deassert pclk_rst err %d\n", err); - goto err_exit_phy; - } - - if (rockchip->link_gen == 2) - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, - PCIE_CLIENT_CONFIG); - else - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, - PCIE_CLIENT_CONFIG); - - rockchip_pcie_write(rockchip, - PCIE_CLIENT_CONF_ENABLE | - PCIE_CLIENT_LINK_TRAIN_ENABLE | - PCIE_CLIENT_ARI_ENABLE | - PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) | - PCIE_CLIENT_MODE_RC, - PCIE_CLIENT_CONFIG); - - for (i = 0; i < MAX_LANE_NUM; i++) { - err = phy_power_on(rockchip->phys[i]); - if (err) { - dev_err(dev, "power on phy%d err %d\n", i, err); - goto err_power_off_phy; - } - } - - /* - * Please don't reorder the deassert sequence of the following - * four reset pins. - */ - err = reset_control_deassert(rockchip->mgmt_sticky_rst); - if (err) { - dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); - goto err_power_off_phy; - } - - err = reset_control_deassert(rockchip->core_rst); - if (err) { - dev_err(dev, "deassert core_rst err %d\n", err); - goto err_power_off_phy; - } - - err = reset_control_deassert(rockchip->mgmt_rst); - if (err) { - dev_err(dev, "deassert mgmt_rst err %d\n", err); - goto err_power_off_phy; - } - - err = reset_control_deassert(rockchip->pipe_rst); - if (err) { - dev_err(dev, "deassert pipe_rst err %d\n", err); - goto err_power_off_phy; - } /* Fix the transmitted FTS count desired to exit from L0s. */ status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1); @@ -514,8 +397,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) err_power_off_phy: while (i--) phy_power_off(rockchip->phys[i]); + i = MAX_LANE_NUM; -err_exit_phy: while (i--) phy_exit(rockchip->phys[i]); return err; @@ -1034,7 +917,7 @@ static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev) if (err) goto err_disable_0v9; - err = rockchip_pcie_init_port(rockchip); + err = rockchip_pcie_host_init_port(rockchip); if (err) goto err_pcie_resume; @@ -1099,7 +982,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev) goto err_set_vpcie; } - err = rockchip_pcie_init_port(rockchip); + err = rockchip_pcie_host_init_port(rockchip); if (err) goto err_vpcie; diff --git a/drivers/pci/rockchip/pcie-rockchip.c b/drivers/pci/rockchip/pcie-rockchip.c index 6c0063d..d03508c 100644 --- a/drivers/pci/rockchip/pcie-rockchip.c +++ b/drivers/pci/rockchip/pcie-rockchip.c @@ -12,6 +12,7 @@ */ #include <linux/clk.h> +#include <linux/delay.h> #include <linux/gpio/consumer.h> #include <linux/of_pci.h> #include <linux/phy/phy.h> @@ -144,6 +145,146 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) return 0; } +int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) +{ + struct device *dev = rockchip->dev; + int err, i; + u32 regs; + + err = reset_control_assert(rockchip->aclk_rst); + if (err) { + dev_err(dev, "assert aclk_rst err %d\n", err); + return err; + } + + err = reset_control_assert(rockchip->pclk_rst); + if (err) { + dev_err(dev, "assert pclk_rst err %d\n", err); + return err; + } + + err = reset_control_assert(rockchip->pm_rst); + if (err) { + dev_err(dev, "assert pm_rst err %d\n", err); + return err; + } + + for (i = 0; i < MAX_LANE_NUM; i++) { + err = phy_init(rockchip->phys[i]); + if (err) { + dev_err(dev, "init phy%d err %d\n", i, err); + goto err_exit_phy; + } + } + + err = reset_control_assert(rockchip->core_rst); + if (err) { + dev_err(dev, "assert core_rst err %d\n", err); + goto err_exit_phy; + } + + err = reset_control_assert(rockchip->mgmt_rst); + if (err) { + dev_err(dev, "assert mgmt_rst err %d\n", err); + goto err_exit_phy; + } + + err = reset_control_assert(rockchip->mgmt_sticky_rst); + if (err) { + dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); + goto err_exit_phy; + } + + err = reset_control_assert(rockchip->pipe_rst); + if (err) { + dev_err(dev, "assert pipe_rst err %d\n", err); + goto err_exit_phy; + } + + udelay(10); + + err = reset_control_deassert(rockchip->pm_rst); + if (err) { + dev_err(dev, "deassert pm_rst err %d\n", err); + goto err_exit_phy; + } + + err = reset_control_deassert(rockchip->aclk_rst); + if (err) { + dev_err(dev, "deassert aclk_rst err %d\n", err); + goto err_exit_phy; + } + + err = reset_control_deassert(rockchip->pclk_rst); + if (err) { + dev_err(dev, "deassert pclk_rst err %d\n", err); + goto err_exit_phy; + } + + if (rockchip->link_gen == 2) + rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, + PCIE_CLIENT_CONFIG); + else + rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, + PCIE_CLIENT_CONFIG); + + regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE | + PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); + + if (rockchip->is_rc) + regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; + else + regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP; + + rockchip_pcie_write(rockchip, regs, PCIE_CLIENT_CONFIG); + + for (i = 0; i < MAX_LANE_NUM; i++) { + err = phy_power_on(rockchip->phys[i]); + if (err) { + dev_err(dev, "power on phy%d err %d\n", i, err); + goto err_power_off_phy; + } + } + + /* + * Please don't reorder the deassert sequence of the following + * four reset pins. + */ + err = reset_control_deassert(rockchip->mgmt_sticky_rst); + if (err) { + dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); + goto err_power_off_phy; + } + + err = reset_control_deassert(rockchip->core_rst); + if (err) { + dev_err(dev, "deassert core_rst err %d\n", err); + goto err_power_off_phy; + } + + err = reset_control_deassert(rockchip->mgmt_rst); + if (err) { + dev_err(dev, "deassert mgmt_rst err %d\n", err); + goto err_power_off_phy; + } + + err = reset_control_deassert(rockchip->pipe_rst); + if (err) { + dev_err(dev, "deassert pipe_rst err %d\n", err); + goto err_power_off_phy; + } + + return 0; +err_power_off_phy: + while (i--) + phy_power_off(rockchip->phys[i]); + i = MAX_LANE_NUM; +err_exit_phy: + while (i--) + phy_exit(rockchip->phys[i]); + return err; +} + int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip) { struct device *dev = rockchip->dev; diff --git a/drivers/pci/rockchip/pcie-rockchip.h b/drivers/pci/rockchip/pcie-rockchip.h index c0f84d9..af3e74f 100644 --- a/drivers/pci/rockchip/pcie-rockchip.h +++ b/drivers/pci/rockchip/pcie-rockchip.h @@ -27,10 +27,12 @@ #define PCIE_CLIENT_BASE 0x0 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001) +#define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0) #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002) #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008) #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x)) #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) +#define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) @@ -238,6 +240,7 @@ static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, } int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip); +int rockchip_pcie_init_port(struct rockchip_pcie *rockchip); int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip); void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip); int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip); -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
[parent not found: <1519348606-243485-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* Re: [v2, 3/6] PCI: rockchip: Spilt out common function to init controller [not found] ` <1519348606-243485-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> @ 2018-02-25 0:51 ` JeffyChen 2018-02-27 11:29 ` [PATCH v2 " Lorenzo Pieralisi 1 sibling, 0 replies; 15+ messages in thread From: JeffyChen @ 2018-02-25 0:51 UTC (permalink / raw) To: Shawn Lin, Bjorn Helgaas, Lorenzo Pieralisi Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA Hi Shawn, tested on my chromebook kevin, with this series and enable CONFIG_PCIE_ROCKCHIP_HOST, the pcie wifi(mrvl 8997) still works. so, for the pcie host driver part: Tested-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> On 02/23/2018 09:16 AM, Shawn Lin wrote: > Most of the operations are used for both of host and EP driver, > so this patch spilt them out to a new function, rockchip_pcie_init_port > in pcie-rockchip.c and rename the original function to > rockchip_pcie_host_init_port to avoid confusion. No functional > changed intended. > > Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > --- > > Changes in v2: None > > drivers/pci/rockchip/pcie-rockchip-host.c | 131 ++------------------------- > drivers/pci/rockchip/pcie-rockchip.c | 141 ++++++++++++++++++++++++++++++ > drivers/pci/rockchip/pcie-rockchip.h | 3 + > 3 files changed, 151 insertions(+), 124 deletions(-) > > diff --git a/drivers/pci/rockchip/pcie-rockchip-host.c b/drivers/pci/rockchip/pcie-rockchip-host.c > index 079949c..f5b0492 100644 > --- a/drivers/pci/rockchip/pcie-rockchip-host.c > +++ b/drivers/pci/rockchip/pcie-rockchip-host.c > @@ -294,134 +294,17 @@ static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip) > * rockchip_pcie_init_port - Initialize hardware > * @rockchip: PCIe port information > */ > -static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > +static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) > { > struct device *dev = rockchip->dev; > - int err, i; > + int err, i = MAX_LANE_NUM; > u32 status; > > gpiod_set_value_cansleep(rockchip->ep_gpio, 0); > > - err = reset_control_assert(rockchip->aclk_rst); > - if (err) { > - dev_err(dev, "assert aclk_rst err %d\n", err); > - return err; > - } > - > - err = reset_control_assert(rockchip->pclk_rst); > - if (err) { > - dev_err(dev, "assert pclk_rst err %d\n", err); > - return err; > - } > - > - err = reset_control_assert(rockchip->pm_rst); > - if (err) { > - dev_err(dev, "assert pm_rst err %d\n", err); > + err = rockchip_pcie_init_port(rockchip); > + if (err) > return err; > - } > - > - for (i = 0; i < MAX_LANE_NUM; i++) { > - err = phy_init(rockchip->phys[i]); > - if (err) { > - dev_err(dev, "init phy%d err %d\n", i, err); > - goto err_exit_phy; > - } > - } > - > - err = reset_control_assert(rockchip->core_rst); > - if (err) { > - dev_err(dev, "assert core_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_assert(rockchip->mgmt_rst); > - if (err) { > - dev_err(dev, "assert mgmt_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_assert(rockchip->mgmt_sticky_rst); > - if (err) { > - dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_assert(rockchip->pipe_rst); > - if (err) { > - dev_err(dev, "assert pipe_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - udelay(10); > - > - err = reset_control_deassert(rockchip->pm_rst); > - if (err) { > - dev_err(dev, "deassert pm_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_deassert(rockchip->aclk_rst); > - if (err) { > - dev_err(dev, "deassert aclk_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_deassert(rockchip->pclk_rst); > - if (err) { > - dev_err(dev, "deassert pclk_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - if (rockchip->link_gen == 2) > - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, > - PCIE_CLIENT_CONFIG); > - else > - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, > - PCIE_CLIENT_CONFIG); > - > - rockchip_pcie_write(rockchip, > - PCIE_CLIENT_CONF_ENABLE | > - PCIE_CLIENT_LINK_TRAIN_ENABLE | > - PCIE_CLIENT_ARI_ENABLE | > - PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) | > - PCIE_CLIENT_MODE_RC, > - PCIE_CLIENT_CONFIG); > - > - for (i = 0; i < MAX_LANE_NUM; i++) { > - err = phy_power_on(rockchip->phys[i]); > - if (err) { > - dev_err(dev, "power on phy%d err %d\n", i, err); > - goto err_power_off_phy; > - } > - } > - > - /* > - * Please don't reorder the deassert sequence of the following > - * four reset pins. > - */ > - err = reset_control_deassert(rockchip->mgmt_sticky_rst); > - if (err) { > - dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); > - goto err_power_off_phy; > - } > - > - err = reset_control_deassert(rockchip->core_rst); > - if (err) { > - dev_err(dev, "deassert core_rst err %d\n", err); > - goto err_power_off_phy; > - } > - > - err = reset_control_deassert(rockchip->mgmt_rst); > - if (err) { > - dev_err(dev, "deassert mgmt_rst err %d\n", err); > - goto err_power_off_phy; > - } > - > - err = reset_control_deassert(rockchip->pipe_rst); > - if (err) { > - dev_err(dev, "deassert pipe_rst err %d\n", err); > - goto err_power_off_phy; > - } > > /* Fix the transmitted FTS count desired to exit from L0s. */ > status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1); > @@ -514,8 +397,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > err_power_off_phy: > while (i--) > phy_power_off(rockchip->phys[i]); > + > i = MAX_LANE_NUM; > -err_exit_phy: > while (i--) > phy_exit(rockchip->phys[i]); > return err; > @@ -1034,7 +917,7 @@ static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev) > if (err) > goto err_disable_0v9; > > - err = rockchip_pcie_init_port(rockchip); > + err = rockchip_pcie_host_init_port(rockchip); > if (err) > goto err_pcie_resume; > > @@ -1099,7 +982,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev) > goto err_set_vpcie; > } > > - err = rockchip_pcie_init_port(rockchip); > + err = rockchip_pcie_host_init_port(rockchip); > if (err) > goto err_vpcie; > > diff --git a/drivers/pci/rockchip/pcie-rockchip.c b/drivers/pci/rockchip/pcie-rockchip.c > index 6c0063d..d03508c 100644 > --- a/drivers/pci/rockchip/pcie-rockchip.c > +++ b/drivers/pci/rockchip/pcie-rockchip.c > @@ -12,6 +12,7 @@ > */ > > #include <linux/clk.h> > +#include <linux/delay.h> > #include <linux/gpio/consumer.h> > #include <linux/of_pci.h> > #include <linux/phy/phy.h> > @@ -144,6 +145,146 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) > return 0; > } > > +int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > +{ > + struct device *dev = rockchip->dev; > + int err, i; > + u32 regs; > + > + err = reset_control_assert(rockchip->aclk_rst); > + if (err) { > + dev_err(dev, "assert aclk_rst err %d\n", err); > + return err; > + } > + > + err = reset_control_assert(rockchip->pclk_rst); > + if (err) { > + dev_err(dev, "assert pclk_rst err %d\n", err); > + return err; > + } > + > + err = reset_control_assert(rockchip->pm_rst); > + if (err) { > + dev_err(dev, "assert pm_rst err %d\n", err); > + return err; > + } > + > + for (i = 0; i < MAX_LANE_NUM; i++) { > + err = phy_init(rockchip->phys[i]); > + if (err) { > + dev_err(dev, "init phy%d err %d\n", i, err); > + goto err_exit_phy; > + } > + } > + > + err = reset_control_assert(rockchip->core_rst); > + if (err) { > + dev_err(dev, "assert core_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + err = reset_control_assert(rockchip->mgmt_rst); > + if (err) { > + dev_err(dev, "assert mgmt_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + err = reset_control_assert(rockchip->mgmt_sticky_rst); > + if (err) { > + dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + err = reset_control_assert(rockchip->pipe_rst); > + if (err) { > + dev_err(dev, "assert pipe_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + udelay(10); > + > + err = reset_control_deassert(rockchip->pm_rst); > + if (err) { > + dev_err(dev, "deassert pm_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + err = reset_control_deassert(rockchip->aclk_rst); > + if (err) { > + dev_err(dev, "deassert aclk_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + err = reset_control_deassert(rockchip->pclk_rst); > + if (err) { > + dev_err(dev, "deassert pclk_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + if (rockchip->link_gen == 2) > + rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, > + PCIE_CLIENT_CONFIG); > + else > + rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, > + PCIE_CLIENT_CONFIG); > + > + regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE | > + PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); > + > + if (rockchip->is_rc) > + regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; > + else > + regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP; > + > + rockchip_pcie_write(rockchip, regs, PCIE_CLIENT_CONFIG); > + > + for (i = 0; i < MAX_LANE_NUM; i++) { > + err = phy_power_on(rockchip->phys[i]); > + if (err) { > + dev_err(dev, "power on phy%d err %d\n", i, err); > + goto err_power_off_phy; > + } > + } > + > + /* > + * Please don't reorder the deassert sequence of the following > + * four reset pins. > + */ > + err = reset_control_deassert(rockchip->mgmt_sticky_rst); > + if (err) { > + dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); > + goto err_power_off_phy; > + } > + > + err = reset_control_deassert(rockchip->core_rst); > + if (err) { > + dev_err(dev, "deassert core_rst err %d\n", err); > + goto err_power_off_phy; > + } > + > + err = reset_control_deassert(rockchip->mgmt_rst); > + if (err) { > + dev_err(dev, "deassert mgmt_rst err %d\n", err); > + goto err_power_off_phy; > + } > + > + err = reset_control_deassert(rockchip->pipe_rst); > + if (err) { > + dev_err(dev, "deassert pipe_rst err %d\n", err); > + goto err_power_off_phy; > + } > + > + return 0; > +err_power_off_phy: > + while (i--) > + phy_power_off(rockchip->phys[i]); > + i = MAX_LANE_NUM; > +err_exit_phy: > + while (i--) > + phy_exit(rockchip->phys[i]); > + return err; > +} > + > int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip) > { > struct device *dev = rockchip->dev; > diff --git a/drivers/pci/rockchip/pcie-rockchip.h b/drivers/pci/rockchip/pcie-rockchip.h > index c0f84d9..af3e74f 100644 > --- a/drivers/pci/rockchip/pcie-rockchip.h > +++ b/drivers/pci/rockchip/pcie-rockchip.h > @@ -27,10 +27,12 @@ > #define PCIE_CLIENT_BASE 0x0 > #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) > #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001) > +#define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0) > #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002) > #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008) > #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x)) > #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) > +#define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) > #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) > #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) > #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) > @@ -238,6 +240,7 @@ static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, > } > > int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip); > +int rockchip_pcie_init_port(struct rockchip_pcie *rockchip); > int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip); > void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip); > int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip); > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/6] PCI: rockchip: Spilt out common function to init controller [not found] ` <1519348606-243485-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2018-02-25 0:51 ` [v2, " JeffyChen @ 2018-02-27 11:29 ` Lorenzo Pieralisi 1 sibling, 0 replies; 15+ messages in thread From: Lorenzo Pieralisi @ 2018-02-27 11:29 UTC (permalink / raw) To: Shawn Lin Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring, Bjorn Helgaas On Fri, Feb 23, 2018 at 09:16:46AM +0800, Shawn Lin wrote: > Most of the operations are used for both of host and EP driver, > so this patch spilt them out to a new function, rockchip_pcie_init_port Here and in the $SUBJECT s/spilt/split I will update it myself if there is no v3 required (but I have some minor comments on patch 5 so I suspect it will be required). Lorenzo > in pcie-rockchip.c and rename the original function to > rockchip_pcie_host_init_port to avoid confusion. No functional > changed intended. > > Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > --- > > Changes in v2: None > > drivers/pci/rockchip/pcie-rockchip-host.c | 131 ++------------------------- > drivers/pci/rockchip/pcie-rockchip.c | 141 ++++++++++++++++++++++++++++++ > drivers/pci/rockchip/pcie-rockchip.h | 3 + > 3 files changed, 151 insertions(+), 124 deletions(-) > > diff --git a/drivers/pci/rockchip/pcie-rockchip-host.c b/drivers/pci/rockchip/pcie-rockchip-host.c > index 079949c..f5b0492 100644 > --- a/drivers/pci/rockchip/pcie-rockchip-host.c > +++ b/drivers/pci/rockchip/pcie-rockchip-host.c > @@ -294,134 +294,17 @@ static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip) > * rockchip_pcie_init_port - Initialize hardware > * @rockchip: PCIe port information > */ > -static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > +static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) > { > struct device *dev = rockchip->dev; > - int err, i; > + int err, i = MAX_LANE_NUM; > u32 status; > > gpiod_set_value_cansleep(rockchip->ep_gpio, 0); > > - err = reset_control_assert(rockchip->aclk_rst); > - if (err) { > - dev_err(dev, "assert aclk_rst err %d\n", err); > - return err; > - } > - > - err = reset_control_assert(rockchip->pclk_rst); > - if (err) { > - dev_err(dev, "assert pclk_rst err %d\n", err); > - return err; > - } > - > - err = reset_control_assert(rockchip->pm_rst); > - if (err) { > - dev_err(dev, "assert pm_rst err %d\n", err); > + err = rockchip_pcie_init_port(rockchip); > + if (err) > return err; > - } > - > - for (i = 0; i < MAX_LANE_NUM; i++) { > - err = phy_init(rockchip->phys[i]); > - if (err) { > - dev_err(dev, "init phy%d err %d\n", i, err); > - goto err_exit_phy; > - } > - } > - > - err = reset_control_assert(rockchip->core_rst); > - if (err) { > - dev_err(dev, "assert core_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_assert(rockchip->mgmt_rst); > - if (err) { > - dev_err(dev, "assert mgmt_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_assert(rockchip->mgmt_sticky_rst); > - if (err) { > - dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_assert(rockchip->pipe_rst); > - if (err) { > - dev_err(dev, "assert pipe_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - udelay(10); > - > - err = reset_control_deassert(rockchip->pm_rst); > - if (err) { > - dev_err(dev, "deassert pm_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_deassert(rockchip->aclk_rst); > - if (err) { > - dev_err(dev, "deassert aclk_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_deassert(rockchip->pclk_rst); > - if (err) { > - dev_err(dev, "deassert pclk_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - if (rockchip->link_gen == 2) > - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, > - PCIE_CLIENT_CONFIG); > - else > - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, > - PCIE_CLIENT_CONFIG); > - > - rockchip_pcie_write(rockchip, > - PCIE_CLIENT_CONF_ENABLE | > - PCIE_CLIENT_LINK_TRAIN_ENABLE | > - PCIE_CLIENT_ARI_ENABLE | > - PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) | > - PCIE_CLIENT_MODE_RC, > - PCIE_CLIENT_CONFIG); > - > - for (i = 0; i < MAX_LANE_NUM; i++) { > - err = phy_power_on(rockchip->phys[i]); > - if (err) { > - dev_err(dev, "power on phy%d err %d\n", i, err); > - goto err_power_off_phy; > - } > - } > - > - /* > - * Please don't reorder the deassert sequence of the following > - * four reset pins. > - */ > - err = reset_control_deassert(rockchip->mgmt_sticky_rst); > - if (err) { > - dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); > - goto err_power_off_phy; > - } > - > - err = reset_control_deassert(rockchip->core_rst); > - if (err) { > - dev_err(dev, "deassert core_rst err %d\n", err); > - goto err_power_off_phy; > - } > - > - err = reset_control_deassert(rockchip->mgmt_rst); > - if (err) { > - dev_err(dev, "deassert mgmt_rst err %d\n", err); > - goto err_power_off_phy; > - } > - > - err = reset_control_deassert(rockchip->pipe_rst); > - if (err) { > - dev_err(dev, "deassert pipe_rst err %d\n", err); > - goto err_power_off_phy; > - } > > /* Fix the transmitted FTS count desired to exit from L0s. */ > status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1); > @@ -514,8 +397,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > err_power_off_phy: > while (i--) > phy_power_off(rockchip->phys[i]); > + > i = MAX_LANE_NUM; > -err_exit_phy: > while (i--) > phy_exit(rockchip->phys[i]); > return err; > @@ -1034,7 +917,7 @@ static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev) > if (err) > goto err_disable_0v9; > > - err = rockchip_pcie_init_port(rockchip); > + err = rockchip_pcie_host_init_port(rockchip); > if (err) > goto err_pcie_resume; > > @@ -1099,7 +982,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev) > goto err_set_vpcie; > } > > - err = rockchip_pcie_init_port(rockchip); > + err = rockchip_pcie_host_init_port(rockchip); > if (err) > goto err_vpcie; > > diff --git a/drivers/pci/rockchip/pcie-rockchip.c b/drivers/pci/rockchip/pcie-rockchip.c > index 6c0063d..d03508c 100644 > --- a/drivers/pci/rockchip/pcie-rockchip.c > +++ b/drivers/pci/rockchip/pcie-rockchip.c > @@ -12,6 +12,7 @@ > */ > > #include <linux/clk.h> > +#include <linux/delay.h> > #include <linux/gpio/consumer.h> > #include <linux/of_pci.h> > #include <linux/phy/phy.h> > @@ -144,6 +145,146 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) > return 0; > } > > +int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > +{ > + struct device *dev = rockchip->dev; > + int err, i; > + u32 regs; > + > + err = reset_control_assert(rockchip->aclk_rst); > + if (err) { > + dev_err(dev, "assert aclk_rst err %d\n", err); > + return err; > + } > + > + err = reset_control_assert(rockchip->pclk_rst); > + if (err) { > + dev_err(dev, "assert pclk_rst err %d\n", err); > + return err; > + } > + > + err = reset_control_assert(rockchip->pm_rst); > + if (err) { > + dev_err(dev, "assert pm_rst err %d\n", err); > + return err; > + } > + > + for (i = 0; i < MAX_LANE_NUM; i++) { > + err = phy_init(rockchip->phys[i]); > + if (err) { > + dev_err(dev, "init phy%d err %d\n", i, err); > + goto err_exit_phy; > + } > + } > + > + err = reset_control_assert(rockchip->core_rst); > + if (err) { > + dev_err(dev, "assert core_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + err = reset_control_assert(rockchip->mgmt_rst); > + if (err) { > + dev_err(dev, "assert mgmt_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + err = reset_control_assert(rockchip->mgmt_sticky_rst); > + if (err) { > + dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + err = reset_control_assert(rockchip->pipe_rst); > + if (err) { > + dev_err(dev, "assert pipe_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + udelay(10); > + > + err = reset_control_deassert(rockchip->pm_rst); > + if (err) { > + dev_err(dev, "deassert pm_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + err = reset_control_deassert(rockchip->aclk_rst); > + if (err) { > + dev_err(dev, "deassert aclk_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + err = reset_control_deassert(rockchip->pclk_rst); > + if (err) { > + dev_err(dev, "deassert pclk_rst err %d\n", err); > + goto err_exit_phy; > + } > + > + if (rockchip->link_gen == 2) > + rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, > + PCIE_CLIENT_CONFIG); > + else > + rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, > + PCIE_CLIENT_CONFIG); > + > + regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE | > + PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); > + > + if (rockchip->is_rc) > + regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; > + else > + regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP; > + > + rockchip_pcie_write(rockchip, regs, PCIE_CLIENT_CONFIG); > + > + for (i = 0; i < MAX_LANE_NUM; i++) { > + err = phy_power_on(rockchip->phys[i]); > + if (err) { > + dev_err(dev, "power on phy%d err %d\n", i, err); > + goto err_power_off_phy; > + } > + } > + > + /* > + * Please don't reorder the deassert sequence of the following > + * four reset pins. > + */ > + err = reset_control_deassert(rockchip->mgmt_sticky_rst); > + if (err) { > + dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); > + goto err_power_off_phy; > + } > + > + err = reset_control_deassert(rockchip->core_rst); > + if (err) { > + dev_err(dev, "deassert core_rst err %d\n", err); > + goto err_power_off_phy; > + } > + > + err = reset_control_deassert(rockchip->mgmt_rst); > + if (err) { > + dev_err(dev, "deassert mgmt_rst err %d\n", err); > + goto err_power_off_phy; > + } > + > + err = reset_control_deassert(rockchip->pipe_rst); > + if (err) { > + dev_err(dev, "deassert pipe_rst err %d\n", err); > + goto err_power_off_phy; > + } > + > + return 0; > +err_power_off_phy: > + while (i--) > + phy_power_off(rockchip->phys[i]); > + i = MAX_LANE_NUM; > +err_exit_phy: > + while (i--) > + phy_exit(rockchip->phys[i]); > + return err; > +} > + > int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip) > { > struct device *dev = rockchip->dev; > diff --git a/drivers/pci/rockchip/pcie-rockchip.h b/drivers/pci/rockchip/pcie-rockchip.h > index c0f84d9..af3e74f 100644 > --- a/drivers/pci/rockchip/pcie-rockchip.h > +++ b/drivers/pci/rockchip/pcie-rockchip.h > @@ -27,10 +27,12 @@ > #define PCIE_CLIENT_BASE 0x0 > #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) > #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001) > +#define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0) > #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002) > #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008) > #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x)) > #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) > +#define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) > #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) > #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) > #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) > @@ -238,6 +240,7 @@ static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, > } > > int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip); > +int rockchip_pcie_init_port(struct rockchip_pcie *rockchip); > int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip); > void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip); > int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip); > -- > 1.9.1 > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 4/6] dt-bindings: PCI: rockchip: Rename rockchip-pcie.txt to rockchip-pcie-host.txt [not found] ` <1519348503-243259-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> ` (2 preceding siblings ...) 2018-02-23 1:16 ` [PATCH v2 3/6] PCI: rockchip: Spilt out common function to init controller Shawn Lin @ 2018-02-23 1:17 ` Shawn Lin [not found] ` <1519348623-243549-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2018-02-23 1:17 ` [PATCH v2 5/6] PCI: rockchip: Add Endpoint controller driver for Rockchip PCIe controller Shawn Lin 2018-02-23 1:17 ` [PATCH v2 6/6] dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe endpoint controller Shawn Lin 5 siblings, 1 reply; 15+ messages in thread From: Shawn Lin @ 2018-02-23 1:17 UTC (permalink / raw) To: Bjorn Helgaas, Lorenzo Pieralisi Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA, Shawn Lin, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring Just make it more obvious that this documentation is referenced for adding Rockchip PCIe controller as root complex mode. Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- Changes in v2: - remove rockchip,rk3399-pcie-host compatible(Suggested by Rob) .../devicetree/bindings/pci/{rockchip-pcie.txt => rockchip-pcie-host.txt} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Documentation/devicetree/bindings/pci/{rockchip-pcie.txt => rockchip-pcie-host.txt} (100%) diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt similarity index 100% rename from Documentation/devicetree/bindings/pci/rockchip-pcie.txt rename to Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt -- 1.9.1 ^ permalink raw reply [flat|nested] 15+ messages in thread
[parent not found: <1519348623-243549-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* Re: [PATCH v2 4/6] dt-bindings: PCI: rockchip: Rename rockchip-pcie.txt to rockchip-pcie-host.txt [not found] ` <1519348623-243549-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> @ 2018-03-02 15:10 ` Rob Herring 0 siblings, 0 replies; 15+ messages in thread From: Rob Herring @ 2018-03-02 15:10 UTC (permalink / raw) To: Shawn Lin Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Lorenzo Pieralisi, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Bjorn Helgaas On Fri, Feb 23, 2018 at 09:17:03AM +0800, Shawn Lin wrote: > Just make it more obvious that this documentation is referenced for > adding Rockchip PCIe controller as root complex mode. > > Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > > --- > > Changes in v2: > - remove rockchip,rk3399-pcie-host compatible(Suggested by Rob) > > .../devicetree/bindings/pci/{rockchip-pcie.txt => rockchip-pcie-host.txt} | 0 > 1 file changed, 0 insertions(+), 0 deletions(-) > rename Documentation/devicetree/bindings/pci/{rockchip-pcie.txt => rockchip-pcie-host.txt} (100%) Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 5/6] PCI: rockchip: Add Endpoint controller driver for Rockchip PCIe controller [not found] ` <1519348503-243259-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> ` (3 preceding siblings ...) 2018-02-23 1:17 ` [PATCH v2 4/6] dt-bindings: PCI: rockchip: Rename rockchip-pcie.txt to rockchip-pcie-host.txt Shawn Lin @ 2018-02-23 1:17 ` Shawn Lin [not found] ` <1519348654-243597-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2018-02-23 1:17 ` [PATCH v2 6/6] dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe endpoint controller Shawn Lin 5 siblings, 1 reply; 15+ messages in thread From: Shawn Lin @ 2018-02-23 1:17 UTC (permalink / raw) To: Bjorn Helgaas, Lorenzo Pieralisi Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA, Shawn Lin, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring This patch adds support to the Rockchip PCIe controller in endpoint mode which currently supports up to 32 regions, and each regions should at least be 1MB per TRM. Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- Changes in v2: - fix some error handling drivers/pci/rockchip/Kconfig | 12 + drivers/pci/rockchip/Makefile | 1 + drivers/pci/rockchip/pcie-rockchip-ep.c | 641 ++++++++++++++++++++++++++++++++ drivers/pci/rockchip/pcie-rockchip.c | 25 +- drivers/pci/rockchip/pcie-rockchip.h | 92 +++++ 5 files changed, 762 insertions(+), 9 deletions(-) create mode 100644 drivers/pci/rockchip/pcie-rockchip-ep.c diff --git a/drivers/pci/rockchip/Kconfig b/drivers/pci/rockchip/Kconfig index d655b77..668f850 100644 --- a/drivers/pci/rockchip/Kconfig +++ b/drivers/pci/rockchip/Kconfig @@ -17,4 +17,16 @@ config PCIE_ROCKCHIP_HOST There is 1 internal PCIe port available to support GEN2 with 4 slots. +config PCIE_ROCKCHIP_EP + bool "Rockchip PCIe endpoint controller" + depends on ARCH_ROCKCHIP || COMPILE_TEST + depends on OF + depends on PCI_ENDPOINT + select MFD_SYSCON + select PCIE_ROCKCHIP + help + Say Y here if you want to support Rockchip PCIe controller in + endpoint mode on Rockchip SoC. There is 1 internal PCIe port + available to support GEN2 with 4 slots. + endmenu diff --git a/drivers/pci/rockchip/Makefile b/drivers/pci/rockchip/Makefile index 0af40db..8dce495 100644 --- a/drivers/pci/rockchip/Makefile +++ b/drivers/pci/rockchip/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o +obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o diff --git a/drivers/pci/rockchip/pcie-rockchip-ep.c b/drivers/pci/rockchip/pcie-rockchip-ep.c new file mode 100644 index 0000000..afe9fc4 --- /dev/null +++ b/drivers/pci/rockchip/pcie-rockchip-ep.c @@ -0,0 +1,641 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Rockchip AXI PCIe endpoint controller driver + * + * Copyright (c) 2018 Rockchip, Inc. + * + * Author: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> + * Simon Xue <xxm-TNX95d0MmH7DzftRWevZcw@public.gmane.org> + * + * Bits taken from Cadence endpoint controller driver + */ + +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/pci-epc.h> +#include <linux/platform_device.h> +#include <linux/sizes.h> +#include <linux/delay.h> +#include <linux/configfs.h> +#include <linux/pci-epf.h> + +#include "pcie-rockchip.h" + +/** + * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver + * @pcie: Rockchip PCIe controller + * @data: pointer to a 'struct rockchip_pcie_data' + * @ob_region_map: bitmask of mapped outbound regions + * @ob_addr: base addresses in the AXI bus where the outbound regions start + * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ + * dedicated outbound regions is mapped. + * @irq_cpu_addr: base address in the CPU space where a write access triggers + * the sending of a memory write (MSI) / normal message (legacy + * IRQ) TLP through the PCIe bus. + * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ + * dedicated outbound region. + * @irq_pci_fn: the latest PCI function that has updated the mapping of + * the MSI/legacy IRQ dedicated outbound region. + * @irq_pending: bitmask of asserted legacy IRQs. + * @max_regions: maximum number of regions supported by hardware + */ +struct rockchip_pcie_ep { + rockchip_pcie_epc pcie; + struct pci_epc *epc; + unsigned long ob_region_map; + phys_addr_t *ob_addr; + phys_addr_t irq_phys_addr; + void __iomem *irq_cpu_addr; + u64 irq_pci_addr; + u8 irq_pci_fn; + u8 irq_pending; + u32 max_regions; +}; + +void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, + u32 r, u32 type, u64 cpu_addr, u64 pci_addr, + size_t size, bool is_clr) +{ + u64 sz = 1ULL << fls64(size - 1); + int num_pass_bits = ilog2(sz); + u32 addr0, addr1, desc0, desc1; + bool is_nor_msg = (type == AXI_WRAPPER_NOR_MSG); + + if (is_clr) { + rockchip_pcie_write(rockchip, 0, + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); + rockchip_pcie_write(rockchip, 0, + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); + rockchip_pcie_write(rockchip, 0, + ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); + rockchip_pcie_write(rockchip, 0, + ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); + rockchip_pcie_write(rockchip, 0, + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r)); + rockchip_pcie_write(rockchip, 0, + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r)); + return; + } + + /* The minimal region size is 1MB */ + if (num_pass_bits < 8) + num_pass_bits = 8; + + cpu_addr -= rockchip->mem_res->start; + addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1)) & + PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | + (lower_32_bits(cpu_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); + addr1 = upper_32_bits(is_nor_msg ? cpu_addr : pci_addr); + desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | type; + desc1 = 0; + + if (is_nor_msg) { + rockchip_pcie_write(rockchip, 0, + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); + rockchip_pcie_write(rockchip, 0, + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); + rockchip_pcie_write(rockchip, desc0, + ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); + rockchip_pcie_write(rockchip, desc1, + ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); + } else { + /* PCI bus address region */ + rockchip_pcie_write(rockchip, addr0, + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); + rockchip_pcie_write(rockchip, addr1, + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); + rockchip_pcie_write(rockchip, desc0, + ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); + rockchip_pcie_write(rockchip, desc1, + ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); + + addr0 = + ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | + (lower_32_bits(cpu_addr) & + PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); + addr1 = upper_32_bits(cpu_addr); + } + + /* CPU bus address region */ + rockchip_pcie_write(rockchip, addr0, + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r)); + rockchip_pcie_write(rockchip, addr1, + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r)); +} + +static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, + struct pci_epf_header *hdr) +{ + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *rockchip = &ep->pcie; + + /* All functions share the same vendor ID with function 0 */ + if (fn == 0) { + u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) | + (hdr->subsys_vendor_id & GENMASK(31, 16)) << 16; + + rockchip_pcie_write(rockchip, vid_regs, + PCIE_CORE_CONFIG_VENDOR); + } + + rockchip_pcie_write(rockchip, hdr->deviceid << 16, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID); + + rockchip_pcie_write(rockchip, + hdr->revid | + hdr->progif_code << 8 | + hdr->subclass_code << 16 | + hdr->baseclass_code << 24, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_REVISION_ID); + rockchip_pcie_write(rockchip, hdr->cache_line_size, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + PCI_CACHE_LINE_SIZE); + rockchip_pcie_write(rockchip, hdr->subsys_id << 16, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + PCI_SUBSYSTEM_VENDOR_ID); + rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + PCI_INTERRUPT_LINE); + + return 0; + +} + +static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, + enum pci_barno bar, dma_addr_t bar_phys, + size_t size, int flags) +{ + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *rockchip = &ep->pcie; + u32 addr0, addr1, reg, cfg, b, aperture, ctrl; + u64 sz; + + /* BAR size is 2^(aperture + 7) */ + sz = max_t(size_t, size, MIN_EP_APERTURE); + + /* + * roundup_pow_of_two() returns an unsigned long, which is not suited + * for 64bit values. + */ + sz = 1ULL << fls64(sz - 1); + aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ + + if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS; + } else { + bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); + bool is_64bits = sz > SZ_2G; + + if (is_64bits && (bar & 1)) + return -EINVAL; + + if (is_64bits && is_prefetch) + ctrl = + ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; + else if (is_prefetch) + ctrl = + ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS; + else if (is_64bits) + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS; + else + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS; + } + + if (bar < BAR_4) { + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn); + b = bar; + } else { + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn); + b = bar - BAR_4; + } + + addr0 = lower_32_bits(bar_phys); + addr1 = upper_32_bits(bar_phys); + + cfg = rockchip_pcie_read(rockchip, reg); + cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); + cfg |= (ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) | + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); + + rockchip_pcie_write(rockchip, cfg, reg); + rockchip_pcie_write(rockchip, addr0, + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar)); + rockchip_pcie_write(rockchip, addr1, + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar)); + + return 0; +} + +static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, + enum pci_barno bar) +{ + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *rockchip = &ep->pcie; + u32 reg, cfg, b, ctrl; + + if (bar < BAR_4) { + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn); + b = bar; + } else { + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn); + b = bar - BAR_4; + } + + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED; + cfg = rockchip_pcie_read(rockchip, reg); + cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); + cfg |= ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl); + + rockchip_pcie_write(rockchip, cfg, reg); + rockchip_pcie_write(rockchip, 0x0, + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar)); + rockchip_pcie_write(rockchip, 0x0, + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar)); + +} + +static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, + phys_addr_t addr, u64 pci_addr, + size_t size) +{ + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *pcie = &ep->pcie; + u32 r; + + r = find_first_zero_bit(&ep->ob_region_map, + sizeof(ep->ob_region_map) * BITS_PER_LONG); + if (r >= ep->max_regions - 1) { + dev_err(&epc->dev, "no free outbound region\n"); + return -EINVAL; + } + + rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, AXI_WRAPPER_MEM_WRITE, addr, + pci_addr, size, false); + + set_bit(r, &ep->ob_region_map); + ep->ob_addr[r] = addr; + + return 0; + +} + +static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, + phys_addr_t addr) +{ + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *rockchip = &ep->pcie; + u32 r; + + for (r = 0; r < ep->max_regions - 1; r++) + if (ep->ob_addr[r] == addr) + break; + + if (r == ep->max_regions - 1) + return; + + rockchip_pcie_prog_ep_ob_atu(rockchip, 0, 0, 0, 0, 0, 0, true); + + ep->ob_addr[r] = 0; + clear_bit(r, &ep->ob_region_map); +} + +static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, + u8 multi_msg_cap) +{ + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *rockchip = &ep->pcie; + u16 flags; + + flags = rockchip_pcie_read(rockchip, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); + flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK; + flags |= + ((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | + PCI_MSI_FLAGS_64BIT; + flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP; + rockchip_pcie_write(rockchip, flags, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); + return 0; +} + +static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) +{ + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *rockchip = &ep->pcie; + u16 flags; + + flags = rockchip_pcie_read(rockchip, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); + if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME)) + return -EINVAL; + + return ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >> + ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET); +} + +static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn, + u8 intx, bool is_asserted) +{ + struct rockchip_pcie *rockchip = &ep->pcie; + u32 r = ep->max_regions - 1; + u32 offset; + u16 status; + u8 msg_code; + + if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR || + ep->irq_pci_fn != fn)) { + rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r, + AXI_WRAPPER_NOR_MSG, + ep->irq_phys_addr, 0, 0, false); + ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR; + ep->irq_pci_fn = fn; + } + + intx &= 3; + if (is_asserted) { + ep->irq_pending |= BIT(intx); + msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx; + } else { + ep->irq_pending &= ~BIT(intx); + msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx; + } + + status = rockchip_pcie_read(rockchip, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + ROCKCHIP_PCIE_EP_CMD_STATUS); + status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; + + if ((status != 0) ^ (ep->irq_pending != 0)) { + status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; + rockchip_pcie_write(rockchip, status, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + ROCKCHIP_PCIE_EP_CMD_STATUS); + } + + offset = + ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) | + ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA; + writel(0, ep->irq_cpu_addr + offset); +} + +static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn, + u8 intx) +{ + u16 cmd; + + cmd = rockchip_pcie_read(&ep->pcie, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + ROCKCHIP_PCIE_EP_CMD_STATUS); + + if (cmd & PCI_COMMAND_INTX_DISABLE) + return -EINVAL; + + rockchip_pcie_ep_assert_intx(ep, fn, intx, true); + mdelay(1); + rockchip_pcie_ep_assert_intx(ep, fn, intx, false); + return 0; +} + +static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, + u8 interrupt_num) +{ + struct rockchip_pcie *rockchip = &ep->pcie; + u16 flags, mme, data, data_mask; + u8 msi_count; + u64 pci_addr, pci_addr_mask = 0xff; + + /* Check MSI enable bit */ + flags = rockchip_pcie_read(&ep->pcie, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); + if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME)) + return -EINVAL; + + /* Get MSI numbers from MME */ + mme = ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >> + ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET); + msi_count = 1 << mme; + if (!interrupt_num || interrupt_num > msi_count) + return -EINVAL; + + /* Set MSI private data */ + data_mask = msi_count - 1; + data = rockchip_pcie_read(rockchip, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + ROCKCHIP_PCIE_EP_MSI_CTRL_REG + + PCI_MSI_DATA_64); + data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask); + + /* Get MSI PCI address */ + pci_addr = rockchip_pcie_read(rockchip, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + ROCKCHIP_PCIE_EP_MSI_CTRL_REG + + PCI_MSI_ADDRESS_HI); + pci_addr <<= 32; + pci_addr |= rockchip_pcie_read(rockchip, + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + + ROCKCHIP_PCIE_EP_MSI_CTRL_REG + + PCI_MSI_ADDRESS_LO); + pci_addr &= GENMASK_ULL(63, 2); + + /* Set the outbound region if needed. */ + if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) || + ep->irq_pci_fn != fn)) { + rockchip_pcie_prog_ep_ob_atu(rockchip, fn, ep->max_regions - 1, + AXI_WRAPPER_MEM_WRITE, + ep->irq_phys_addr, + pci_addr & ~pci_addr_mask, + pci_addr_mask + 1, false); + ep->irq_pci_addr = (pci_addr & ~pci_addr_mask); + ep->irq_pci_fn = fn; + } + + writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); + return 0; +} + + +static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, + enum pci_epc_irq_type type, + u8 interrupt_num) +{ + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0); + case PCI_EPC_IRQ_MSI: + return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num); + default: + return -EINVAL; + } +} + +static int rockchip_pcie_ep_start(struct pci_epc *epc) +{ + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *rockchip = &ep->pcie; + struct pci_epf *epf; + u32 cfg; + + cfg = BIT(0); + list_for_each_entry(epf, &epc->pci_epf, list) + cfg |= BIT(epf->func_no); + + rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG); + + list_for_each_entry(epf, &epc->pci_epf, list) + pci_epf_linkup(epf); + + return 0; +} + +static const struct pci_epc_ops rockchip_pcie_epc_ops = { + .write_header = rockchip_pcie_ep_write_header, + .set_bar = rockchip_pcie_ep_set_bar, + .clear_bar = rockchip_pcie_ep_clear_bar, + .map_addr = rockchip_pcie_ep_map_addr, + .unmap_addr = rockchip_pcie_ep_unmap_addr, + .set_msi = rockchip_pcie_ep_set_msi, + .get_msi = rockchip_pcie_ep_get_msi, + .raise_irq = rockchip_pcie_ep_raise_irq, + .start = rockchip_pcie_ep_start, +}; + +/** + * rockchip_pcie_parse_dt - Parse Device Tree + * @rockchip: PCIe port information + * + * Return: '0' on success and error value on failure + */ +static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip, + struct rockchip_pcie_ep *ep) +{ + struct device *dev = rockchip->dev; + int err; + + err = rockchip_pcie_parse_dt(rockchip); + if (err) + return err; + + err = rockchip_pcie_get_phys(rockchip); + if (err) + return err; + + err = of_property_read_u32(dev->of_node, + "rockchip,max-outbound-regions", + &ep->max_regions); + if (err < 0 || ep->max_regions > MAX_REGION_LIMIT) + ep->max_regions = MAX_REGION_LIMIT; + + err = of_property_read_u8(dev->of_node, "max-functions", + &ep->epc->max_functions); + if (err < 0) + ep->epc->max_functions = 1; + + return 0; +} + +static const struct of_device_id rockchip_pcie_ep_of_match[] = { + { .compatible = "rockchip,rk3399-pcie-ep"}, + {}, +}; + +static int rockchip_pcie_ep_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rockchip_pcie_ep *ep; + rockchip_pcie_epc *rockchip; + struct pci_epc *epc; + size_t max_regions; + int err; + + ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); + if (!ep) + return -ENOMEM; + + platform_set_drvdata(pdev, ep); + + rockchip = &ep->pcie; + rockchip->is_rc = false; + rockchip->dev = dev; + + epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops); + if (IS_ERR(epc)) { + dev_err(dev, "failed to create epc device\n"); + return PTR_ERR(epc); + } + + ep->epc = epc; + epc_set_drvdata(epc, ep); + + err = rockchip_pcie_parse_ep_dt(rockchip, ep); + if (err) + return err; + + err = rockchip_pcie_enable_clocks(rockchip); + if (err) + return err; + + err = rockchip_pcie_init_port(rockchip); + if (err) + goto err_disable_clocks; + + /* Establish the link automatically */ + rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, + PCIE_CLIENT_CONFIG); + + max_regions = ep->max_regions; + ep->ob_addr = devm_kzalloc(dev, max_regions * sizeof(*ep->ob_addr), + GFP_KERNEL); + + if (!ep->ob_addr) { + err = -ENOMEM; + goto err_uninit_port; + } + + /* Only enable function 0 by default */ + rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); + + + err = pci_epc_mem_init(epc, rockchip->mem_res->start, + resource_size(rockchip->mem_res)); + if (err < 0) { + dev_err(dev, "failed to initialize the memory space\n"); + goto err_uninit_port; + } + + ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, + SZ_128K); + if (!ep->irq_cpu_addr) { + dev_err(dev, "failed to reserve memory space for MSI\n"); + err = -ENOMEM; + goto err_epc_mem_exit; + } + + ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; + + return 0; +err_epc_mem_exit: + pci_epc_mem_exit(epc); +err_uninit_port: + rockchip_pcie_deinit_phys(rockchip); +err_disable_clocks: + rockchip_pcie_disable_clocks(rockchip); + return err; +} + +static struct platform_driver rockchip_pcie_ep_driver = { + .driver = { + .name = "rockchip-pcie-ep", + .of_match_table = rockchip_pcie_ep_of_match, + }, + .probe = rockchip_pcie_ep_probe, +}; + +builtin_platform_driver(rockchip_pcie_ep_driver); diff --git a/drivers/pci/rockchip/pcie-rockchip.c b/drivers/pci/rockchip/pcie-rockchip.c index d03508c..1d38ad7 100644 --- a/drivers/pci/rockchip/pcie-rockchip.c +++ b/drivers/pci/rockchip/pcie-rockchip.c @@ -29,15 +29,22 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) struct resource *regs; int err; - regs = platform_get_resource_byname(pdev, - IORESOURCE_MEM, - "axi-base"); - rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); - if (IS_ERR(rockchip->reg_base)) - return PTR_ERR(rockchip->reg_base); - - regs = platform_get_resource_byname(pdev, - IORESOURCE_MEM, + if (rockchip->is_rc) { + regs = platform_get_resource_byname(pdev, + IORESOURCE_MEM, + "axi-base"); + rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); + if (IS_ERR(rockchip->reg_base)) + return PTR_ERR(rockchip->reg_base); + } else { + rockchip->mem_res = + platform_get_resource_byname(pdev, IORESOURCE_MEM, + "mem-base"); + if (!rockchip->mem_res) + return -EINVAL; + } + + regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb-base"); rockchip->apb_base = devm_ioremap_resource(dev, regs); if (IS_ERR(rockchip->apb_base)) diff --git a/drivers/pci/rockchip/pcie-rockchip.h b/drivers/pci/rockchip/pcie-rockchip.h index af3e74f..f4bfc22 100644 --- a/drivers/pci/rockchip/pcie-rockchip.h +++ b/drivers/pci/rockchip/pcie-rockchip.h @@ -23,6 +23,9 @@ #define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4) #define MAX_LANE_NUM 4 +#define MAX_REGION_LIMIT 32 +#define MIN_EP_APERTURE 28 + #define PCIE_CLIENT_BASE 0x0 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) @@ -109,7 +112,14 @@ #define PCIE_CORE_INT_MMVC BIT(19) #define PCIE_CORE_CONFIG_VENDOR (PCIE_CORE_CTRL_MGMT_BASE + 0x44) #define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210) +#define PCIE_CORE_PHY_FUNC_CFG (PCIE_CORE_CTRL_MGMT_BASE + 0x2c0) #define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300) +#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED 0x0 +#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS 0x1 +#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS 0x4 +#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 +#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS 0x6 +#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 #define PCIE_CORE_INT \ (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \ @@ -120,6 +130,7 @@ PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \ PCIE_CORE_INT_MMVC) +#define PCIE_RC_RP_ATS_BASE 0x400000 #define PCIE_RC_CONFIG_NORMAL_BASE 0x800000 #define PCIE_RC_CONFIG_BASE 0xa00000 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) @@ -188,6 +199,85 @@ #define RC_REGION_0_TYPE_MASK GENMASK(3, 0) #define MAX_AXI_WRAPPER_REGION_NUM 33 + +#define ROCKCHIP_PCIE_MSG_ROUTING_TO_RC 0x0 +#define ROCKCHIP_PCIE_MSG_ROUTING_VIA_ADDR 0x1 +#define ROCKCHIP_PCIE_MSG_ROUTING_VIA_ID 0x2 +#define ROCKCHIP_PCIE_MSG_ROUTING_BROADCAST 0x3 +#define ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX 0x4 +#define ROCKCHIP_PCIE_MSG_ROUTING_PME_ACK 0x5 +#define ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA 0x20 +#define ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTB 0x21 +#define ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTC 0x22 +#define ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTD 0x23 +#define ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA 0x24 +#define ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTB 0x25 +#define ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTC 0x26 +#define ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTD 0x27 +#define ROCKCHIP_PCIE_MSG_ROUTING_MASK GENMASK(7, 5) +#define ROCKCHIP_PCIE_MSG_ROUTING(route) \ + (((route) << 5) & ROCKCHIP_PCIE_MSG_ROUTING_MASK) +#define ROCKCHIP_PCIE_MSG_CODE_MASK GENMASK(15, 8) +#define ROCKCHIP_PCIE_MSG_CODE(code) \ + (((code) << 8) & ROCKCHIP_PCIE_MSG_CODE_MASK) +#define ROCKCHIP_PCIE_MSG_NO_DATA BIT(16) + + +#define ROCKCHIP_PCIE_EP_CMD_STATUS 0x4 +#define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19) +#define ROCKCHIP_PCIE_EP_MSI_CTRL_REG 0x90 +#define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET 17 +#define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17) +#define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET 20 +#define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK GENMASK(22, 20) +#define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(16) +#define ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP BIT(24) +#define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1 +#define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3 +#define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) +#define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ + (PCIE_RC_RP_ATS_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) +#define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ + (PCIE_RC_RP_ATS_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) +#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ + (PCIE_RC_RP_ATS_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) +#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) +#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ + (((devfn) << 12) & \ + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) +#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) +#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ + (((bus) << 20) & ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) +#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ + (PCIE_RC_RP_ATS_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) +#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) +#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) +#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ + (((devfn) << 24) & ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) +#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r) \ + (PCIE_RC_RP_ATS_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) +#define ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r) \ + (PCIE_RC_RP_ATS_BASE + 0x000c + ((r) & 0x1f) * 0x0020) +#define ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ + (PCIE_RC_RP_ATS_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) +#define ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ + (PCIE_RC_RP_ATS_BASE + 0x001c + ((r) & 0x1f) * 0x0020) + +#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn) \ + (PCIE_CORE_CTRL_MGMT_BASE + 0x0240 + (fn) * 0x0008) +#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn) \ + (PCIE_CORE_CTRL_MGMT_BASE + 0x0244 + (fn) * 0x0008) +#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ + (GENMASK(4, 0) << ((b) * 8)) +#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ + (((a) << ((b) * 8)) & \ + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) +#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ + (GENMASK(7, 5) << ((b) * 8)) +#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ + (((c) << ((b) * 8 + 5)) & \ + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) + struct rockchip_pcie { void __iomem *reg_base; /* DT axi-base */ void __iomem *apb_base; /* DT apb-base */ @@ -225,8 +315,10 @@ struct rockchip_pcie { phys_addr_t msg_bus_addr; phys_addr_t mem_bus_addr; bool is_rc; + struct resource *mem_res; }; +typedef struct rockchip_pcie rockchip_pcie_epc; static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg) { -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
[parent not found: <1519348654-243597-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* Re: [PATCH v2 5/6] PCI: rockchip: Add Endpoint controller driver for Rockchip PCIe controller [not found] ` <1519348654-243597-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> @ 2018-02-27 15:32 ` Lorenzo Pieralisi [not found] ` <20180227153202.GB7184-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org> 2018-02-28 12:11 ` Lorenzo Pieralisi 1 sibling, 1 reply; 15+ messages in thread From: Lorenzo Pieralisi @ 2018-02-27 15:32 UTC (permalink / raw) To: Shawn Lin Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring, Bjorn Helgaas On Fri, Feb 23, 2018 at 09:17:33AM +0800, Shawn Lin wrote: > This patch adds support to the Rockchip PCIe controller in endpoint mode > which currently supports up to 32 regions, and each regions should at > least be 1MB per TRM. > > Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > > --- > > Changes in v2: > - fix some error handling > > drivers/pci/rockchip/Kconfig | 12 + > drivers/pci/rockchip/Makefile | 1 + > drivers/pci/rockchip/pcie-rockchip-ep.c | 641 ++++++++++++++++++++++++++++++++ > drivers/pci/rockchip/pcie-rockchip.c | 25 +- > drivers/pci/rockchip/pcie-rockchip.h | 92 +++++ > 5 files changed, 762 insertions(+), 9 deletions(-) > create mode 100644 drivers/pci/rockchip/pcie-rockchip-ep.c > > diff --git a/drivers/pci/rockchip/Kconfig b/drivers/pci/rockchip/Kconfig > index d655b77..668f850 100644 > --- a/drivers/pci/rockchip/Kconfig > +++ b/drivers/pci/rockchip/Kconfig > @@ -17,4 +17,16 @@ config PCIE_ROCKCHIP_HOST > There is 1 internal PCIe port available to support GEN2 with > 4 slots. > > +config PCIE_ROCKCHIP_EP > + bool "Rockchip PCIe endpoint controller" > + depends on ARCH_ROCKCHIP || COMPILE_TEST > + depends on OF > + depends on PCI_ENDPOINT > + select MFD_SYSCON > + select PCIE_ROCKCHIP > + help > + Say Y here if you want to support Rockchip PCIe controller in > + endpoint mode on Rockchip SoC. There is 1 internal PCIe port > + available to support GEN2 with 4 slots. > + > endmenu > diff --git a/drivers/pci/rockchip/Makefile b/drivers/pci/rockchip/Makefile > index 0af40db..8dce495 100644 > --- a/drivers/pci/rockchip/Makefile > +++ b/drivers/pci/rockchip/Makefile > @@ -1,3 +1,4 @@ > # SPDX-License-Identifier: GPL-2.0 > obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o > obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o > +obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o > diff --git a/drivers/pci/rockchip/pcie-rockchip-ep.c b/drivers/pci/rockchip/pcie-rockchip-ep.c > new file mode 100644 > index 0000000..afe9fc4 > --- /dev/null > +++ b/drivers/pci/rockchip/pcie-rockchip-ep.c > @@ -0,0 +1,641 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Rockchip AXI PCIe endpoint controller driver > + * > + * Copyright (c) 2018 Rockchip, Inc. > + * > + * Author: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > + * Simon Xue <xxm-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > + * > + * Bits taken from Cadence endpoint controller driver I reviewed this patch and I then realized that it is not bits, it is that the drivers are almost identical. Are we talking about the same IP (possibly with some HW wrapper of sorts) ? Thanks, Lorenzo > + */ > + > +#include <linux/kernel.h> > +#include <linux/of.h> > +#include <linux/pci-epc.h> > +#include <linux/platform_device.h> > +#include <linux/sizes.h> > +#include <linux/delay.h> > +#include <linux/configfs.h> > +#include <linux/pci-epf.h> > + > +#include "pcie-rockchip.h" > + > +/** > + * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver > + * @pcie: Rockchip PCIe controller > + * @data: pointer to a 'struct rockchip_pcie_data' > + * @ob_region_map: bitmask of mapped outbound regions > + * @ob_addr: base addresses in the AXI bus where the outbound regions start > + * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ > + * dedicated outbound regions is mapped. > + * @irq_cpu_addr: base address in the CPU space where a write access triggers > + * the sending of a memory write (MSI) / normal message (legacy > + * IRQ) TLP through the PCIe bus. > + * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ > + * dedicated outbound region. > + * @irq_pci_fn: the latest PCI function that has updated the mapping of > + * the MSI/legacy IRQ dedicated outbound region. > + * @irq_pending: bitmask of asserted legacy IRQs. > + * @max_regions: maximum number of regions supported by hardware > + */ > +struct rockchip_pcie_ep { > + rockchip_pcie_epc pcie; > + struct pci_epc *epc; > + unsigned long ob_region_map; > + phys_addr_t *ob_addr; > + phys_addr_t irq_phys_addr; > + void __iomem *irq_cpu_addr; > + u64 irq_pci_addr; > + u8 irq_pci_fn; > + u8 irq_pending; > + u32 max_regions; > +}; > + > +void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, > + u32 r, u32 type, u64 cpu_addr, u64 pci_addr, > + size_t size, bool is_clr) > +{ > + u64 sz = 1ULL << fls64(size - 1); > + int num_pass_bits = ilog2(sz); > + u32 addr0, addr1, desc0, desc1; > + bool is_nor_msg = (type == AXI_WRAPPER_NOR_MSG); > + > + if (is_clr) { > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r)); > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r)); > + return; > + } > + > + /* The minimal region size is 1MB */ > + if (num_pass_bits < 8) > + num_pass_bits = 8; > + > + cpu_addr -= rockchip->mem_res->start; > + addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1)) & > + PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | > + (lower_32_bits(cpu_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); > + addr1 = upper_32_bits(is_nor_msg ? cpu_addr : pci_addr); > + desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | type; > + desc1 = 0; > + > + if (is_nor_msg) { > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); > + rockchip_pcie_write(rockchip, desc0, > + ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); > + rockchip_pcie_write(rockchip, desc1, > + ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); > + } else { > + /* PCI bus address region */ > + rockchip_pcie_write(rockchip, addr0, > + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); > + rockchip_pcie_write(rockchip, addr1, > + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); > + rockchip_pcie_write(rockchip, desc0, > + ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); > + rockchip_pcie_write(rockchip, desc1, > + ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); > + > + addr0 = > + ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | > + (lower_32_bits(cpu_addr) & > + PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); > + addr1 = upper_32_bits(cpu_addr); > + } > + > + /* CPU bus address region */ > + rockchip_pcie_write(rockchip, addr0, > + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r)); > + rockchip_pcie_write(rockchip, addr1, > + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r)); > +} > + > +static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, > + struct pci_epf_header *hdr) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + > + /* All functions share the same vendor ID with function 0 */ > + if (fn == 0) { > + u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) | > + (hdr->subsys_vendor_id & GENMASK(31, 16)) << 16; > + > + rockchip_pcie_write(rockchip, vid_regs, > + PCIE_CORE_CONFIG_VENDOR); > + } > + > + rockchip_pcie_write(rockchip, hdr->deviceid << 16, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID); > + > + rockchip_pcie_write(rockchip, > + hdr->revid | > + hdr->progif_code << 8 | > + hdr->subclass_code << 16 | > + hdr->baseclass_code << 24, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_REVISION_ID); > + rockchip_pcie_write(rockchip, hdr->cache_line_size, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + PCI_CACHE_LINE_SIZE); > + rockchip_pcie_write(rockchip, hdr->subsys_id << 16, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + PCI_SUBSYSTEM_VENDOR_ID); > + rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + PCI_INTERRUPT_LINE); > + > + return 0; > + > +} > + > +static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, > + enum pci_barno bar, dma_addr_t bar_phys, > + size_t size, int flags) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + u32 addr0, addr1, reg, cfg, b, aperture, ctrl; > + u64 sz; > + > + /* BAR size is 2^(aperture + 7) */ > + sz = max_t(size_t, size, MIN_EP_APERTURE); > + > + /* > + * roundup_pow_of_two() returns an unsigned long, which is not suited > + * for 64bit values. > + */ > + sz = 1ULL << fls64(sz - 1); > + aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ > + > + if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { > + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS; > + } else { > + bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); > + bool is_64bits = sz > SZ_2G; > + > + if (is_64bits && (bar & 1)) > + return -EINVAL; > + > + if (is_64bits && is_prefetch) > + ctrl = > + ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; > + else if (is_prefetch) > + ctrl = > + ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS; > + else if (is_64bits) > + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS; > + else > + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS; > + } > + > + if (bar < BAR_4) { > + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn); > + b = bar; > + } else { > + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn); > + b = bar - BAR_4; > + } > + > + addr0 = lower_32_bits(bar_phys); > + addr1 = upper_32_bits(bar_phys); > + > + cfg = rockchip_pcie_read(rockchip, reg); > + cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | > + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); > + cfg |= (ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) | > + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); > + > + rockchip_pcie_write(rockchip, cfg, reg); > + rockchip_pcie_write(rockchip, addr0, > + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar)); > + rockchip_pcie_write(rockchip, addr1, > + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar)); > + > + return 0; > +} > + > +static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, > + enum pci_barno bar) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + u32 reg, cfg, b, ctrl; > + > + if (bar < BAR_4) { > + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn); > + b = bar; > + } else { > + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn); > + b = bar - BAR_4; > + } > + > + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED; > + cfg = rockchip_pcie_read(rockchip, reg); > + cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | > + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); > + cfg |= ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl); > + > + rockchip_pcie_write(rockchip, cfg, reg); > + rockchip_pcie_write(rockchip, 0x0, > + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar)); > + rockchip_pcie_write(rockchip, 0x0, > + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar)); > + > +} > + > +static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, > + phys_addr_t addr, u64 pci_addr, > + size_t size) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *pcie = &ep->pcie; > + u32 r; > + > + r = find_first_zero_bit(&ep->ob_region_map, > + sizeof(ep->ob_region_map) * BITS_PER_LONG); > + if (r >= ep->max_regions - 1) { > + dev_err(&epc->dev, "no free outbound region\n"); > + return -EINVAL; > + } > + > + rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, AXI_WRAPPER_MEM_WRITE, addr, > + pci_addr, size, false); > + > + set_bit(r, &ep->ob_region_map); > + ep->ob_addr[r] = addr; > + > + return 0; > + > +} > + > +static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, > + phys_addr_t addr) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + u32 r; > + > + for (r = 0; r < ep->max_regions - 1; r++) > + if (ep->ob_addr[r] == addr) > + break; > + > + if (r == ep->max_regions - 1) > + return; > + > + rockchip_pcie_prog_ep_ob_atu(rockchip, 0, 0, 0, 0, 0, 0, true); > + > + ep->ob_addr[r] = 0; > + clear_bit(r, &ep->ob_region_map); > +} > + > +static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, > + u8 multi_msg_cap) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + u16 flags; > + > + flags = rockchip_pcie_read(rockchip, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > + flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK; > + flags |= > + ((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | > + PCI_MSI_FLAGS_64BIT; > + flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP; > + rockchip_pcie_write(rockchip, flags, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > + return 0; > +} > + > +static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + u16 flags; > + > + flags = rockchip_pcie_read(rockchip, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > + if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME)) > + return -EINVAL; > + > + return ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >> > + ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET); > +} > + > +static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn, > + u8 intx, bool is_asserted) > +{ > + struct rockchip_pcie *rockchip = &ep->pcie; > + u32 r = ep->max_regions - 1; > + u32 offset; > + u16 status; > + u8 msg_code; > + > + if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR || > + ep->irq_pci_fn != fn)) { > + rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r, > + AXI_WRAPPER_NOR_MSG, > + ep->irq_phys_addr, 0, 0, false); > + ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR; > + ep->irq_pci_fn = fn; > + } > + > + intx &= 3; > + if (is_asserted) { > + ep->irq_pending |= BIT(intx); > + msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx; > + } else { > + ep->irq_pending &= ~BIT(intx); > + msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx; > + } > + > + status = rockchip_pcie_read(rockchip, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_CMD_STATUS); > + status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; > + > + if ((status != 0) ^ (ep->irq_pending != 0)) { > + status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; > + rockchip_pcie_write(rockchip, status, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_CMD_STATUS); > + } > + > + offset = > + ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) | > + ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA; > + writel(0, ep->irq_cpu_addr + offset); > +} > + > +static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn, > + u8 intx) > +{ > + u16 cmd; > + > + cmd = rockchip_pcie_read(&ep->pcie, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_CMD_STATUS); > + > + if (cmd & PCI_COMMAND_INTX_DISABLE) > + return -EINVAL; > + > + rockchip_pcie_ep_assert_intx(ep, fn, intx, true); > + mdelay(1); > + rockchip_pcie_ep_assert_intx(ep, fn, intx, false); > + return 0; > +} > + > +static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, > + u8 interrupt_num) > +{ > + struct rockchip_pcie *rockchip = &ep->pcie; > + u16 flags, mme, data, data_mask; > + u8 msi_count; > + u64 pci_addr, pci_addr_mask = 0xff; > + > + /* Check MSI enable bit */ > + flags = rockchip_pcie_read(&ep->pcie, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > + if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME)) > + return -EINVAL; > + > + /* Get MSI numbers from MME */ > + mme = ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >> > + ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET); > + msi_count = 1 << mme; > + if (!interrupt_num || interrupt_num > msi_count) > + return -EINVAL; > + > + /* Set MSI private data */ > + data_mask = msi_count - 1; > + data = rockchip_pcie_read(rockchip, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG + > + PCI_MSI_DATA_64); > + data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask); > + > + /* Get MSI PCI address */ > + pci_addr = rockchip_pcie_read(rockchip, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG + > + PCI_MSI_ADDRESS_HI); > + pci_addr <<= 32; > + pci_addr |= rockchip_pcie_read(rockchip, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG + > + PCI_MSI_ADDRESS_LO); > + pci_addr &= GENMASK_ULL(63, 2); > + > + /* Set the outbound region if needed. */ > + if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) || > + ep->irq_pci_fn != fn)) { > + rockchip_pcie_prog_ep_ob_atu(rockchip, fn, ep->max_regions - 1, > + AXI_WRAPPER_MEM_WRITE, > + ep->irq_phys_addr, > + pci_addr & ~pci_addr_mask, > + pci_addr_mask + 1, false); > + ep->irq_pci_addr = (pci_addr & ~pci_addr_mask); > + ep->irq_pci_fn = fn; > + } > + > + writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); > + return 0; > +} > + > + > +static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, > + enum pci_epc_irq_type type, > + u8 interrupt_num) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + > + switch (type) { > + case PCI_EPC_IRQ_LEGACY: > + return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0); > + case PCI_EPC_IRQ_MSI: > + return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num); > + default: > + return -EINVAL; > + } > +} > + > +static int rockchip_pcie_ep_start(struct pci_epc *epc) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + struct pci_epf *epf; > + u32 cfg; > + > + cfg = BIT(0); > + list_for_each_entry(epf, &epc->pci_epf, list) > + cfg |= BIT(epf->func_no); > + > + rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG); > + > + list_for_each_entry(epf, &epc->pci_epf, list) > + pci_epf_linkup(epf); > + > + return 0; > +} > + > +static const struct pci_epc_ops rockchip_pcie_epc_ops = { > + .write_header = rockchip_pcie_ep_write_header, > + .set_bar = rockchip_pcie_ep_set_bar, > + .clear_bar = rockchip_pcie_ep_clear_bar, > + .map_addr = rockchip_pcie_ep_map_addr, > + .unmap_addr = rockchip_pcie_ep_unmap_addr, > + .set_msi = rockchip_pcie_ep_set_msi, > + .get_msi = rockchip_pcie_ep_get_msi, > + .raise_irq = rockchip_pcie_ep_raise_irq, > + .start = rockchip_pcie_ep_start, > +}; > + > +/** > + * rockchip_pcie_parse_dt - Parse Device Tree > + * @rockchip: PCIe port information > + * > + * Return: '0' on success and error value on failure > + */ > +static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip, > + struct rockchip_pcie_ep *ep) > +{ > + struct device *dev = rockchip->dev; > + int err; > + > + err = rockchip_pcie_parse_dt(rockchip); > + if (err) > + return err; > + > + err = rockchip_pcie_get_phys(rockchip); > + if (err) > + return err; > + > + err = of_property_read_u32(dev->of_node, > + "rockchip,max-outbound-regions", > + &ep->max_regions); > + if (err < 0 || ep->max_regions > MAX_REGION_LIMIT) > + ep->max_regions = MAX_REGION_LIMIT; > + > + err = of_property_read_u8(dev->of_node, "max-functions", > + &ep->epc->max_functions); > + if (err < 0) > + ep->epc->max_functions = 1; > + > + return 0; > +} > + > +static const struct of_device_id rockchip_pcie_ep_of_match[] = { > + { .compatible = "rockchip,rk3399-pcie-ep"}, > + {}, > +}; > + > +static int rockchip_pcie_ep_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct rockchip_pcie_ep *ep; > + rockchip_pcie_epc *rockchip; > + struct pci_epc *epc; > + size_t max_regions; > + int err; > + > + ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); > + if (!ep) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, ep); > + > + rockchip = &ep->pcie; > + rockchip->is_rc = false; > + rockchip->dev = dev; > + > + epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops); > + if (IS_ERR(epc)) { > + dev_err(dev, "failed to create epc device\n"); > + return PTR_ERR(epc); > + } > + > + ep->epc = epc; > + epc_set_drvdata(epc, ep); > + > + err = rockchip_pcie_parse_ep_dt(rockchip, ep); > + if (err) > + return err; > + > + err = rockchip_pcie_enable_clocks(rockchip); > + if (err) > + return err; > + > + err = rockchip_pcie_init_port(rockchip); > + if (err) > + goto err_disable_clocks; > + > + /* Establish the link automatically */ > + rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, > + PCIE_CLIENT_CONFIG); > + > + max_regions = ep->max_regions; > + ep->ob_addr = devm_kzalloc(dev, max_regions * sizeof(*ep->ob_addr), > + GFP_KERNEL); > + > + if (!ep->ob_addr) { > + err = -ENOMEM; > + goto err_uninit_port; > + } > + > + /* Only enable function 0 by default */ > + rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); > + > + > + err = pci_epc_mem_init(epc, rockchip->mem_res->start, > + resource_size(rockchip->mem_res)); > + if (err < 0) { > + dev_err(dev, "failed to initialize the memory space\n"); > + goto err_uninit_port; > + } > + > + ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, > + SZ_128K); > + if (!ep->irq_cpu_addr) { > + dev_err(dev, "failed to reserve memory space for MSI\n"); > + err = -ENOMEM; > + goto err_epc_mem_exit; > + } > + > + ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; > + > + return 0; > +err_epc_mem_exit: > + pci_epc_mem_exit(epc); > +err_uninit_port: > + rockchip_pcie_deinit_phys(rockchip); > +err_disable_clocks: > + rockchip_pcie_disable_clocks(rockchip); > + return err; > +} > + > +static struct platform_driver rockchip_pcie_ep_driver = { > + .driver = { > + .name = "rockchip-pcie-ep", > + .of_match_table = rockchip_pcie_ep_of_match, > + }, > + .probe = rockchip_pcie_ep_probe, > +}; > + > +builtin_platform_driver(rockchip_pcie_ep_driver); > diff --git a/drivers/pci/rockchip/pcie-rockchip.c b/drivers/pci/rockchip/pcie-rockchip.c > index d03508c..1d38ad7 100644 > --- a/drivers/pci/rockchip/pcie-rockchip.c > +++ b/drivers/pci/rockchip/pcie-rockchip.c > @@ -29,15 +29,22 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) > struct resource *regs; > int err; > > - regs = platform_get_resource_byname(pdev, > - IORESOURCE_MEM, > - "axi-base"); > - rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); > - if (IS_ERR(rockchip->reg_base)) > - return PTR_ERR(rockchip->reg_base); > - > - regs = platform_get_resource_byname(pdev, > - IORESOURCE_MEM, > + if (rockchip->is_rc) { > + regs = platform_get_resource_byname(pdev, > + IORESOURCE_MEM, > + "axi-base"); > + rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); > + if (IS_ERR(rockchip->reg_base)) > + return PTR_ERR(rockchip->reg_base); > + } else { > + rockchip->mem_res = > + platform_get_resource_byname(pdev, IORESOURCE_MEM, > + "mem-base"); > + if (!rockchip->mem_res) > + return -EINVAL; > + } > + > + regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, > "apb-base"); > rockchip->apb_base = devm_ioremap_resource(dev, regs); > if (IS_ERR(rockchip->apb_base)) > diff --git a/drivers/pci/rockchip/pcie-rockchip.h b/drivers/pci/rockchip/pcie-rockchip.h > index af3e74f..f4bfc22 100644 > --- a/drivers/pci/rockchip/pcie-rockchip.h > +++ b/drivers/pci/rockchip/pcie-rockchip.h > @@ -23,6 +23,9 @@ > > #define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4) > #define MAX_LANE_NUM 4 > +#define MAX_REGION_LIMIT 32 > +#define MIN_EP_APERTURE 28 > + > > #define PCIE_CLIENT_BASE 0x0 > #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) > @@ -109,7 +112,14 @@ > #define PCIE_CORE_INT_MMVC BIT(19) > #define PCIE_CORE_CONFIG_VENDOR (PCIE_CORE_CTRL_MGMT_BASE + 0x44) > #define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210) > +#define PCIE_CORE_PHY_FUNC_CFG (PCIE_CORE_CTRL_MGMT_BASE + 0x2c0) > #define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300) > +#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED 0x0 > +#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS 0x1 > +#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS 0x4 > +#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 > +#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS 0x6 > +#define ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 > > #define PCIE_CORE_INT \ > (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \ > @@ -120,6 +130,7 @@ > PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \ > PCIE_CORE_INT_MMVC) > > +#define PCIE_RC_RP_ATS_BASE 0x400000 > #define PCIE_RC_CONFIG_NORMAL_BASE 0x800000 > #define PCIE_RC_CONFIG_BASE 0xa00000 > #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) > @@ -188,6 +199,85 @@ > #define RC_REGION_0_TYPE_MASK GENMASK(3, 0) > #define MAX_AXI_WRAPPER_REGION_NUM 33 > > + > +#define ROCKCHIP_PCIE_MSG_ROUTING_TO_RC 0x0 > +#define ROCKCHIP_PCIE_MSG_ROUTING_VIA_ADDR 0x1 > +#define ROCKCHIP_PCIE_MSG_ROUTING_VIA_ID 0x2 > +#define ROCKCHIP_PCIE_MSG_ROUTING_BROADCAST 0x3 > +#define ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX 0x4 > +#define ROCKCHIP_PCIE_MSG_ROUTING_PME_ACK 0x5 > +#define ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA 0x20 > +#define ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTB 0x21 > +#define ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTC 0x22 > +#define ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTD 0x23 > +#define ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA 0x24 > +#define ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTB 0x25 > +#define ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTC 0x26 > +#define ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTD 0x27 > +#define ROCKCHIP_PCIE_MSG_ROUTING_MASK GENMASK(7, 5) > +#define ROCKCHIP_PCIE_MSG_ROUTING(route) \ > + (((route) << 5) & ROCKCHIP_PCIE_MSG_ROUTING_MASK) > +#define ROCKCHIP_PCIE_MSG_CODE_MASK GENMASK(15, 8) > +#define ROCKCHIP_PCIE_MSG_CODE(code) \ > + (((code) << 8) & ROCKCHIP_PCIE_MSG_CODE_MASK) > +#define ROCKCHIP_PCIE_MSG_NO_DATA BIT(16) > + > + > +#define ROCKCHIP_PCIE_EP_CMD_STATUS 0x4 > +#define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19) > +#define ROCKCHIP_PCIE_EP_MSI_CTRL_REG 0x90 > +#define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET 17 > +#define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17) > +#define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET 20 > +#define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK GENMASK(22, 20) > +#define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(16) > +#define ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP BIT(24) > +#define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1 > +#define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3 > +#define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) > +#define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ > + (PCIE_RC_RP_ATS_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) > +#define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ > + (PCIE_RC_RP_ATS_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) > +#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ > + (PCIE_RC_RP_ATS_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) > +#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) > +#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ > + (((devfn) << 12) & \ > + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) > +#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) > +#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ > + (((bus) << 20) & ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) > +#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ > + (PCIE_RC_RP_ATS_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) > +#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) > +#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) > +#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ > + (((devfn) << 24) & ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) > +#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r) \ > + (PCIE_RC_RP_ATS_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) > +#define ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r) \ > + (PCIE_RC_RP_ATS_BASE + 0x000c + ((r) & 0x1f) * 0x0020) > +#define ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ > + (PCIE_RC_RP_ATS_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) > +#define ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ > + (PCIE_RC_RP_ATS_BASE + 0x001c + ((r) & 0x1f) * 0x0020) > + > +#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn) \ > + (PCIE_CORE_CTRL_MGMT_BASE + 0x0240 + (fn) * 0x0008) > +#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn) \ > + (PCIE_CORE_CTRL_MGMT_BASE + 0x0244 + (fn) * 0x0008) > +#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ > + (GENMASK(4, 0) << ((b) * 8)) > +#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ > + (((a) << ((b) * 8)) & \ > + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) > +#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ > + (GENMASK(7, 5) << ((b) * 8)) > +#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ > + (((c) << ((b) * 8 + 5)) & \ > + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) > + > struct rockchip_pcie { > void __iomem *reg_base; /* DT axi-base */ > void __iomem *apb_base; /* DT apb-base */ > @@ -225,8 +315,10 @@ struct rockchip_pcie { > phys_addr_t msg_bus_addr; > phys_addr_t mem_bus_addr; > bool is_rc; > + struct resource *mem_res; > }; > > +typedef struct rockchip_pcie rockchip_pcie_epc; > > static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg) > { > -- > 1.9.1 > > ^ permalink raw reply [flat|nested] 15+ messages in thread
[parent not found: <20180227153202.GB7184-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org>]
* Re: [PATCH v2 5/6] PCI: rockchip: Add Endpoint controller driver for Rockchip PCIe controller [not found] ` <20180227153202.GB7184-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org> @ 2018-02-28 1:40 ` Shawn Lin [not found] ` <8244c52c-73d3-5b20-eb39-ddc37968163a-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 0 siblings, 1 reply; 15+ messages in thread From: Shawn Lin @ 2018-02-28 1:40 UTC (permalink / raw) To: Lorenzo Pieralisi Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA, shawn.lin-TNX95d0MmH7DzftRWevZcw, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring, Bjorn Helgaas Dear Lorenzo, On 2018/2/27 23:32, Lorenzo Pieralisi wrote: > On Fri, Feb 23, 2018 at 09:17:33AM +0800, Shawn Lin wrote: >> This patch adds support to the Rockchip PCIe controller in endpoint mode >> which currently supports up to 32 regions, and each regions should at >> least be 1MB per TRM. >> >> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> >> > > I reviewed this patch and I then realized that it is not bits, it is > that the drivers are almost identical. Are we talking about the same IP > (possibly with some HW wrapper of sorts) ? > Nope, I would seriouly say they are not the same IP legally :) If we take about IP, it's referred to a functional entity designed and licensed by the provider, but it's not the case here since (1) There is nothing about cadence throughout the TRM when upstreamed it in 2016, and actually it was designed much earlier than 2016. (2) Much of the flow was different, and even some of the bit offset is different per my reading of cadence's driver, though most registers looks much similar. So my best guess was HW guys referenced to cadence's register layout(or the reverse), so they are much partially compatible from the register level POV, but the backend design are different leading to the quite different control flow and also rockchip controller have lots of HW bugs that I didn't see them when reviewing cadence's driver which do the same flow using similar register. That's very common if you search drivers/mmc/host/sdhci*, which means all of them share the *same* register layout and control flow, so it makes software guys' life easy, but still they are different IPs. But it's sightly different here as the pcie registers aren't the totally same and the flow control is different. Also historically that happened for other controllers designed from rockchip, for instance, SPI controller looks much like designware one, but the flow control was totally differnt preventing SW guys to refactor the designware driver to fit for rockchip one. This is all I could guess here, hope that help for you. > > > ^ permalink raw reply [flat|nested] 15+ messages in thread
[parent not found: <8244c52c-73d3-5b20-eb39-ddc37968163a-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* Re: [PATCH v2 5/6] PCI: rockchip: Add Endpoint controller driver for Rockchip PCIe controller [not found] ` <8244c52c-73d3-5b20-eb39-ddc37968163a-TNX95d0MmH7DzftRWevZcw@public.gmane.org> @ 2018-02-28 11:22 ` Lorenzo Pieralisi 0 siblings, 0 replies; 15+ messages in thread From: Lorenzo Pieralisi @ 2018-02-28 11:22 UTC (permalink / raw) To: Shawn Lin Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring, Bjorn Helgaas On Wed, Feb 28, 2018 at 09:40:36AM +0800, Shawn Lin wrote: > Dear Lorenzo, > > On 2018/2/27 23:32, Lorenzo Pieralisi wrote: > >On Fri, Feb 23, 2018 at 09:17:33AM +0800, Shawn Lin wrote: > >>This patch adds support to the Rockchip PCIe controller in endpoint mode > >>which currently supports up to 32 regions, and each regions should at > >>least be 1MB per TRM. > >> > >>Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > >> > > > > >I reviewed this patch and I then realized that it is not bits, it is > >that the drivers are almost identical. Are we talking about the same IP > >(possibly with some HW wrapper of sorts) ? > > > > Nope, I would seriouly say they are not the same IP legally :) > If we take about IP, it's referred to a functional entity designed > and licensed by the provider, but it's not the case here since > > (1) There is nothing about cadence throughout the TRM when upstreamed > it in 2016, and actually it was designed much earlier than 2016. > (2) Much of the flow was different, and even some of the bit offset is > different per my reading of cadence's driver, though most registers > looks much similar. > > So my best guess was HW guys referenced to cadence's register layout(or > the reverse), so they are much partially compatible from the > register level POV, but the backend design are different leading to the > quite different control flow and also rockchip controller have lots of > HW bugs that I didn't see them when reviewing cadence's driver which do > the same flow using similar register. That's very common if you search > drivers/mmc/host/sdhci*, which means all of them share the *same* > register layout and control flow, so it makes software guys' life easy, > but still they are different IPs. But it's sightly different here as > the pcie registers aren't the totally same and the flow control is > different. > > Also historically that happened for other controllers designed from > rockchip, for instance, SPI controller looks much like designware one, > but the flow control was totally differnt preventing SW guys to > refactor the designware driver to fit for rockchip one. > > This is all I could guess here, hope that help for you. Well - there is still lots of duplicated code there, which may mean duplicate bugs to fix, that's not ideal at all. It would be great if we manage to separate common code and glue code (you call it "flow" which I have no idea what it refers to) around it. I will review this patch anyway but this driver and cadence's are pretty much indentical, there is not much doubt about that. Thanks, Lorenzo ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 5/6] PCI: rockchip: Add Endpoint controller driver for Rockchip PCIe controller [not found] ` <1519348654-243597-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2018-02-27 15:32 ` Lorenzo Pieralisi @ 2018-02-28 12:11 ` Lorenzo Pieralisi [not found] ` <20180228121120.GC18879-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org> 1 sibling, 1 reply; 15+ messages in thread From: Lorenzo Pieralisi @ 2018-02-28 12:11 UTC (permalink / raw) To: Shawn Lin Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring, cyrille.pitchen-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, Bjorn Helgaas [cc: Cyrille] On Fri, Feb 23, 2018 at 09:17:33AM +0800, Shawn Lin wrote: > This patch adds support to the Rockchip PCIe controller in endpoint mode > which currently supports up to 32 regions, and each regions should at > least be 1MB per TRM. > > Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > > --- > > Changes in v2: > - fix some error handling > > drivers/pci/rockchip/Kconfig | 12 + > drivers/pci/rockchip/Makefile | 1 + > drivers/pci/rockchip/pcie-rockchip-ep.c | 641 ++++++++++++++++++++++++++++++++ > drivers/pci/rockchip/pcie-rockchip.c | 25 +- > drivers/pci/rockchip/pcie-rockchip.h | 92 +++++ > 5 files changed, 762 insertions(+), 9 deletions(-) > create mode 100644 drivers/pci/rockchip/pcie-rockchip-ep.c > > diff --git a/drivers/pci/rockchip/Kconfig b/drivers/pci/rockchip/Kconfig > index d655b77..668f850 100644 > --- a/drivers/pci/rockchip/Kconfig > +++ b/drivers/pci/rockchip/Kconfig > @@ -17,4 +17,16 @@ config PCIE_ROCKCHIP_HOST > There is 1 internal PCIe port available to support GEN2 with > 4 slots. > > +config PCIE_ROCKCHIP_EP > + bool "Rockchip PCIe endpoint controller" > + depends on ARCH_ROCKCHIP || COMPILE_TEST > + depends on OF > + depends on PCI_ENDPOINT > + select MFD_SYSCON > + select PCIE_ROCKCHIP > + help > + Say Y here if you want to support Rockchip PCIe controller in > + endpoint mode on Rockchip SoC. There is 1 internal PCIe port > + available to support GEN2 with 4 slots. > + > endmenu > diff --git a/drivers/pci/rockchip/Makefile b/drivers/pci/rockchip/Makefile > index 0af40db..8dce495 100644 > --- a/drivers/pci/rockchip/Makefile > +++ b/drivers/pci/rockchip/Makefile > @@ -1,3 +1,4 @@ > # SPDX-License-Identifier: GPL-2.0 > obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o > obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o > +obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o > diff --git a/drivers/pci/rockchip/pcie-rockchip-ep.c b/drivers/pci/rockchip/pcie-rockchip-ep.c > new file mode 100644 > index 0000000..afe9fc4 > --- /dev/null > +++ b/drivers/pci/rockchip/pcie-rockchip-ep.c > @@ -0,0 +1,641 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Rockchip AXI PCIe endpoint controller driver > + * > + * Copyright (c) 2018 Rockchip, Inc. > + * > + * Author: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > + * Simon Xue <xxm-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > + * > + * Bits taken from Cadence endpoint controller driver Well, "Bits" is an understatement here; anyway I think this is a useless comment so I would remove it. > + */ > + > +#include <linux/kernel.h> > +#include <linux/of.h> > +#include <linux/pci-epc.h> > +#include <linux/platform_device.h> > +#include <linux/sizes.h> > +#include <linux/delay.h> > +#include <linux/configfs.h> > +#include <linux/pci-epf.h> Nit: Alphabetical order. > +#include "pcie-rockchip.h" > + > +/** > + * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver > + * @pcie: Rockchip PCIe controller > + * @data: pointer to a 'struct rockchip_pcie_data' > + * @ob_region_map: bitmask of mapped outbound regions > + * @ob_addr: base addresses in the AXI bus where the outbound regions start > + * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ > + * dedicated outbound regions is mapped. > + * @irq_cpu_addr: base address in the CPU space where a write access triggers > + * the sending of a memory write (MSI) / normal message (legacy > + * IRQ) TLP through the PCIe bus. > + * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ > + * dedicated outbound region. > + * @irq_pci_fn: the latest PCI function that has updated the mapping of > + * the MSI/legacy IRQ dedicated outbound region. > + * @irq_pending: bitmask of asserted legacy IRQs. > + * @max_regions: maximum number of regions supported by hardware > + */ > +struct rockchip_pcie_ep { > + rockchip_pcie_epc pcie; > + struct pci_epc *epc; > + unsigned long ob_region_map; > + phys_addr_t *ob_addr; > + phys_addr_t irq_phys_addr; > + void __iomem *irq_cpu_addr; > + u64 irq_pci_addr; > + u8 irq_pci_fn; > + u8 irq_pending; > + u32 max_regions; > +}; > + I think struct cdns_pcie_ep layout (whose content is identical) is more sensible, follow it. > +void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, > + u32 r, u32 type, u64 cpu_addr, u64 pci_addr, > + size_t size, bool is_clr) > +{ > + u64 sz = 1ULL << fls64(size - 1); > + int num_pass_bits = ilog2(sz); > + u32 addr0, addr1, desc0, desc1; > + bool is_nor_msg = (type == AXI_WRAPPER_NOR_MSG); > + > + if (is_clr) { > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r)); > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r)); > + return; > + } You can split the (is_clr) path in a separate function, say: rockchip_pcie_clear_ep_ob_atu() it would simplify this one. > + > + /* The minimal region size is 1MB */ > + if (num_pass_bits < 8) > + num_pass_bits = 8; > + > + cpu_addr -= rockchip->mem_res->start; > + addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1)) & > + PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | > + (lower_32_bits(cpu_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); > + addr1 = upper_32_bits(is_nor_msg ? cpu_addr : pci_addr); > + desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | type; > + desc1 = 0; > + > + if (is_nor_msg) { > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); > + rockchip_pcie_write(rockchip, 0, > + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); > + rockchip_pcie_write(rockchip, desc0, > + ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); > + rockchip_pcie_write(rockchip, desc1, > + ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); > + } else { > + /* PCI bus address region */ > + rockchip_pcie_write(rockchip, addr0, > + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); > + rockchip_pcie_write(rockchip, addr1, > + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); > + rockchip_pcie_write(rockchip, desc0, > + ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); > + rockchip_pcie_write(rockchip, desc1, > + ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); > + > + addr0 = > + ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | > + (lower_32_bits(cpu_addr) & > + PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); > + addr1 = upper_32_bits(cpu_addr); > + } > + > + /* CPU bus address region */ > + rockchip_pcie_write(rockchip, addr0, > + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r)); > + rockchip_pcie_write(rockchip, addr1, > + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r)); > +} > + > +static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, > + struct pci_epf_header *hdr) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + > + /* All functions share the same vendor ID with function 0 */ > + if (fn == 0) { > + u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) | > + (hdr->subsys_vendor_id & GENMASK(31, 16)) << 16; > + > + rockchip_pcie_write(rockchip, vid_regs, > + PCIE_CORE_CONFIG_VENDOR); > + } > + > + rockchip_pcie_write(rockchip, hdr->deviceid << 16, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID); > + > + rockchip_pcie_write(rockchip, > + hdr->revid | > + hdr->progif_code << 8 | > + hdr->subclass_code << 16 | > + hdr->baseclass_code << 24, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_REVISION_ID); > + rockchip_pcie_write(rockchip, hdr->cache_line_size, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + PCI_CACHE_LINE_SIZE); > + rockchip_pcie_write(rockchip, hdr->subsys_id << 16, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + PCI_SUBSYSTEM_VENDOR_ID); > + rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + PCI_INTERRUPT_LINE); > + > + return 0; > + Useless empty line. > +} > + > +static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, > + enum pci_barno bar, dma_addr_t bar_phys, > + size_t size, int flags) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + u32 addr0, addr1, reg, cfg, b, aperture, ctrl; > + u64 sz; > + > + /* BAR size is 2^(aperture + 7) */ > + sz = max_t(size_t, size, MIN_EP_APERTURE); > + > + /* > + * roundup_pow_of_two() returns an unsigned long, which is not suited > + * for 64bit values. > + */ > + sz = 1ULL << fls64(sz - 1); > + aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ > + > + if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { > + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS; > + } else { > + bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); > + bool is_64bits = sz > SZ_2G; > + > + if (is_64bits && (bar & 1)) > + return -EINVAL; > + > + if (is_64bits && is_prefetch) > + ctrl = > + ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; > + else if (is_prefetch) > + ctrl = > + ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS; > + else if (is_64bits) > + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS; > + else > + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS; > + } > + > + if (bar < BAR_4) { > + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn); > + b = bar; > + } else { > + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn); > + b = bar - BAR_4; > + } > + > + addr0 = lower_32_bits(bar_phys); > + addr1 = upper_32_bits(bar_phys); > + > + cfg = rockchip_pcie_read(rockchip, reg); > + cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | > + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); > + cfg |= (ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) | > + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); > + > + rockchip_pcie_write(rockchip, cfg, reg); > + rockchip_pcie_write(rockchip, addr0, > + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar)); > + rockchip_pcie_write(rockchip, addr1, > + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar)); > + > + return 0; > +} > + > +static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, > + enum pci_barno bar) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + u32 reg, cfg, b, ctrl; > + > + if (bar < BAR_4) { > + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn); > + b = bar; > + } else { > + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn); > + b = bar - BAR_4; > + } > + > + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED; > + cfg = rockchip_pcie_read(rockchip, reg); > + cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | > + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); > + cfg |= ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl); > + > + rockchip_pcie_write(rockchip, cfg, reg); > + rockchip_pcie_write(rockchip, 0x0, > + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar)); > + rockchip_pcie_write(rockchip, 0x0, > + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar)); > + Useless empty line. > +} > + > +static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, > + phys_addr_t addr, u64 pci_addr, > + size_t size) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *pcie = &ep->pcie; > + u32 r; > + > + r = find_first_zero_bit(&ep->ob_region_map, > + sizeof(ep->ob_region_map) * BITS_PER_LONG); > + if (r >= ep->max_regions - 1) { Why are we comparing for equality against (max_regions - 1) ? Aren't we leaving a region out ? NB: I know this code is identical to the Cadence driver but copy and paste is not a good reason for it and if that's a bug it ought to be fixed in both drivers. > + dev_err(&epc->dev, "no free outbound region\n"); > + return -EINVAL; > + } > + > + rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, AXI_WRAPPER_MEM_WRITE, addr, > + pci_addr, size, false); > + > + set_bit(r, &ep->ob_region_map); > + ep->ob_addr[r] = addr; > + > + return 0; > + Useless empty line. > +} > + > +static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, > + phys_addr_t addr) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + u32 r; > + > + for (r = 0; r < ep->max_regions - 1; r++) > + if (ep->ob_addr[r] == addr) > + break; See above for max_regions - 1. > + > + if (r == ep->max_regions - 1) > + return; Ditto. > + > + rockchip_pcie_prog_ep_ob_atu(rockchip, 0, 0, 0, 0, 0, 0, true); > + > + ep->ob_addr[r] = 0; > + clear_bit(r, &ep->ob_region_map); > +} > + > +static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, > + u8 multi_msg_cap) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + u16 flags; > + > + flags = rockchip_pcie_read(rockchip, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > + flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK; > + flags |= > + ((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | > + PCI_MSI_FLAGS_64BIT; > + flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP; > + rockchip_pcie_write(rockchip, flags, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > + return 0; > +} > + > +static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + u16 flags; > + > + flags = rockchip_pcie_read(rockchip, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > + if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME)) > + return -EINVAL; > + > + return ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >> > + ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET); > +} > + > +static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn, > + u8 intx, bool is_asserted) > +{ > + struct rockchip_pcie *rockchip = &ep->pcie; > + u32 r = ep->max_regions - 1; > + u32 offset; > + u16 status; > + u8 msg_code; > + > + if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR || > + ep->irq_pci_fn != fn)) { > + rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r, > + AXI_WRAPPER_NOR_MSG, > + ep->irq_phys_addr, 0, 0, false); > + ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR; > + ep->irq_pci_fn = fn; > + } > + > + intx &= 3; > + if (is_asserted) { > + ep->irq_pending |= BIT(intx); > + msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx; > + } else { > + ep->irq_pending &= ~BIT(intx); > + msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx; > + } > + > + status = rockchip_pcie_read(rockchip, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_CMD_STATUS); > + status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; > + > + if ((status != 0) ^ (ep->irq_pending != 0)) { > + status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; > + rockchip_pcie_write(rockchip, status, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_CMD_STATUS); > + } > + > + offset = > + ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) | > + ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA; > + writel(0, ep->irq_cpu_addr + offset); > +} > + > +static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn, > + u8 intx) > +{ > + u16 cmd; > + > + cmd = rockchip_pcie_read(&ep->pcie, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_CMD_STATUS); > + > + if (cmd & PCI_COMMAND_INTX_DISABLE) > + return -EINVAL; > + > + rockchip_pcie_ep_assert_intx(ep, fn, intx, true); > + mdelay(1); Is there some HW engineering backing this mdelay() value ? That's a question for Cadence driver too. > + rockchip_pcie_ep_assert_intx(ep, fn, intx, false); > + return 0; > +} > + > +static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, > + u8 interrupt_num) > +{ > + struct rockchip_pcie *rockchip = &ep->pcie; > + u16 flags, mme, data, data_mask; > + u8 msi_count; > + u64 pci_addr, pci_addr_mask = 0xff; > + > + /* Check MSI enable bit */ > + flags = rockchip_pcie_read(&ep->pcie, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > + if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME)) > + return -EINVAL; > + > + /* Get MSI numbers from MME */ > + mme = ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >> > + ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET); > + msi_count = 1 << mme; > + if (!interrupt_num || interrupt_num > msi_count) > + return -EINVAL; > + > + /* Set MSI private data */ > + data_mask = msi_count - 1; > + data = rockchip_pcie_read(rockchip, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG + > + PCI_MSI_DATA_64); > + data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask); > + > + /* Get MSI PCI address */ > + pci_addr = rockchip_pcie_read(rockchip, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG + > + PCI_MSI_ADDRESS_HI); > + pci_addr <<= 32; > + pci_addr |= rockchip_pcie_read(rockchip, > + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG + > + PCI_MSI_ADDRESS_LO); > + pci_addr &= GENMASK_ULL(63, 2); > + > + /* Set the outbound region if needed. */ > + if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) || > + ep->irq_pci_fn != fn)) { > + rockchip_pcie_prog_ep_ob_atu(rockchip, fn, ep->max_regions - 1, > + AXI_WRAPPER_MEM_WRITE, > + ep->irq_phys_addr, > + pci_addr & ~pci_addr_mask, > + pci_addr_mask + 1, false); > + ep->irq_pci_addr = (pci_addr & ~pci_addr_mask); > + ep->irq_pci_fn = fn; > + } > + > + writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); > + return 0; > +} > + > + Useless empty line. > +static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, > + enum pci_epc_irq_type type, > + u8 interrupt_num) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + > + switch (type) { > + case PCI_EPC_IRQ_LEGACY: > + return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0); Why always INTA (question valid on Cadence driver too) ? > + case PCI_EPC_IRQ_MSI: > + return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num); > + default: > + return -EINVAL; > + } > +} > + > +static int rockchip_pcie_ep_start(struct pci_epc *epc) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->pcie; > + struct pci_epf *epf; > + u32 cfg; > + > + cfg = BIT(0); > + list_for_each_entry(epf, &epc->pci_epf, list) > + cfg |= BIT(epf->func_no); > + > + rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG); > + > + list_for_each_entry(epf, &epc->pci_epf, list) > + pci_epf_linkup(epf); > + > + return 0; > +} > + > +static const struct pci_epc_ops rockchip_pcie_epc_ops = { > + .write_header = rockchip_pcie_ep_write_header, > + .set_bar = rockchip_pcie_ep_set_bar, > + .clear_bar = rockchip_pcie_ep_clear_bar, > + .map_addr = rockchip_pcie_ep_map_addr, > + .unmap_addr = rockchip_pcie_ep_unmap_addr, > + .set_msi = rockchip_pcie_ep_set_msi, > + .get_msi = rockchip_pcie_ep_get_msi, > + .raise_irq = rockchip_pcie_ep_raise_irq, > + .start = rockchip_pcie_ep_start, > +}; > + > +/** > + * rockchip_pcie_parse_dt - Parse Device Tree > + * @rockchip: PCIe port information Missing a parameter. By the way a kerneldoc for this entry does not seem that useful to me, you can remove it. > + * > + * Return: '0' on success and error value on failure > + */ > +static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip, > + struct rockchip_pcie_ep *ep) > +{ > + struct device *dev = rockchip->dev; > + int err; > + > + err = rockchip_pcie_parse_dt(rockchip); > + if (err) > + return err; > + > + err = rockchip_pcie_get_phys(rockchip); > + if (err) > + return err; > + > + err = of_property_read_u32(dev->of_node, > + "rockchip,max-outbound-regions", > + &ep->max_regions); > + if (err < 0 || ep->max_regions > MAX_REGION_LIMIT) > + ep->max_regions = MAX_REGION_LIMIT; > + > + err = of_property_read_u8(dev->of_node, "max-functions", > + &ep->epc->max_functions); > + if (err < 0) > + ep->epc->max_functions = 1; > + > + return 0; > +} > + > +static const struct of_device_id rockchip_pcie_ep_of_match[] = { > + { .compatible = "rockchip,rk3399-pcie-ep"}, > + {}, > +}; > + > +static int rockchip_pcie_ep_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct rockchip_pcie_ep *ep; > + rockchip_pcie_epc *rockchip; > + struct pci_epc *epc; > + size_t max_regions; > + int err; > + > + ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); > + if (!ep) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, ep); What's this used for ? > + rockchip = &ep->pcie; > + rockchip->is_rc = false; > + rockchip->dev = dev; > + > + epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops); > + if (IS_ERR(epc)) { > + dev_err(dev, "failed to create epc device\n"); > + return PTR_ERR(epc); > + } > + > + ep->epc = epc; > + epc_set_drvdata(epc, ep); > + > + err = rockchip_pcie_parse_ep_dt(rockchip, ep); > + if (err) > + return err; > + > + err = rockchip_pcie_enable_clocks(rockchip); > + if (err) > + return err; > + > + err = rockchip_pcie_init_port(rockchip); > + if (err) > + goto err_disable_clocks; > + > + /* Establish the link automatically */ > + rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, > + PCIE_CLIENT_CONFIG); > + > + max_regions = ep->max_regions; > + ep->ob_addr = devm_kzalloc(dev, max_regions * sizeof(*ep->ob_addr), > + GFP_KERNEL); > + > + if (!ep->ob_addr) { > + err = -ENOMEM; > + goto err_uninit_port; > + } > + > + /* Only enable function 0 by default */ > + rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); > + > + Useless empty line. > + err = pci_epc_mem_init(epc, rockchip->mem_res->start, > + resource_size(rockchip->mem_res)); > + if (err < 0) { > + dev_err(dev, "failed to initialize the memory space\n"); > + goto err_uninit_port; > + } > + > + ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, > + SZ_128K); > + if (!ep->irq_cpu_addr) { > + dev_err(dev, "failed to reserve memory space for MSI\n"); > + err = -ENOMEM; > + goto err_epc_mem_exit; > + } > + > + ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; > + > + return 0; > +err_epc_mem_exit: > + pci_epc_mem_exit(epc); > +err_uninit_port: > + rockchip_pcie_deinit_phys(rockchip); > +err_disable_clocks: > + rockchip_pcie_disable_clocks(rockchip); > + return err; > +} > + > +static struct platform_driver rockchip_pcie_ep_driver = { > + .driver = { > + .name = "rockchip-pcie-ep", > + .of_match_table = rockchip_pcie_ep_of_match, > + }, > + .probe = rockchip_pcie_ep_probe, > +}; > + > +builtin_platform_driver(rockchip_pcie_ep_driver); > diff --git a/drivers/pci/rockchip/pcie-rockchip.c b/drivers/pci/rockchip/pcie-rockchip.c > index d03508c..1d38ad7 100644 > --- a/drivers/pci/rockchip/pcie-rockchip.c > +++ b/drivers/pci/rockchip/pcie-rockchip.c > @@ -29,15 +29,22 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) > struct resource *regs; > int err; > > - regs = platform_get_resource_byname(pdev, > - IORESOURCE_MEM, > - "axi-base"); > - rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); > - if (IS_ERR(rockchip->reg_base)) > - return PTR_ERR(rockchip->reg_base); > - > - regs = platform_get_resource_byname(pdev, > - IORESOURCE_MEM, > + if (rockchip->is_rc) { > + regs = platform_get_resource_byname(pdev, > + IORESOURCE_MEM, > + "axi-base"); > + rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); > + if (IS_ERR(rockchip->reg_base)) > + return PTR_ERR(rockchip->reg_base); > + } else { > + rockchip->mem_res = > + platform_get_resource_byname(pdev, IORESOURCE_MEM, > + "mem-base"); > + if (!rockchip->mem_res) > + return -EINVAL; > + } > + > + regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, > "apb-base"); > rockchip->apb_base = devm_ioremap_resource(dev, regs); > if (IS_ERR(rockchip->apb_base)) > diff --git a/drivers/pci/rockchip/pcie-rockchip.h b/drivers/pci/rockchip/pcie-rockchip.h > index af3e74f..f4bfc22 100644 > --- a/drivers/pci/rockchip/pcie-rockchip.h > +++ b/drivers/pci/rockchip/pcie-rockchip.h > @@ -23,6 +23,9 @@ [...] > +typedef struct rockchip_pcie rockchip_pcie_epc; This typedef has no justification and just obfuscates, please remove it. Thanks, Lorenzo ^ permalink raw reply [flat|nested] 15+ messages in thread
[parent not found: <20180228121120.GC18879-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org>]
* Re: [PATCH v2 5/6] PCI: rockchip: Add Endpoint controller driver for Rockchip PCIe controller [not found] ` <20180228121120.GC18879-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org> @ 2018-03-01 3:45 ` Shawn Lin 0 siblings, 0 replies; 15+ messages in thread From: Shawn Lin @ 2018-03-01 3:45 UTC (permalink / raw) To: Lorenzo Pieralisi Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA, shawn.lin-TNX95d0MmH7DzftRWevZcw, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring, cyrille.pitchen-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, Bjorn Helgaas Dear Lorenzo, On 2018/2/28 20:11, Lorenzo Pieralisi wrote: > [cc: Cyrille] >> + * Bits taken from Cadence endpoint controller driver > > Well, "Bits" is an understatement here; anyway I think this is > a useless comment so I would remove it. Sure. > >> + */ >> + >> +#include <linux/kernel.h> >> +#include <linux/of.h> >> +#include <linux/pci-epc.h> >> +#include <linux/platform_device.h> >> +#include <linux/sizes.h> >> +#include <linux/delay.h> >> +#include <linux/configfs.h> >> +#include <linux/pci-epf.h> > > Nit: Alphabetical order. Sure. > >> +#include "pcie-rockchip.h" >> + >> +/** >> + * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver >> + * @pcie: Rockchip PCIe controller >> + * @data: pointer to a 'struct rockchip_pcie_data' >> + * @ob_region_map: bitmask of mapped outbound regions >> + * @ob_addr: base addresses in the AXI bus where the outbound regions start >> + * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ >> + * dedicated outbound regions is mapped. >> + * @irq_cpu_addr: base address in the CPU space where a write access triggers >> + * the sending of a memory write (MSI) / normal message (legacy >> + * IRQ) TLP through the PCIe bus. >> + * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ >> + * dedicated outbound region. >> + * @irq_pci_fn: the latest PCI function that has updated the mapping of >> + * the MSI/legacy IRQ dedicated outbound region. >> + * @irq_pending: bitmask of asserted legacy IRQs. >> + * @max_regions: maximum number of regions supported by hardware >> + */ >> +struct rockchip_pcie_ep { >> + rockchip_pcie_epc pcie; >> + struct pci_epc *epc; >> + unsigned long ob_region_map; >> + phys_addr_t *ob_addr; >> + phys_addr_t irq_phys_addr; >> + void __iomem *irq_cpu_addr; >> + u64 irq_pci_addr; >> + u8 irq_pci_fn; >> + u8 irq_pending; >> + u32 max_regions; >> +}; >> + > > I think struct cdns_pcie_ep layout (whose content is identical) > is more sensible, follow it. Sure. > >> +void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, >> + u32 r, u32 type, u64 cpu_addr, u64 pci_addr, >> + size_t size, bool is_clr) >> +{ >> + u64 sz = 1ULL << fls64(size - 1); >> + int num_pass_bits = ilog2(sz); >> + u32 addr0, addr1, desc0, desc1; >> + bool is_nor_msg = (type == AXI_WRAPPER_NOR_MSG); >> + >> + if (is_clr) { >> + rockchip_pcie_write(rockchip, 0, >> + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); >> + rockchip_pcie_write(rockchip, 0, >> + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); >> + rockchip_pcie_write(rockchip, 0, >> + ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); >> + rockchip_pcie_write(rockchip, 0, >> + ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); >> + rockchip_pcie_write(rockchip, 0, >> + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r)); >> + rockchip_pcie_write(rockchip, 0, >> + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r)); >> + return; >> + } > > You can split the (is_clr) path in a separate function, say: > > rockchip_pcie_clear_ep_ob_atu() > > it would simplify this one. Okay. > >> + >> + /* The minimal region size is 1MB */ >> + if (num_pass_bits < 8) >> + num_pass_bits = 8; >> + >> + cpu_addr -= rockchip->mem_res->start; >> + addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1)) & >> + PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | >> + (lower_32_bits(cpu_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); >> + addr1 = upper_32_bits(is_nor_msg ? cpu_addr : pci_addr); >> + desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | type; >> + desc1 = 0; >> + >> + if (is_nor_msg) { >> + rockchip_pcie_write(rockchip, 0, >> + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); >> + rockchip_pcie_write(rockchip, 0, >> + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); >> + rockchip_pcie_write(rockchip, desc0, >> + ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); >> + rockchip_pcie_write(rockchip, desc1, >> + ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); >> + } else { >> + /* PCI bus address region */ >> + rockchip_pcie_write(rockchip, addr0, >> + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r)); >> + rockchip_pcie_write(rockchip, addr1, >> + ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r)); >> + rockchip_pcie_write(rockchip, desc0, >> + ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); >> + rockchip_pcie_write(rockchip, desc1, >> + ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); >> + >> + addr0 = >> + ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | >> + (lower_32_bits(cpu_addr) & >> + PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); >> + addr1 = upper_32_bits(cpu_addr); >> + } >> + >> + /* CPU bus address region */ >> + rockchip_pcie_write(rockchip, addr0, >> + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r)); >> + rockchip_pcie_write(rockchip, addr1, >> + ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r)); >> +} >> + >> +static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, >> + struct pci_epf_header *hdr) >> +{ >> + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); >> + struct rockchip_pcie *rockchip = &ep->pcie; >> + >> + /* All functions share the same vendor ID with function 0 */ >> + if (fn == 0) { >> + u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) | >> + (hdr->subsys_vendor_id & GENMASK(31, 16)) << 16; >> + >> + rockchip_pcie_write(rockchip, vid_regs, >> + PCIE_CORE_CONFIG_VENDOR); >> + } >> + >> + rockchip_pcie_write(rockchip, hdr->deviceid << 16, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID); >> + >> + rockchip_pcie_write(rockchip, >> + hdr->revid | >> + hdr->progif_code << 8 | >> + hdr->subclass_code << 16 | >> + hdr->baseclass_code << 24, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_REVISION_ID); >> + rockchip_pcie_write(rockchip, hdr->cache_line_size, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + >> + PCI_CACHE_LINE_SIZE); >> + rockchip_pcie_write(rockchip, hdr->subsys_id << 16, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + >> + PCI_SUBSYSTEM_VENDOR_ID); >> + rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + >> + PCI_INTERRUPT_LINE); >> + >> + return 0; >> + > > Useless empty line. > >> +} >> + >> +static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, >> + enum pci_barno bar, dma_addr_t bar_phys, >> + size_t size, int flags) >> +{ >> + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); >> + struct rockchip_pcie *rockchip = &ep->pcie; >> + u32 addr0, addr1, reg, cfg, b, aperture, ctrl; >> + u64 sz; >> + >> + /* BAR size is 2^(aperture + 7) */ >> + sz = max_t(size_t, size, MIN_EP_APERTURE); >> + >> + /* >> + * roundup_pow_of_two() returns an unsigned long, which is not suited >> + * for 64bit values. >> + */ >> + sz = 1ULL << fls64(sz - 1); >> + aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ >> + >> + if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { >> + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS; >> + } else { >> + bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); >> + bool is_64bits = sz > SZ_2G; >> + >> + if (is_64bits && (bar & 1)) >> + return -EINVAL; >> + >> + if (is_64bits && is_prefetch) >> + ctrl = >> + ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; >> + else if (is_prefetch) >> + ctrl = >> + ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS; >> + else if (is_64bits) >> + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS; >> + else >> + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS; >> + } >> + >> + if (bar < BAR_4) { >> + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn); >> + b = bar; >> + } else { >> + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn); >> + b = bar - BAR_4; >> + } >> + >> + addr0 = lower_32_bits(bar_phys); >> + addr1 = upper_32_bits(bar_phys); >> + >> + cfg = rockchip_pcie_read(rockchip, reg); >> + cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | >> + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); >> + cfg |= (ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) | >> + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); >> + >> + rockchip_pcie_write(rockchip, cfg, reg); >> + rockchip_pcie_write(rockchip, addr0, >> + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar)); >> + rockchip_pcie_write(rockchip, addr1, >> + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar)); >> + >> + return 0; >> +} >> + >> +static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, >> + enum pci_barno bar) >> +{ >> + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); >> + struct rockchip_pcie *rockchip = &ep->pcie; >> + u32 reg, cfg, b, ctrl; >> + >> + if (bar < BAR_4) { >> + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn); >> + b = bar; >> + } else { >> + reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn); >> + b = bar - BAR_4; >> + } >> + >> + ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED; >> + cfg = rockchip_pcie_read(rockchip, reg); >> + cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | >> + ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); >> + cfg |= ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl); >> + >> + rockchip_pcie_write(rockchip, cfg, reg); >> + rockchip_pcie_write(rockchip, 0x0, >> + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar)); >> + rockchip_pcie_write(rockchip, 0x0, >> + ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar)); >> + > > Useless empty line. > >> +} >> + >> +static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, >> + phys_addr_t addr, u64 pci_addr, >> + size_t size) >> +{ >> + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); >> + struct rockchip_pcie *pcie = &ep->pcie; >> + u32 r; >> + >> + r = find_first_zero_bit(&ep->ob_region_map, >> + sizeof(ep->ob_region_map) * BITS_PER_LONG); >> + if (r >= ep->max_regions - 1) { > > Why are we comparing for equality against (max_regions - 1) ? Aren't > we leaving a region out ? > > NB: I know this code is identical to the Cadence driver but copy and > paste is not a good reason for it and if that's a bug it ought to be > fixed in both drivers. > Region 0 is reserved for config space, so it should never be used elsewhere, suggested by TRM. >> + dev_err(&epc->dev, "no free outbound region\n"); >> + return -EINVAL; >> + } >> + >> + rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, AXI_WRAPPER_MEM_WRITE, addr, >> + pci_addr, size, false); >> + >> + set_bit(r, &ep->ob_region_map); >> + ep->ob_addr[r] = addr; >> + >> + return 0; >> + > > Useless empty line. > >> +} >> + >> +static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, >> + phys_addr_t addr) >> +{ >> + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); >> + struct rockchip_pcie *rockchip = &ep->pcie; >> + u32 r; >> + >> + for (r = 0; r < ep->max_regions - 1; r++) >> + if (ep->ob_addr[r] == addr) >> + break; > > See above for max_regions - 1. > >> + >> + if (r == ep->max_regions - 1) >> + return; > > Ditto. > >> + >> + rockchip_pcie_prog_ep_ob_atu(rockchip, 0, 0, 0, 0, 0, 0, true); >> + >> + ep->ob_addr[r] = 0; >> + clear_bit(r, &ep->ob_region_map); >> +} >> + >> +static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, >> + u8 multi_msg_cap) >> +{ >> + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); >> + struct rockchip_pcie *rockchip = &ep->pcie; >> + u16 flags; >> + >> + flags = rockchip_pcie_read(rockchip, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + >> + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); >> + flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK; >> + flags |= >> + ((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | >> + PCI_MSI_FLAGS_64BIT; >> + flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP; >> + rockchip_pcie_write(rockchip, flags, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + >> + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); >> + return 0; >> +} >> + >> +static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) >> +{ >> + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); >> + struct rockchip_pcie *rockchip = &ep->pcie; >> + u16 flags; >> + >> + flags = rockchip_pcie_read(rockchip, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + >> + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); >> + if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME)) >> + return -EINVAL; >> + >> + return ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >> >> + ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET); >> +} >> + >> +static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn, >> + u8 intx, bool is_asserted) >> +{ >> + struct rockchip_pcie *rockchip = &ep->pcie; >> + u32 r = ep->max_regions - 1; >> + u32 offset; >> + u16 status; >> + u8 msg_code; >> + >> + if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR || >> + ep->irq_pci_fn != fn)) { >> + rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r, >> + AXI_WRAPPER_NOR_MSG, >> + ep->irq_phys_addr, 0, 0, false); >> + ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR; >> + ep->irq_pci_fn = fn; >> + } >> + >> + intx &= 3; >> + if (is_asserted) { >> + ep->irq_pending |= BIT(intx); >> + msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx; >> + } else { >> + ep->irq_pending &= ~BIT(intx); >> + msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx; >> + } >> + >> + status = rockchip_pcie_read(rockchip, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + >> + ROCKCHIP_PCIE_EP_CMD_STATUS); >> + status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; >> + >> + if ((status != 0) ^ (ep->irq_pending != 0)) { >> + status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; >> + rockchip_pcie_write(rockchip, status, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + >> + ROCKCHIP_PCIE_EP_CMD_STATUS); >> + } >> + >> + offset = >> + ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) | >> + ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA; >> + writel(0, ep->irq_cpu_addr + offset); >> +} >> + >> +static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn, >> + u8 intx) >> +{ >> + u16 cmd; >> + >> + cmd = rockchip_pcie_read(&ep->pcie, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + >> + ROCKCHIP_PCIE_EP_CMD_STATUS); >> + >> + if (cmd & PCI_COMMAND_INTX_DISABLE) >> + return -EINVAL; >> + >> + rockchip_pcie_ep_assert_intx(ep, fn, intx, true); >> + mdelay(1); > > Is there some HW engineering backing this mdelay() value ? That's a > question for Cadence driver too. Per TRM, It needs vague "small duty cycles" between toggling the INTx depending on the actual AHB bus rate but I just borrowed 1 ms which is sufficent enough. > >> + rockchip_pcie_ep_assert_intx(ep, fn, intx, false); >> + return 0; >> +} >> + >> +static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, >> + u8 interrupt_num) >> +{ >> + struct rockchip_pcie *rockchip = &ep->pcie; >> + u16 flags, mme, data, data_mask; >> + u8 msi_count; >> + u64 pci_addr, pci_addr_mask = 0xff; >> + >> + /* Check MSI enable bit */ >> + flags = rockchip_pcie_read(&ep->pcie, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + >> + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); >> + if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME)) >> + return -EINVAL; >> + >> + /* Get MSI numbers from MME */ >> + mme = ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >> >> + ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET); >> + msi_count = 1 << mme; >> + if (!interrupt_num || interrupt_num > msi_count) >> + return -EINVAL; >> + >> + /* Set MSI private data */ >> + data_mask = msi_count - 1; >> + data = rockchip_pcie_read(rockchip, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + >> + ROCKCHIP_PCIE_EP_MSI_CTRL_REG + >> + PCI_MSI_DATA_64); >> + data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask); >> + >> + /* Get MSI PCI address */ >> + pci_addr = rockchip_pcie_read(rockchip, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + >> + ROCKCHIP_PCIE_EP_MSI_CTRL_REG + >> + PCI_MSI_ADDRESS_HI); >> + pci_addr <<= 32; >> + pci_addr |= rockchip_pcie_read(rockchip, >> + ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + >> + ROCKCHIP_PCIE_EP_MSI_CTRL_REG + >> + PCI_MSI_ADDRESS_LO); >> + pci_addr &= GENMASK_ULL(63, 2); >> + >> + /* Set the outbound region if needed. */ >> + if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) || >> + ep->irq_pci_fn != fn)) { >> + rockchip_pcie_prog_ep_ob_atu(rockchip, fn, ep->max_regions - 1, >> + AXI_WRAPPER_MEM_WRITE, >> + ep->irq_phys_addr, >> + pci_addr & ~pci_addr_mask, >> + pci_addr_mask + 1, false); >> + ep->irq_pci_addr = (pci_addr & ~pci_addr_mask); >> + ep->irq_pci_fn = fn; >> + } >> + >> + writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); >> + return 0; >> +} >> + >> + > > Useless empty line. > >> +static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, >> + enum pci_epc_irq_type type, >> + u8 interrupt_num) >> +{ >> + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); >> + >> + switch (type) { >> + case PCI_EPC_IRQ_LEGACY: >> + return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0); > > Why always INTA (question valid on Cadence driver too) ? See drivers/pci/endpoint/pci-epc-core.c: interrupt_num: the MSI interrupt number I did it because the framework driver, pci_epf_test_raise_irq, always raise INTA. Other value is valid for MSI(NOT X)... > >> + case PCI_EPC_IRQ_MSI: >> + return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num); >> + default: >> + return -EINVAL; >> + } >> +} >> + >> +static int rockchip_pcie_ep_start(struct pci_epc *epc) >> +{ >> + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); >> + struct rockchip_pcie *rockchip = &ep->pcie; >> + struct pci_epf *epf; >> + u32 cfg; >> + >> + cfg = BIT(0); >> + list_for_each_entry(epf, &epc->pci_epf, list) >> + cfg |= BIT(epf->func_no); >> + >> + rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG); >> + >> + list_for_each_entry(epf, &epc->pci_epf, list) >> + pci_epf_linkup(epf); >> + >> + return 0; >> +} >> + >> +static const struct pci_epc_ops rockchip_pcie_epc_ops = { >> + .write_header = rockchip_pcie_ep_write_header, >> + .set_bar = rockchip_pcie_ep_set_bar, >> + .clear_bar = rockchip_pcie_ep_clear_bar, >> + .map_addr = rockchip_pcie_ep_map_addr, >> + .unmap_addr = rockchip_pcie_ep_unmap_addr, >> + .set_msi = rockchip_pcie_ep_set_msi, >> + .get_msi = rockchip_pcie_ep_get_msi, >> + .raise_irq = rockchip_pcie_ep_raise_irq, >> + .start = rockchip_pcie_ep_start, >> +}; >> + >> +/** >> + * rockchip_pcie_parse_dt - Parse Device Tree >> + * @rockchip: PCIe port information > > Missing a parameter. By the way a kerneldoc for this entry does > not seem that useful to me, you can remove it. > >> + * >> + * Return: '0' on success and error value on failure >> + */ >> +static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip, >> + struct rockchip_pcie_ep *ep) >> +{ >> + struct device *dev = rockchip->dev; >> + int err; >> + >> + err = rockchip_pcie_parse_dt(rockchip); >> + if (err) >> + return err; >> + >> + err = rockchip_pcie_get_phys(rockchip); >> + if (err) >> + return err; >> + >> + err = of_property_read_u32(dev->of_node, >> + "rockchip,max-outbound-regions", >> + &ep->max_regions); >> + if (err < 0 || ep->max_regions > MAX_REGION_LIMIT) >> + ep->max_regions = MAX_REGION_LIMIT; >> + >> + err = of_property_read_u8(dev->of_node, "max-functions", >> + &ep->epc->max_functions); >> + if (err < 0) >> + ep->epc->max_functions = 1; >> + >> + return 0; >> +} >> + >> +static const struct of_device_id rockchip_pcie_ep_of_match[] = { >> + { .compatible = "rockchip,rk3399-pcie-ep"}, >> + {}, >> +}; >> + >> +static int rockchip_pcie_ep_probe(struct platform_device *pdev) >> +{ >> + struct device *dev = &pdev->dev; >> + struct rockchip_pcie_ep *ep; >> + rockchip_pcie_epc *rockchip; >> + struct pci_epc *epc; >> + size_t max_regions; >> + int err; >> + >> + ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); >> + if (!ep) >> + return -ENOMEM; >> + >> + platform_set_drvdata(pdev, ep); > > What's this used for ? will remove. > >> + rockchip = &ep->pcie; >> + rockchip->is_rc = false; >> + rockchip->dev = dev; >> + >> + epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops); >> + if (IS_ERR(epc)) { >> + dev_err(dev, "failed to create epc device\n"); >> + return PTR_ERR(epc); >> + } >> + >> + ep->epc = epc; >> + epc_set_drvdata(epc, ep); >> + >> + err = rockchip_pcie_parse_ep_dt(rockchip, ep); >> + if (err) >> + return err; >> + >> + err = rockchip_pcie_enable_clocks(rockchip); >> + if (err) >> + return err; >> + >> + err = rockchip_pcie_init_port(rockchip); >> + if (err) >> + goto err_disable_clocks; >> + >> + /* Establish the link automatically */ >> + rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, >> + PCIE_CLIENT_CONFIG); >> + >> + max_regions = ep->max_regions; >> + ep->ob_addr = devm_kzalloc(dev, max_regions * sizeof(*ep->ob_addr), >> + GFP_KERNEL); >> + >> + if (!ep->ob_addr) { >> + err = -ENOMEM; >> + goto err_uninit_port; >> + } >> + >> + /* Only enable function 0 by default */ >> + rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); >> + >> + > > Useless empty line. > >> + err = pci_epc_mem_init(epc, rockchip->mem_res->start, >> + resource_size(rockchip->mem_res)); >> + if (err < 0) { >> + dev_err(dev, "failed to initialize the memory space\n"); >> + goto err_uninit_port; >> + } >> + >> + ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, >> + SZ_128K); >> + if (!ep->irq_cpu_addr) { >> + dev_err(dev, "failed to reserve memory space for MSI\n"); >> + err = -ENOMEM; >> + goto err_epc_mem_exit; >> + } >> + >> + ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; >> + >> + return 0; >> +err_epc_mem_exit: >> + pci_epc_mem_exit(epc); >> +err_uninit_port: >> + rockchip_pcie_deinit_phys(rockchip); >> +err_disable_clocks: >> + rockchip_pcie_disable_clocks(rockchip); >> + return err; >> +} >> + >> +static struct platform_driver rockchip_pcie_ep_driver = { >> + .driver = { >> + .name = "rockchip-pcie-ep", >> + .of_match_table = rockchip_pcie_ep_of_match, >> + }, >> + .probe = rockchip_pcie_ep_probe, >> +}; >> + >> +builtin_platform_driver(rockchip_pcie_ep_driver); >> diff --git a/drivers/pci/rockchip/pcie-rockchip.c b/drivers/pci/rockchip/pcie-rockchip.c >> index d03508c..1d38ad7 100644 >> --- a/drivers/pci/rockchip/pcie-rockchip.c >> +++ b/drivers/pci/rockchip/pcie-rockchip.c >> @@ -29,15 +29,22 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) >> struct resource *regs; >> int err; >> >> - regs = platform_get_resource_byname(pdev, >> - IORESOURCE_MEM, >> - "axi-base"); >> - rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); >> - if (IS_ERR(rockchip->reg_base)) >> - return PTR_ERR(rockchip->reg_base); >> - >> - regs = platform_get_resource_byname(pdev, >> - IORESOURCE_MEM, >> + if (rockchip->is_rc) { >> + regs = platform_get_resource_byname(pdev, >> + IORESOURCE_MEM, >> + "axi-base"); >> + rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); >> + if (IS_ERR(rockchip->reg_base)) >> + return PTR_ERR(rockchip->reg_base); >> + } else { >> + rockchip->mem_res = >> + platform_get_resource_byname(pdev, IORESOURCE_MEM, >> + "mem-base"); >> + if (!rockchip->mem_res) >> + return -EINVAL; >> + } >> + >> + regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, >> "apb-base"); >> rockchip->apb_base = devm_ioremap_resource(dev, regs); >> if (IS_ERR(rockchip->apb_base)) >> diff --git a/drivers/pci/rockchip/pcie-rockchip.h b/drivers/pci/rockchip/pcie-rockchip.h >> index af3e74f..f4bfc22 100644 >> --- a/drivers/pci/rockchip/pcie-rockchip.h >> +++ b/drivers/pci/rockchip/pcie-rockchip.h >> @@ -23,6 +23,9 @@ > > [...] > >> +typedef struct rockchip_pcie rockchip_pcie_epc; > > This typedef has no justification and just obfuscates, please remove it. > Done. > Thanks, > Lorenzo > > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 6/6] dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe endpoint controller [not found] ` <1519348503-243259-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> ` (4 preceding siblings ...) 2018-02-23 1:17 ` [PATCH v2 5/6] PCI: rockchip: Add Endpoint controller driver for Rockchip PCIe controller Shawn Lin @ 2018-02-23 1:17 ` Shawn Lin 5 siblings, 0 replies; 15+ messages in thread From: Shawn Lin @ 2018-02-23 1:17 UTC (permalink / raw) To: Bjorn Helgaas, Lorenzo Pieralisi Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Heiko Stuebner, linux-pci-u79uwXL29TY76Z2rM5mHXA, Shawn Lin, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring This patch documents the DT bindings for the Rockchip PCIe controller when configured in endpoint mode. Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> --- Changes in v2: None .../devicetree/bindings/pci/rockchip-pcie-ep.txt | 62 ++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt new file mode 100644 index 0000000..77846730 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt @@ -0,0 +1,62 @@ +* Rockchip AXI PCIe Endpoint Controller DT description + +Required properties: +- compatible: Should contain "rockchip,rk3399-pcie-ep" +- reg: Two register ranges as listed in the reg-names property +- reg-names: Must include the following names + - "apb-base" + - "mem-base" +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - "aclk" + - "aclk-perf" + - "hclk" + - "pm" +- resets: Must contain seven entries for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following names + - "core" + - "mgmt" + - "mgmt-sticky" + - "pipe" + - "pm" + - "aclk" + - "pclk" +- pinctrl-names : The pin control state names +- pinctrl-0: The "default" pinctrl state +- phys: Must contain an phandle to a PHY for each entry in phy-names. +- phy-names: Must include 4 entries for all 4 lanes even if some of + them won't be used for your cases. Entries are of the form "pcie-phy-N": + where N ranges from 0 to 3. + (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt + for changing the #phy-cells of phy node to support it) +- rockchip,max-outbound-regions: Maximum number of outbound regions + +Optional Property: +- num-lanes: number of lanes to use +- max-functions: Maximum number of functions that can be configured (default 1). + +pcie0-ep: pcie@f8000000 { + compatible = "rockchip,rk3399-pcie-ep"; + #address-cells = <3>; + #size-cells = <2>; + rockchip,max-outbound-regions = <16>; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; + max-functions = /bits/ 8 <8>; + num-lanes = <4>; + reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>; + reg-names = "apb-base", "mem-base"; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; + phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; + phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq>; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-03-02 15:10 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
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2018-02-23 1:15 [PATCH v2 0/6] Add endpoint driver for Rockchip PCIe controller Shawn Lin
[not found] ` <1519348503-243259-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2018-02-23 1:15 ` [PATCH v2 1/6] PCI: rockchip: Create individual folder for rockchip drivers Shawn Lin
2018-02-23 1:16 ` [PATCH v2 2/6] PCI: rockchip: Split out common function to parse DT Shawn Lin
2018-02-23 1:16 ` [PATCH v2 3/6] PCI: rockchip: Spilt out common function to init controller Shawn Lin
[not found] ` <1519348606-243485-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2018-02-25 0:51 ` [v2, " JeffyChen
2018-02-27 11:29 ` [PATCH v2 " Lorenzo Pieralisi
2018-02-23 1:17 ` [PATCH v2 4/6] dt-bindings: PCI: rockchip: Rename rockchip-pcie.txt to rockchip-pcie-host.txt Shawn Lin
[not found] ` <1519348623-243549-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2018-03-02 15:10 ` Rob Herring
2018-02-23 1:17 ` [PATCH v2 5/6] PCI: rockchip: Add Endpoint controller driver for Rockchip PCIe controller Shawn Lin
[not found] ` <1519348654-243597-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2018-02-27 15:32 ` Lorenzo Pieralisi
[not found] ` <20180227153202.GB7184-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org>
2018-02-28 1:40 ` Shawn Lin
[not found] ` <8244c52c-73d3-5b20-eb39-ddc37968163a-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2018-02-28 11:22 ` Lorenzo Pieralisi
2018-02-28 12:11 ` Lorenzo Pieralisi
[not found] ` <20180228121120.GC18879-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org>
2018-03-01 3:45 ` Shawn Lin
2018-02-23 1:17 ` [PATCH v2 6/6] dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe endpoint controller Shawn Lin
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