[PATCH 0/5] Optimization with aware of cpu capacity for R-Car Gen3

[PATCH 0/5] Optimization with aware of cpu capacity for R-Car Gen3

[Gaku Inami]

These add the scheduler information to be aware cpu capacity. Some
R-Car SoCs have big LITTLE architecture(e.g. CA57/CA53). It has a
difference performance/power consumption for each CPUs.

As the scheduler will be aware the capacity of CPU, the scheduler is
balancing so that the free capacity of each CPU is even. This means
that it aggressively migrates tasks to big CPUs(e.g. CA57) with large
capacity in case of the system load is low and middle, the performance
of user application is improved than before.

Since most users for IVI are using CPU with performance oriented than
power consumption, this change will benefit for their use-cases. Some
benchmark is improved as an example below.

UnixBench (1 parallel) on R-Car M3-W (CA57x2 + CA53x4) :
                                            before      after
 - Dhrystone 2 using register variables    9197952   15534005   +68%
 - Double-Precision Whetstone                 1390       1697   +22%
 - Execl Throughput                            621       1189   +91%
 - File Copy 1024 bufsize 2000 maxblocks     81755     138840   +69%
 - File Copy 256 bufsize 500 maxblocks       25819      40125   +55%
 - File Copy 4096 bufsize 8000 maxblocks    212116     384956   +81%
 - Pipe Throughput                          133006     232866   +75%
 - Pipe-based Context Switching              23973      46271   +93%
 - Process Creation                           1085       2253  +107%
 - Shell Scripts (1 concurrent)                682       1003   +47%
 - Shell Scripts (8 concurrent)                261        319   +22%
 - System Call Overhead                     107912     193681   +79%
 - System Benchmarks Index Score               177        293   +65%

UnixBench (8 parallel) on R-Car H3 (CA57x4 + CA53x4) :
                                            before      after
 - Dhrystone 2 using register variables   86830146   86498236     0%
 - Double-Precision Whetstone                11640      11783    +1%
 - Execl Throughput                           4196       4207     0%
 - File Copy 1024 bufsize 2000 maxblocks    122995     127868    +3%
 - File Copy 256 bufsize 500 maxblocks       32339      30683    -6%
 - File Copy 4096 bufsize 8000 maxblocks    312526     421738   +34%
 - Pipe Throughput                          904408     896829    -1%
 - Pipe-based Context Switching             136409     122969   -10%
 - Process Creation                           5877       5712    -3%
 - Shell Scripts (1 concurrent)               3533       3279    -7%
 - Shell Scripts (8 concurrent)                467        465     0%
 - System Call Overhead                     738344     735697     0%
 - System Benchmarks Index Score               718        721     0%

based on renesas-devel-20180212-v4.16-rc1

Gaku Inami (5):
  arm64: dts: renesas: r8a7795: Add multi-cluster definition
  arm64: dts: renesas: r8a7796: Add multi-cluster definition
  arm64: dts: renesas: r8a7795: Add cpu capacity-dmips-mhz
  arm64: dts: renesas: r8a7796: Add cpu capacity-dmips-mhz
  soc: renesas: rcar-topology: Add support to be aware cpu capacity

 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 40 ++++++++++++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 32 +++++++++++++++++++++++++
 drivers/soc/renesas/Kconfig              |  4 ++++
 drivers/soc/renesas/Makefile             |  1 +
 drivers/soc/renesas/rcar-topology.c      | 36 ++++++++++++++++++++++++++++
 5 files changed, 113 insertions(+)
 create mode 100644 drivers/soc/renesas/rcar-topology.c

-- 
2.7.4

[PATCH 1/5] arm64: dts: renesas: r8a7795: Add multi-cluster definition

[Gaku Inami]

This patch adds the "cpu-map" for multi-cluster into r8a7795
device-tree. This definition is used to parse the cpu topology.

Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index ce85704..ffcc91e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -34,6 +34,38 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&a57_0>;
+				};
+				core1 {
+					cpu = <&a57_1>;
+				};
+				core2 {
+					cpu = <&a57_2>;
+				};
+				core3 {
+					cpu = <&a57_3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&a53_0>;
+				};
+				core1 {
+					cpu = <&a53_1>;
+				};
+				core2 {
+					cpu = <&a53_2>;
+				};
+				core3 {
+					cpu = <&a53_3>;
+				};
+			};
+		};
+
 		a57_0: cpu@0 {
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x0>;
-- 
2.7.4

Re: [PATCH 1/5] arm64: dts: renesas: r8a7795: Add multi-cluster definition

[Geert Uytterhoeven]

On Tue, Feb 27, 2018 at 3:19 AM, Gaku Inami <gaku.inami.xh@renesas.com> wrote:
> This patch adds the "cpu-map" for multi-cluster into r8a7795
> device-tree. This definition is used to parse the cpu topology.
>
> Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 2/5] arm64: dts: renesas: r8a7796: Add multi-cluster definition

[Gaku Inami]

This patch adds the "cpu-map" for multi-cluster into r8a7796
device-tree. This definition is used to parse the cpu topology.

Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index f8e9313..154df9b 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -64,6 +64,32 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&a57_0>;
+				};
+				core1 {
+					cpu = <&a57_1>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&a53_0>;
+				};
+				core1 {
+					cpu = <&a53_1>;
+				};
+				core2 {
+					cpu = <&a53_2>;
+				};
+				core3 {
+					cpu = <&a53_3>;
+				};
+			};
+		};
+
 		a57_0: cpu@0 {
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x0>;
-- 
2.7.4

Re: [PATCH 2/5] arm64: dts: renesas: r8a7796: Add multi-cluster definition

[Geert Uytterhoeven]

On Tue, Feb 27, 2018 at 3:19 AM, Gaku Inami <gaku.inami.xh@renesas.com> wrote:
> This patch adds the "cpu-map" for multi-cluster into r8a7796
> device-tree. This definition is used to parse the cpu topology.
>
> Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 3/5] arm64: dts: renesas: r8a7795: Add cpu capacity-dmips-mhz

[Gaku Inami]

Set the capacity-dmips-mhz for r8a7795, that is based on dhrystone.

Expected cpu capacity:
Cortex-A57@1.5GHz: 1024, Cortex-A53@1.2GHz: 411

Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index ffcc91e..be15864 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -75,6 +75,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
+			capacity-dmips-mhz = <1024>;
 			#cooling-cells = <2>;
 		};
 
@@ -87,6 +88,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
+			capacity-dmips-mhz = <1024>;
 			#cooling-cells = <2>;
 		};
 
@@ -99,6 +101,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
+			capacity-dmips-mhz = <1024>;
 			#cooling-cells = <2>;
 		};
 
@@ -111,6 +114,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
+			capacity-dmips-mhz = <1024>;
 			#cooling-cells = <2>;
 		};
 
@@ -123,6 +127,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
+			capacity-dmips-mhz = <411>;
 		};
 
 		a53_1: cpu@101 {
@@ -134,6 +139,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
+			capacity-dmips-mhz = <411>;
 		};
 
 		a53_2: cpu@102 {
@@ -145,6 +151,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
+			capacity-dmips-mhz = <411>;
 		};
 
 		a53_3: cpu@103 {
@@ -156,6 +163,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
+			capacity-dmips-mhz = <411>;
 		};
 
 		L2_CA57: cache-controller-0 {
-- 
2.7.4

Re: [PATCH 3/5] arm64: dts: renesas: r8a7795: Add cpu capacity-dmips-mhz

[Geert Uytterhoeven]

Hi Inami-san,

On Tue, Feb 27, 2018 at 3:19 AM, Gaku Inami <gaku.inami.xh@renesas.com> wrote:
> Set the capacity-dmips-mhz for r8a7795, that is based on dhrystone.
>
> Expected cpu capacity:
> Cortex-A57@1.5GHz: 1024, Cortex-A53@1.2GHz: 411

Thanks for your patch!

> Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

411 for the A53 cores sounds a bit low to me, though.
Documentation/devicetree/bindings/arm/cpu-capacity.txt uses 578.

Perhaps you already took into account the maximum clock frequencies?
According to the binding document, you should not do that (cfr.
"final capacities are 1024 for cluster0 and 446 for cluster1" in the
bindings doc).

> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -123,6 +127,7 @@
>                         enable-method = "psci";
>                         clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
>                         operating-points-v2 = <&cluster1_opp>;
> +                       capacity-dmips-mhz = <411>;
>                 };

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 3/5] arm64: dts: renesas: r8a7795: Add cpu capacity-dmips-mhz

[Gaku Inami]

Hi Geert-san,

> -----Original Message-----
> From: geert.uytterhoeven@gmail.com [mailto:geert.uytterhoeven@gmail.com] On Behalf Of Geert Uytterhoeven
> Sent: Monday, March 5, 2018 7:24 PM
[snip]
>
> 411 for the A53 cores sounds a bit low to me, though.
> Documentation/devicetree/bindings/arm/cpu-capacity.txt uses 578.
> 
> Perhaps you already took into account the maximum clock frequencies?
> According to the binding document, you should not do that (cfr.
> "final capacities are 1024 for cluster0 and 446 for cluster1" in the
> bindings doc).

Thanks for your review.

I set 411 for CA53 based on dhrystone measurement and current implementation.

The average in 10 times of measurement as follows:

  cpu   max-freq   dhrystone
  ---------------------------------
  A57   1500 MHz  15532585 lps/s
  A53   1200 MHz   6241541 lps/s

With the value of CA57 is scaled at 1024, I end up with 411 for CA53. 
However, since cpufreq is not available on renesas-devel-20180212-v4.16-rc1,
the final capacity is set by directly using capacity-dmips-mhz in dt as below.

  $ cat /sys/devices/system/cpu/cpu*/cpu_capacity
  1024
  1024
  1024
  1024
  411
  411
  411
  411

Considering cpufreq is available later, is it better to set the value(514)
for CA53 scaled by different maximum frequencies?

Regards,
Inami

Re: [PATCH 3/5] arm64: dts: renesas: r8a7795: Add cpu capacity-dmips-mhz

[Geert Uytterhoeven]

Hi Inami-san,

On Wed, Mar 7, 2018 at 2:48 AM, Gaku Inami <gaku.inami.xh@renesas.com> wrote:
>> From: geert.uytterhoeven@gmail.com [mailto:geert.uytterhoeven@gmail.com] On Behalf Of Geert Uytterhoeven
>> Sent: Monday, March 5, 2018 7:24 PM
> [snip]
>>
>> 411 for the A53 cores sounds a bit low to me, though.
>> Documentation/devicetree/bindings/arm/cpu-capacity.txt uses 578.
>>
>> Perhaps you already took into account the maximum clock frequencies?
>> According to the binding document, you should not do that (cfr.
>> "final capacities are 1024 for cluster0 and 446 for cluster1" in the
>> bindings doc).
>
> Thanks for your review.
>
> I set 411 for CA53 based on dhrystone measurement and current implementation.
>
> The average in 10 times of measurement as follows:
>
>   cpu   max-freq   dhrystone
>   ---------------------------------
>   A57   1500 MHz  15532585 lps/s
>   A53   1200 MHz   6241541 lps/s
>
> With the value of CA57 is scaled at 1024, I end up with 411 for CA53.
> However, since cpufreq is not available on renesas-devel-20180212-v4.16-rc1,
> the final capacity is set by directly using capacity-dmips-mhz in dt as below.

Documentation/devicetree/bindings/arm/cpu-capacity.txt:

"capacity-dmips-mhz is an optional cpu node [1] property: u32 value
 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
 maximum frequency available to the cpu is then used to calculate the capacity
 value internally used by the kernel."

IIUIC, you should thus not use 15532585 and 6241541 directly, but
scale them to the frequency.

So the formula for CA53 becomes:

1024 / (15532585 / 1500) * (6241541 / 1200) = 514

> Considering cpufreq is available later, is it better to set the value(514)
> for CA53 scaled by different maximum frequencies?

DT describes the hardware, not software limitations, so IMHO 514 is the correct
value.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/5] arm64: dts: renesas: r8a7795: Add cpu capacity-dmips-mhz

[Simon Horman]

On Wed, Mar 07, 2018 at 08:47:43AM +0100, Geert Uytterhoeven wrote:
> Hi Inami-san,
> 
> On Wed, Mar 7, 2018 at 2:48 AM, Gaku Inami <gaku.inami.xh@renesas.com> wrote:
> >> From: geert.uytterhoeven@gmail.com [mailto:geert.uytterhoeven@gmail.com] On Behalf Of Geert Uytterhoeven
> >> Sent: Monday, March 5, 2018 7:24 PM
> > [snip]
> >>
> >> 411 for the A53 cores sounds a bit low to me, though.
> >> Documentation/devicetree/bindings/arm/cpu-capacity.txt uses 578.
> >>
> >> Perhaps you already took into account the maximum clock frequencies?
> >> According to the binding document, you should not do that (cfr.
> >> "final capacities are 1024 for cluster0 and 446 for cluster1" in the
> >> bindings doc).
> >
> > Thanks for your review.
> >
> > I set 411 for CA53 based on dhrystone measurement and current implementation.
> >
> > The average in 10 times of measurement as follows:
> >
> >   cpu   max-freq   dhrystone
> >   ---------------------------------
> >   A57   1500 MHz  15532585 lps/s
> >   A53   1200 MHz   6241541 lps/s
> >
> > With the value of CA57 is scaled at 1024, I end up with 411 for CA53.
> > However, since cpufreq is not available on renesas-devel-20180212-v4.16-rc1,
> > the final capacity is set by directly using capacity-dmips-mhz in dt as below.
> 
> Documentation/devicetree/bindings/arm/cpu-capacity.txt:
> 
> "capacity-dmips-mhz is an optional cpu node [1] property: u32 value
>  representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
>  maximum frequency available to the cpu is then used to calculate the capacity
>  value internally used by the kernel."
> 
> IIUIC, you should thus not use 15532585 and 6241541 directly, but
> scale them to the frequency.
> 
> So the formula for CA53 becomes:
> 
> 1024 / (15532585 / 1500) * (6241541 / 1200) = 514
> 
> > Considering cpufreq is available later, is it better to set the value(514)
> > for CA53 scaled by different maximum frequencies?
> 
> DT describes the hardware, not software limitations, so IMHO 514 is the correct
> value.

Yes agreed. Please refresh this patchset accordingly.

RE: [PATCH 3/5] arm64: dts: renesas: r8a7795: Add cpu capacity-dmips-mhz

[Gaku Inami]

Hi Geert-san, Simon-san,

> -----Original Message-----
> From: linux-renesas-soc-owner@vger.kernel.org [mailto:linux-renesas-soc-owner@vger.kernel.org] On Behalf Of Simon
> Horman
> Sent: Wednesday, March 7, 2018 5:11 PM
[snip]
> >
> > Documentation/devicetree/bindings/arm/cpu-capacity.txt:
> >
> > "capacity-dmips-mhz is an optional cpu node [1] property: u32 value
> >  representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
> >  maximum frequency available to the cpu is then used to calculate the capacity
> >  value internally used by the kernel."
> >
> > IIUIC, you should thus not use 15532585 and 6241541 directly, but
> > scale them to the frequency.
> >
> > So the formula for CA53 becomes:
> >
> > 1024 / (15532585 / 1500) * (6241541 / 1200) = 514
> >
> > > Considering cpufreq is available later, is it better to set the value(514)
> > > for CA53 scaled by different maximum frequencies?
> >
> > DT describes the hardware, not software limitations, so IMHO 514 is the correct
> > value.

Sorry, I misunderstood the intention of definition in DT.
Thanks for your detailed explanation. I understood it.

> Yes agreed. Please refresh this patchset accordingly.

I will update v2 patch.

Regards,
Inami

[PATCH 4/5] arm64: dts: renesas: r8a7796: Add cpu capacity-dmips-mhz

[Gaku Inami]

Set the capacity-dmips-mhz for r8a7796, that is based on dhrystone.

Expected cpu capacity:
Cortex-A57@1.5Ghz: 1024, Cortex-A53@1.2GHz: 411

Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 154df9b..a776d29 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -99,6 +99,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
+			capacity-dmips-mhz = <1024>;
 			#cooling-cells = <2>;
 		};
 
@@ -111,6 +112,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
+			capacity-dmips-mhz = <1024>;
 			#cooling-cells = <2>;
 		};
 
@@ -123,6 +125,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
+			capacity-dmips-mhz = <411>;
 		};
 
 		a53_1: cpu@101 {
@@ -134,6 +137,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
+			capacity-dmips-mhz = <411>;
 		};
 
 		a53_2: cpu@102 {
@@ -145,6 +149,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
+			capacity-dmips-mhz = <411>;
 		};
 
 		a53_3: cpu@103 {
@@ -156,6 +161,7 @@
 			enable-method = "psci";
 			clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
+			capacity-dmips-mhz = <411>;
 		};
 
 		L2_CA57: cache-controller-0 {
-- 
2.7.4

Re: [PATCH 4/5] arm64: dts: renesas: r8a7796: Add cpu capacity-dmips-mhz

[Geert Uytterhoeven]

Hi Inami-san,

On Tue, Feb 27, 2018 at 3:19 AM, Gaku Inami <gaku.inami.xh@renesas.com> wrote:
> Set the capacity-dmips-mhz for r8a7796, that is based on dhrystone.
>
> Expected cpu capacity:
> Cortex-A57@1.5Ghz: 1024, Cortex-A53@1.2GHz: 411

Thanks for your patch!

> Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

But same comment as for r8a7795.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 5/5] soc: renesas: rcar-topology: Add support to be aware cpu capacity

[Gaku Inami]

Some R-Car SoCs support big LITTLE architecture produced by ARM, that
have different power/performance characteristics between each CPUs.
In order to aware such as difference, this patch changes the sched
domain flags that the tasks can be scheduled with capacity awareness.
If you use big LITTLE without this patch, the scheduler may make
unintended behaviors.

Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com>
---
 drivers/soc/renesas/Kconfig         |  4 ++++
 drivers/soc/renesas/Makefile        |  1 +
 drivers/soc/renesas/rcar-topology.c | 36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 41 insertions(+)
 create mode 100644 drivers/soc/renesas/rcar-topology.c

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 6efd7be..296bdee 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -16,6 +16,7 @@ config SOC_RENESAS
 	select SYSC_R8A7796 if ARCH_R8A7796
 	select SYSC_R8A77970 if ARCH_R8A77970
 	select SYSC_R8A77995 if ARCH_R8A77995
+	select RCAR_CPU_TOPOLOGY if ARCH_R8A7795 || ARCH_R8A7796
 
 if SOC_RENESAS
 
@@ -71,4 +72,7 @@ config RST_RCAR
 config SYSC_RCAR
 	bool "R-Car System Controller support" if COMPILE_TEST
 
+config RCAR_CPU_TOPOLOGY
+	bool "R-Car CPU Topology" if COMPILE_TEST
+
 endif # SOC_RENESAS
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 845d62a..244f243 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_SYSC_R8A77995)	+= r8a77995-sysc.o
 # Family
 obj-$(CONFIG_RST_RCAR)		+= rcar-rst.o
 obj-$(CONFIG_SYSC_RCAR)		+= rcar-sysc.o
+obj-$(CONFIG_RCAR_CPU_TOPOLOGY)	+= rcar-topology.o
diff --git a/drivers/soc/renesas/rcar-topology.c b/drivers/soc/renesas/rcar-topology.c
new file mode 100644
index 0000000..7e941cf
--- /dev/null
+++ b/drivers/soc/renesas/rcar-topology.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  R-Car CPU topology for ARM big.LITTLE platforms
+ *
+ * Copyright (C) 2018 Renesas Electronics Corporation.
+ *
+ */
+
+#include <linux/cpuset.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/sched/topology.h>
+#include <linux/topology.h>
+
+static int rcar_cpu_cpu_flags(void)
+{
+	return SD_ASYM_CPUCAPACITY;
+}
+
+static struct sched_domain_topology_level rcar_topology[] = {
+#ifdef CONFIG_SCHED_MC
+	{ cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
+#endif
+	{ cpu_cpu_mask, rcar_cpu_cpu_flags, SD_INIT_NAME(DIE) },
+	{ NULL, }
+};
+
+static int __init rcar_topology_init(void)
+{
+	if (of_machine_is_compatible("renesas,r8a7795") ||
+	    of_machine_is_compatible("renesas,r8a7796"))
+		set_sched_topology(rcar_topology);
+
+	return 0;
+}
+early_initcall(rcar_topology_init);
-- 
2.7.4

Re: [PATCH 5/5] soc: renesas: rcar-topology: Add support to be aware cpu capacity

[Geert Uytterhoeven]

Hi Inami-san,

On Tue, Feb 27, 2018 at 3:19 AM, Gaku Inami <gaku.inami.xh@renesas.com> wrote:
> Some R-Car SoCs support big LITTLE architecture produced by ARM, that
> have different power/performance characteristics between each CPUs.
> In order to aware such as difference, this patch changes the sched
> domain flags that the tasks can be scheduled with capacity awareness.
> If you use big LITTLE without this patch, the scheduler may make
> unintended behaviors.
>
> Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/drivers/soc/renesas/rcar-topology.c
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + *  R-Car CPU topology for ARM big.LITTLE platforms
> + *
> + * Copyright (C) 2018 Renesas Electronics Corporation.
> + *
> + */
> +
> +#include <linux/cpuset.h>
> +#include <linux/init.h>
> +#include <linux/of.h>
> +#include <linux/sched/topology.h>
> +#include <linux/topology.h>
> +
> +static int rcar_cpu_cpu_flags(void)
> +{
> +       return SD_ASYM_CPUCAPACITY;
> +}
> +
> +static struct sched_domain_topology_level rcar_topology[] = {
> +#ifdef CONFIG_SCHED_MC
> +       { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
> +#endif
> +       { cpu_cpu_mask, rcar_cpu_cpu_flags, SD_INIT_NAME(DIE) },
> +       { NULL, }
> +};
> +
> +static int __init rcar_topology_init(void)
> +{
> +       if (of_machine_is_compatible("renesas,r8a7795") ||
> +           of_machine_is_compatible("renesas,r8a7796"))
> +               set_sched_topology(rcar_topology);
> +
> +       return 0;
> +}
> +early_initcall(rcar_topology_init);

None of the above seems R-Car specific to me. So please explain why this
can't just be added to arch/arm64/kernel/topology.c instead, and enabled
unconditionally.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 5/5] soc: renesas: rcar-topology: Add support to be aware cpu capacity

[Gaku Inami]

Hi Geert-san,

> -----Original Message-----
> From: geert.uytterhoeven@gmail.com [mailto:geert.uytterhoeven@gmail.com] On Behalf Of Geert Uytterhoeven

[snip]

> None of the above seems R-Car specific to me. So please explain why this
> can't just be added to arch/arm64/kernel/topology.c instead, and enabled
> unconditionally.

Thanks for your feedback.

As you said, this code should not be R-Car specific. I will consider again
that it enables SD_ASYM_CPUCAPACITY unconditionally.

Regards,
Inami