* [PATCH v3 01/13] firmware: qcom: scm: Add ipq4019 soc compatible
2018-03-20 3:58 [PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals Sricharan R
@ 2018-03-20 3:58 ` Sricharan R
2018-03-20 3:58 ` [PATCH v3 02/13] ARM: dts: ipq4019: Add a few peripheral nodes Sricharan R
` (11 subsequent siblings)
12 siblings, 0 replies; 35+ messages in thread
From: Sricharan R @ 2018-03-20 3:58 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
Cc: sricharan
Add the compatible for ipq4019.
This does not need clocks to do scm calls.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++-
drivers/firmware/qcom_scm.c | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index 7b40054..fcf6979 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -11,9 +11,10 @@ Required properties:
* "qcom,scm-msm8660" for MSM8660 platforms
* "qcom,scm-msm8690" for MSM8690 platforms
* "qcom,scm-msm8996" for MSM8996 platforms
+ * "qcom,scm-ipq4019" for IPQ4019 platforms
* "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
- clocks: One to three clocks may be required based on compatible.
- * No clock required for "qcom,scm-msm8996"
+ * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"
* Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"
* Core, iface, and bus clocks required for "qcom,scm"
- clock-names: Must contain "core" for the core clock, "iface" for the interface
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 5a7d6930..e778af7 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -603,6 +603,9 @@ static void qcom_scm_shutdown(struct platform_device *pdev)
{ .compatible = "qcom,scm-msm8996",
.data = NULL, /* no clocks */
},
+ { .compatible = "qcom,scm-ipq4019",
+ .data = NULL, /* no clocks */
+ },
{ .compatible = "qcom,scm",
.data = (void *)(SCM_HAS_CORE_CLK
| SCM_HAS_IFACE_CLK
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH v3 02/13] ARM: dts: ipq4019: Add a few peripheral nodes
2018-03-20 3:58 [PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals Sricharan R
2018-03-20 3:58 ` [PATCH v3 01/13] firmware: qcom: scm: Add ipq4019 soc compatible Sricharan R
@ 2018-03-20 3:58 ` Sricharan R
2018-03-20 3:58 ` [PATCH v3 03/13] ARM: dts: ipq4019: Change the max opp frequency Sricharan R
` (10 subsequent siblings)
12 siblings, 0 replies; 35+ messages in thread
From: Sricharan R @ 2018-03-20 3:58 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
Cc: sricharan
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 ++++++++++++++++++++++++++++++++++++
1 file changed, 134 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 10d112a..3a7127c 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -25,7 +25,9 @@
aliases {
spi0 = &spi_0;
+ spi1 = &spi_1;
i2c0 = &i2c_0;
+ i2c1 = &i2c_1;
};
cpus {
@@ -104,6 +106,12 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq4019";
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -172,6 +180,22 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&blsp_dma 5>, <&blsp_dma 4>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x78b6000 0x600>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&blsp_dma 7>, <&blsp_dma 6>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -184,9 +208,24 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
+ dma-names = "rx", "tx";
status = "disabled";
};
+ i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x78b8000 0x600>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&blsp_dma 11>, <&blsp_dma 10>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
cryptobam: dma@8e04000 {
compatible = "qcom,bam-v1.7.0";
@@ -293,6 +332,101 @@
reg = <0x4ab000 0x4>;
};
+ pcie0: pci@40000000 {
+ compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+ reg = <0x40000000 0xf1d
+ 0x40000f20 0xa8
+ 0x80000 0x2000
+ 0x40100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
+ 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ clocks = <&gcc GCC_PCIE_AHB_CLK>,
+ <&gcc GCC_PCIE_AXI_M_CLK>,
+ <&gcc GCC_PCIE_AXI_S_CLK>;
+ clock-names = "aux",
+ "master_bus",
+ "slave_bus";
+
+ resets = <&gcc PCIE_AXI_M_ARES>,
+ <&gcc PCIE_AXI_S_ARES>,
+ <&gcc PCIE_PIPE_ARES>,
+ <&gcc PCIE_AXI_M_VMIDMT_ARES>,
+ <&gcc PCIE_AXI_S_XPU_ARES>,
+ <&gcc PCIE_PARF_XPU_ARES>,
+ <&gcc PCIE_PHY_ARES>,
+ <&gcc PCIE_AXI_M_STICKY_ARES>,
+ <&gcc PCIE_PIPE_STICKY_ARES>,
+ <&gcc PCIE_PWR_ARES>,
+ <&gcc PCIE_AHB_ARES>,
+ <&gcc PCIE_PHY_AHB_ARES>;
+ reset-names = "axi_m",
+ "axi_s",
+ "pipe",
+ "axi_m_vmid",
+ "axi_s_xpu",
+ "parf",
+ "phy",
+ "axi_m_sticky",
+ "pipe_sticky",
+ "pwr",
+ "ahb",
+ "phy_ahb";
+
+ status = "disabled";
+ };
+
+ qpic_bam: dma@7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7984000 0x1a000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ nand: qpic-nand@79b0000 {
+ compatible = "qcom,ipq4019-nand";
+ reg = <0x79b0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ status = "disabled";
+
+ nand@0 {
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+ };
+
wifi0: wifi@a000000 {
compatible = "qcom,ipq4019-wifi";
reg = <0xa000000 0x200000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH v3 03/13] ARM: dts: ipq4019: Change the max opp frequency
2018-03-20 3:58 [PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals Sricharan R
2018-03-20 3:58 ` [PATCH v3 01/13] firmware: qcom: scm: Add ipq4019 soc compatible Sricharan R
2018-03-20 3:58 ` [PATCH v3 02/13] ARM: dts: ipq4019: Add a few peripheral nodes Sricharan R
@ 2018-03-20 3:58 ` Sricharan R
2018-03-20 3:58 ` [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data Sricharan R
` (9 subsequent siblings)
12 siblings, 0 replies; 35+ messages in thread
From: Sricharan R @ 2018-03-20 3:58 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
Cc: sricharan
The max opp frequency is 716MHZ. So update that.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 3a7127c..e87e825 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -47,7 +47,7 @@
48000 1100000
200000 1100000
500000 1100000
- 666000 1100000
+ 716000 1100000
>;
clock-latency = <256000>;
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-03-20 3:58 [PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals Sricharan R
` (2 preceding siblings ...)
2018-03-20 3:58 ` [PATCH v3 03/13] ARM: dts: ipq4019: Change the max opp frequency Sricharan R
@ 2018-03-20 3:58 ` Sricharan R
2018-03-20 7:33 ` Stephen Boyd
2018-03-20 14:31 ` Richard Cochran
2018-03-20 3:58 ` [PATCH v3 05/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi Sricharan R
` (8 subsequent siblings)
12 siblings, 2 replies; 35+ messages in thread
From: Sricharan R @ 2018-03-20 3:58 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
Cc: sricharan
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Adds missing memory, reserved-memory nodes.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ad0fbc9 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,34 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256MB */
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd1@87000000 {
+ /* Reserved for other subsystem */
+ reg = <0x87000000 0x500000>;
+ no-map;
+ };
+
+ wifi_dump@87500000 {
+ reg = <0x87500000 0x600000>;
+ no-map;
+ };
+
+ rsvd2@87B00000 {
+ /* Reserved for other subsystem */
+ reg = <0x87B00000 0x500000>;
+ no-map;
+ };
+ };
+
soc {
rng@22000 {
status = "ok";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-03-20 3:58 ` [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data Sricharan R
@ 2018-03-20 7:33 ` Stephen Boyd
2018-03-20 11:45 ` sricharan
2018-03-20 14:31 ` Richard Cochran
1 sibling, 1 reply; 35+ messages in thread
From: Stephen Boyd @ 2018-03-20 7:33 UTC (permalink / raw)
To: absahu, andy.gross, bjorn.andersson, catalin.marinas, david.brown,
devicetree, linux-arm-kernel, linux-arm-msm, linux-kernel,
linux-soc, linux, marc.zyngier, mark.rutland, robh+dt, robh,
sboyd, will.deacon
Cc: sricharan
Quoting Sricharan R (2018-03-19 20:58:47)
> Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
That is an odd place for a reviewed-by tag.
> Adds missing memory, reserved-memory nodes.
>
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> ---
> arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
> index e413b21e..ad0fbc9 100644
> --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
> @@ -20,6 +20,34 @@
> model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
> compatible = "qcom,ipq4019";
>
> + memory {
> + device_type = "memory";
> + reg = <0x80000000 0x10000000>; /* 256MB */
> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + rsvd1@87000000 {
> + /* Reserved for other subsystem */
> + reg = <0x87000000 0x500000>;
> + no-map;
> + };
> +
> + wifi_dump@87500000 {
> + reg = <0x87500000 0x600000>;
> + no-map;
> + };
> +
> + rsvd2@87B00000 {
Lowercase hex please.
> + /* Reserved for other subsystem */
> + reg = <0x87B00000 0x500000>;
> + no-map;
> + };
> + };
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-03-20 7:33 ` Stephen Boyd
@ 2018-03-20 11:45 ` sricharan
0 siblings, 0 replies; 35+ messages in thread
From: sricharan @ 2018-03-20 11:45 UTC (permalink / raw)
To: Stephen Boyd
Cc: absahu, andy.gross, bjorn.andersson, catalin.marinas, david.brown,
devicetree, linux-arm-kernel, linux-arm-msm, linux-kernel,
linux-soc, linux, marc.zyngier, mark.rutland, robh+dt, robh,
sboyd, will.deacon
Hi Stephen,
On 2018-03-20 13:03, Stephen Boyd wrote:
> Quoting Sricharan R (2018-03-19 20:58:47)
>> Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
>
> That is an odd place for a reviewed-by tag.
>
oops, by mistake. will fix.
>> Adds missing memory, reserved-memory nodes.
>>
>> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
>> ---
>> arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28
>> +++++++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
>> b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
>> index e413b21e..ad0fbc9 100644
>> --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
>> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
>> @@ -20,6 +20,34 @@
>> model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
>> compatible = "qcom,ipq4019";
>>
>> + memory {
>> + device_type = "memory";
>> + reg = <0x80000000 0x10000000>; /* 256MB */
>> + };
>> +
>> + reserved-memory {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + rsvd1@87000000 {
>> + /* Reserved for other subsystem */
>> + reg = <0x87000000 0x500000>;
>> + no-map;
>> + };
>> +
>> + wifi_dump@87500000 {
>> + reg = <0x87500000 0x600000>;
>> + no-map;
>> + };
>> +
>> + rsvd2@87B00000 {
>
> Lowercase hex please.
ok.
Regards,
Sricharan
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-03-20 3:58 ` [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data Sricharan R
2018-03-20 7:33 ` Stephen Boyd
@ 2018-03-20 14:31 ` Richard Cochran
2018-03-21 9:10 ` sricharan
2018-03-29 14:37 ` Andy Gross
1 sibling, 2 replies; 35+ messages in thread
From: Richard Cochran @ 2018-03-20 14:31 UTC (permalink / raw)
To: Sricharan R
Cc: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
On Tue, Mar 20, 2018 at 09:28:47AM +0530, Sricharan R wrote:
> Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
> Adds missing memory, reserved-memory nodes.
>
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> ---
> arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++++++++++++++++++++++++++
Q: Does mainline Linux even boot on the DK?
A: No, it doesn't.
Please add the missing basic board support before hacking random stuff
into the DTS.
Thanks,
Richard
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-03-20 14:31 ` Richard Cochran
@ 2018-03-21 9:10 ` sricharan
2018-03-21 15:07 ` Richard Cochran
2018-03-29 14:37 ` Andy Gross
1 sibling, 1 reply; 35+ messages in thread
From: sricharan @ 2018-03-21 9:10 UTC (permalink / raw)
To: Richard Cochran
Cc: mark.rutland, robh, devicetree, marc.zyngier, catalin.marinas,
will.deacon, linux, bjorn.andersson, david.brown, absahu, robh+dt,
linux-arm-kernel, linux-arm-msm, andy.gross, linux-soc, sboyd,
linux-kernel
On 2018-03-20 20:01, Richard Cochran wrote:
> On Tue, Mar 20, 2018 at 09:28:47AM +0530, Sricharan R wrote:
>> Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
>> Adds missing memory, reserved-memory nodes.
>>
>> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
>> ---
>> arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28
>> +++++++++++++++++++++++++++
>
> Q: Does mainline Linux even boot on the DK?
>
> A: No, it doesn't.
Yes, i saw that it was booting out of mainline.
Both DK01 and DK04 boards boots out of mainline.
cat /proc/version
Linux version 4.16.0-rc6 (srichara@srichara-linux) (gcc version 6.3.1
20170109 (Linaro GCC 6.3-2017.02)) #1677 SMP PREEMPT Wed Mar 21 12:58:14
IST 2018
If it does not boot for you, then can you check if your bootloader is
passing this bootarg ?
bootargs=console=ttyMSM0,115200n8
This is the only one required from bootloader to boot.
That said, there should have been a default 'chosen' node in DTS
for the serial console atleast which is not there today. I will add
this
in my v4 along with other changes.
Regards,
Sricharan
>
> Please add the missing basic board support before hacking random stuff
> into the DTS.
>
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-03-21 9:10 ` sricharan
@ 2018-03-21 15:07 ` Richard Cochran
2018-03-22 13:05 ` sricharan
0 siblings, 1 reply; 35+ messages in thread
From: Richard Cochran @ 2018-03-21 15:07 UTC (permalink / raw)
To: sricharan
Cc: mark.rutland, robh, devicetree, marc.zyngier, catalin.marinas,
will.deacon, linux, bjorn.andersson, david.brown, absahu, robh+dt,
linux-arm-kernel, linux-arm-msm, andy.gross, linux-soc, sboyd,
linux-kernel
On Wed, Mar 21, 2018 at 02:40:43PM +0530, sricharan@codeaurora.org wrote:
> Yes, i saw that it was booting out of mainline.
> Both DK01 and DK04 boards boots out of mainline.
Well, that is good news.
Which kernel config did you use?
Thanks,
Richard
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-03-21 15:07 ` Richard Cochran
@ 2018-03-22 13:05 ` sricharan
2018-03-22 21:32 ` Richard Cochran
0 siblings, 1 reply; 35+ messages in thread
From: sricharan @ 2018-03-22 13:05 UTC (permalink / raw)
To: Richard Cochran
Cc: mark.rutland, robh, linux-kernel, devicetree, marc.zyngier,
catalin.marinas, will.deacon, linux, bjorn.andersson, david.brown,
absahu, robh+dt, linux-arm-msm, andy.gross, linux-soc, sboyd,
linux-arm-kernel
On 2018-03-21 20:37, Richard Cochran wrote:
> On Wed, Mar 21, 2018 at 02:40:43PM +0530, sricharan@codeaurora.org
> wrote:
>> Yes, i saw that it was booting out of mainline.
>> Both DK01 and DK04 boards boots out of mainline.
>
> Well, that is good news.
>
> Which kernel config did you use?
qcom_defconfig.
Meanwhile i just posted a v4 (CCed you), is it possible that
i can have test feedback ? . That will be great.
Regards,
Sricharan
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-03-22 13:05 ` sricharan
@ 2018-03-22 21:32 ` Richard Cochran
2018-03-23 10:25 ` sricharan
0 siblings, 1 reply; 35+ messages in thread
From: Richard Cochran @ 2018-03-22 21:32 UTC (permalink / raw)
To: sricharan
Cc: mark.rutland, robh, linux-kernel, devicetree, marc.zyngier,
catalin.marinas, will.deacon, linux, bjorn.andersson, david.brown,
absahu, robh+dt, linux-arm-msm, andy.gross, linux-soc, sboyd,
linux-arm-kernel
On Thu, Mar 22, 2018 at 06:35:48PM +0530, sricharan@codeaurora.org wrote:
> Meanwhile i just posted a v4 (CCed you), is it possible that
> i can have test feedback ? . That will be great.
I don't have any DK in hand, but I do have a custom design most
similar to the DK7. I'll gladly try to boot it with your series.
Just to be clear: You are running pure mainline with absolutely no
out-of-tree patches or other modifications, right?
Thanks,
Richard
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-03-22 21:32 ` Richard Cochran
@ 2018-03-23 10:25 ` sricharan
0 siblings, 0 replies; 35+ messages in thread
From: sricharan @ 2018-03-23 10:25 UTC (permalink / raw)
To: Richard Cochran
Cc: mark.rutland, robh, devicetree, marc.zyngier, catalin.marinas,
will.deacon, linux-kernel, linux, david.brown, absahu, robh+dt,
linux-arm-msm, andy.gross, bjorn.andersson, linux-soc, sboyd,
linux-arm-kernel
On 2018-03-23 03:02, Richard Cochran wrote:
> On Thu, Mar 22, 2018 at 06:35:48PM +0530, sricharan@codeaurora.org
> wrote:
>> Meanwhile i just posted a v4 (CCed you), is it possible that
>> i can have test feedback ? . That will be great.
>
> I don't have any DK in hand, but I do have a custom design most
> similar to the DK7. I'll gladly try to boot it with your series.
>
> Just to be clear: You are running pure mainline with absolutely no
> out-of-tree patches or other modifications, right?
Yes, mainline (4.16-rc6), plus my patches, pushed it here as well [1]
Btw, posted v5 to fix a minor thing that i missed earlier.
[1] https://github.com/sricharanaz/kernel/tree/ipq_test
Regards,
Sricharan
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-03-20 14:31 ` Richard Cochran
2018-03-21 9:10 ` sricharan
@ 2018-03-29 14:37 ` Andy Gross
2018-03-29 16:32 ` Richard Cochran
2018-03-29 16:37 ` Richard Cochran
1 sibling, 2 replies; 35+ messages in thread
From: Andy Gross @ 2018-03-29 14:37 UTC (permalink / raw)
To: Richard Cochran
Cc: Sricharan R, robh+dt, robh, mark.rutland, linux, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
On Tue, Mar 20, 2018 at 07:31:31AM -0700, Richard Cochran wrote:
> On Tue, Mar 20, 2018 at 09:28:47AM +0530, Sricharan R wrote:
> > Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
> > Adds missing memory, reserved-memory nodes.
> >
> > Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> > ---
> > arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++++++++++++++++++++++++++
>
> Q: Does mainline Linux even boot on the DK?
>
> A: No, it doesn't.
If you aren't actually testing/validating this specific board, how can you make
a statement like this? Unless you have tested these specifically on this board,
I'd appreciate not getting false information about what is or is not working.
>
> Please add the missing basic board support before hacking random stuff
> into the DTS.
Feel free to send your own contributions where you are adding the things that
are important to you.
Regards,
Andy Gross
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-03-29 14:37 ` Andy Gross
@ 2018-03-29 16:32 ` Richard Cochran
2018-03-29 16:37 ` Richard Cochran
1 sibling, 0 replies; 35+ messages in thread
From: Richard Cochran @ 2018-03-29 16:32 UTC (permalink / raw)
To: Andy Gross
Cc: Sricharan R, robh+dt, robh, mark.rutland, linux, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
On Thu, Mar 29, 2018 at 09:37:15AM -0500, Andy Gross wrote:
>
> If you aren't actually testing/validating this specific board, how can you make
> a statement like this? Unless you have tested these specifically on this board,
> I'd appreciate not getting false information about what is or is not working.
I tested qualcomm's 4.4 kernel from codeaurora, and *it* doesn't boot
on the ipq4019. I apologize for making a misleading statement. I
assumed that the ipq4019 DTSs were merged in not booting from the
beginning.
Sorry,
Richard
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-03-29 14:37 ` Andy Gross
2018-03-29 16:32 ` Richard Cochran
@ 2018-03-29 16:37 ` Richard Cochran
2018-04-02 9:58 ` sricharan
1 sibling, 1 reply; 35+ messages in thread
From: Richard Cochran @ 2018-03-29 16:37 UTC (permalink / raw)
To: Andy Gross
Cc: Sricharan R, robh+dt, robh, mark.rutland, linux, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
On Thu, Mar 29, 2018 at 09:37:15AM -0500, Andy Gross wrote:
>
> Feel free to send your own contributions where you are adding the things that
> are important to you.
You can count on it. I am really happy that ipq4019 at least boots mainline.
BTW is there any hope of getting a working mainline DTS for the
ipq8062, ideally for the ap145_100 board?
Thanks,
Richard
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-03-29 16:37 ` Richard Cochran
@ 2018-04-02 9:58 ` sricharan
2018-04-06 4:55 ` Richard Cochran
0 siblings, 1 reply; 35+ messages in thread
From: sricharan @ 2018-04-02 9:58 UTC (permalink / raw)
To: Richard Cochran
Cc: Andy Gross, robh+dt, robh, mark.rutland, linux, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
On 2018-03-29 22:07, Richard Cochran wrote:
> On Thu, Mar 29, 2018 at 09:37:15AM -0500, Andy Gross wrote:
>>
>> Feel free to send your own contributions where you are adding the
>> things that
>> are important to you.
>
> You can count on it. I am really happy that ipq4019 at least boots
> mainline.
>
> BTW is there any hope of getting a working mainline DTS for the
> ipq8062, ideally for the ap145_100 board?
Yes, i will post another series for ipq806[2/4] updates and the
corresponding
boards after this.
Regards,
Sricharan
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-04-02 9:58 ` sricharan
@ 2018-04-06 4:55 ` Richard Cochran
2018-04-06 13:05 ` sricharan
0 siblings, 1 reply; 35+ messages in thread
From: Richard Cochran @ 2018-04-06 4:55 UTC (permalink / raw)
To: sricharan
Cc: Andy Gross, robh+dt, robh, mark.rutland, linux, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
On Mon, Apr 02, 2018 at 03:28:47PM +0530, sricharan@codeaurora.org wrote:
> Yes, i will post another series for ipq806[2/4] updates and the
> corresponding
> boards after this.
I tried mainline on the ap148 using qcom_defconfig and the
qcom-ipq8064-ap148.dtb, and it doesn't boot FYI.
Thanks,
Richard
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-04-06 4:55 ` Richard Cochran
@ 2018-04-06 13:05 ` sricharan
2018-04-06 15:13 ` Richard Cochran
0 siblings, 1 reply; 35+ messages in thread
From: sricharan @ 2018-04-06 13:05 UTC (permalink / raw)
To: Richard Cochran
Cc: Andy Gross, robh+dt, robh, mark.rutland, linux, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
On 2018-04-06 10:25, Richard Cochran wrote:
> On Mon, Apr 02, 2018 at 03:28:47PM +0530, sricharan@codeaurora.org
> wrote:
>> Yes, i will post another series for ipq806[2/4] updates and the
>> corresponding
>> boards after this.
>
> I tried mainline on the ap148 using qcom_defconfig and the
> qcom-ipq8064-ap148.dtb, and it doesn't boot FYI.
>
I tried booting mainline built with qcom_defconfig on ap148 and
did boot. Not sure if your bootloader's bootarg is this,
'console=ttyMSM0,115200n8' ?
root@(none):/# cat /proc/version
Linux version 4.16.0 (srichara@srichara-linux) (gcc version 6.3.1
20170109 (Linaro GCC 6.3-2017.02)) #1691 SMP PREEMPT Fri Apr 6 15:30:45
IST 2018
root@(none):/#
Regards,
Sricharan
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-04-06 13:05 ` sricharan
@ 2018-04-06 15:13 ` Richard Cochran
2018-04-06 16:08 ` sricharan
0 siblings, 1 reply; 35+ messages in thread
From: Richard Cochran @ 2018-04-06 15:13 UTC (permalink / raw)
To: sricharan
Cc: Andy Gross, robh+dt, robh, mark.rutland, linux, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
On Fri, Apr 06, 2018 at 06:35:49PM +0530, sricharan@codeaurora.org wrote:
> I tried booting mainline built with qcom_defconfig on ap148 and
> did boot. Not sure if your bootloader's bootarg is this,
> 'console=ttyMSM0,115200n8' ?
Yes, I think so. I'll double check it.
Do you have any out-of-tree patches or special jumper settings?
Thanks,
Richard
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
2018-04-06 15:13 ` Richard Cochran
@ 2018-04-06 16:08 ` sricharan
0 siblings, 0 replies; 35+ messages in thread
From: sricharan @ 2018-04-06 16:08 UTC (permalink / raw)
To: Richard Cochran
Cc: Andy Gross, robh+dt, robh, mark.rutland, linux, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
On 2018-04-06 20:43, Richard Cochran wrote:
> On Fri, Apr 06, 2018 at 06:35:49PM +0530, sricharan@codeaurora.org
> wrote:
>> I tried booting mainline built with qcom_defconfig on ap148 and
>> did boot. Not sure if your bootloader's bootarg is this,
>> 'console=ttyMSM0,115200n8' ?
>
> Yes, I think so. I'll double check it.
>
> Do you have any out-of-tree patches or special jumper settings?
No out of tree patches or special jumper settings. I am booting the
mainline kernel, ap148.dtb + ramfs.
Regards,
Sricharan
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v3 05/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
2018-03-20 3:58 [PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals Sricharan R
` (3 preceding siblings ...)
2018-03-20 3:58 ` [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data Sricharan R
@ 2018-03-20 3:58 ` Sricharan R
2018-03-20 14:32 ` Richard Cochran
2018-03-20 3:58 ` [PATCH v3 06/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file Sricharan R
` (7 subsequent siblings)
12 siblings, 1 reply; 35+ messages in thread
From: Sricharan R @ 2018-03-20 3:58 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
Cc: sricharan
Add the common parts for the dk04 boards.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 129 ++++++++++++++++++++++++++
1 file changed, 129 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 0000000..96ce081
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+ compatible = "qcom,ipq4019";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256MB */
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd1@87000000 {
+ /* Reserved for other subsystem */
+ reg = <0x87000000 0x500000>;
+ no-map;
+ };
+
+ wifi_dump@87500000 {
+ reg = <0x87500000 0x600000>;
+ no-map;
+ };
+
+ rsvd2@87B00000 {
+ /* Reserved for other subsystem */
+ reg = <0x87B00000 0x500000>;
+ no-map;
+ };
+ };
+
+ soc {
+ pinctrl@1000000 {
+ serial_0_pins: serial0_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ serial_1_pins: serial1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ bias-disable;
+ output-high;
+ };
+ };
+
+ i2c_0_pins: i2c_0_pinmux {
+ mux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+ };
+
+ nand_pins: nand_pins {
+ mux {
+ pins = "gpio53", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59",
+ "gpio60", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68", "gpio69";
+ function = "qpic";
+ };
+ };
+ };
+
+ serial@78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ serial@78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ blsp_dma: dma@7884000 {
+ status = "ok";
+ };
+
+ spi_0: spi@78b5000 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 12 0>;
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "n25q128a11";
+ spi-max-frequency = <24000000>;
+ };
+ };
+
+ pcie0: pci@40000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 38 0x1>;
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH v3 05/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
2018-03-20 3:58 ` [PATCH v3 05/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi Sricharan R
@ 2018-03-20 14:32 ` Richard Cochran
0 siblings, 0 replies; 35+ messages in thread
From: Richard Cochran @ 2018-03-20 14:32 UTC (permalink / raw)
To: Sricharan R
Cc: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
On Tue, Mar 20, 2018 at 09:28:48AM +0530, Sricharan R wrote:
> Add the common parts for the dk04 boards.
Does this board even boot with mainline linux?
Thanks,
Richard
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v3 06/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
2018-03-20 3:58 [PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals Sricharan R
` (4 preceding siblings ...)
2018-03-20 3:58 ` [PATCH v3 05/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi Sricharan R
@ 2018-03-20 3:58 ` Sricharan R
2018-03-20 7:34 ` Stephen Boyd
2018-03-20 3:58 ` [PATCH v3 07/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 " Sricharan R
` (6 subsequent siblings)
12 siblings, 1 reply; 35+ messages in thread
From: Sricharan R @ 2018-03-20 3:58 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
Cc: sricharan
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 20 ++++++++++++++++++++
2 files changed, 21 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b59e99b..4f209fb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -747,6 +747,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 0000000..871ac3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+
+ soc {
+ qpic_bam: dma@7984000 {
+ status = "ok";
+ };
+
+ nand: qpic-nand@79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH v3 06/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
2018-03-20 3:58 ` [PATCH v3 06/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file Sricharan R
@ 2018-03-20 7:34 ` Stephen Boyd
2018-03-20 12:10 ` sricharan
0 siblings, 1 reply; 35+ messages in thread
From: Stephen Boyd @ 2018-03-20 7:34 UTC (permalink / raw)
To: absahu, andy.gross, bjorn.andersson, catalin.marinas, david.brown,
devicetree, linux-arm-kernel, linux-arm-msm, linux-kernel,
linux-soc, linux, marc.zyngier, mark.rutland, robh+dt, robh,
sboyd, will.deacon
Cc: sricharan
Quoting Sricharan R (2018-03-19 20:58:49)
> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
> new file mode 100644
> index 0000000..871ac3f
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
> @@ -0,0 +1,20 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
> +
> +#include "qcom-ipq4019-ap.dk04.1.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
> +
> + soc {
> + qpic_bam: dma@7984000 {
Why the labels?
> + status = "ok";
> + };
> +
> + nand: qpic-nand@79b0000 {
> + pinctrl-0 = <&nand_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + };
> + };
> +};
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH v3 06/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
2018-03-20 7:34 ` Stephen Boyd
@ 2018-03-20 12:10 ` sricharan
0 siblings, 0 replies; 35+ messages in thread
From: sricharan @ 2018-03-20 12:10 UTC (permalink / raw)
To: Stephen Boyd
Cc: absahu, andy.gross, bjorn.andersson, catalin.marinas, david.brown,
devicetree, linux-arm-kernel, linux-arm-msm, linux-kernel,
linux-soc, linux, marc.zyngier, mark.rutland, robh+dt, robh,
sboyd, will.deacon
On 2018-03-20 13:04, Stephen Boyd wrote:
> Quoting Sricharan R (2018-03-19 20:58:49)
>> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
>> b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
>> new file mode 100644
>> index 0000000..871ac3f
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
>> @@ -0,0 +1,20 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> +
>> +#include "qcom-ipq4019-ap.dk04.1.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
>> +
>> + soc {
>> + qpic_bam: dma@7984000 {
>
> Why the labels?
>
ok, will remove here and few other places to make it uniform.
Regards,
Sricharan
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v3 07/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
2018-03-20 3:58 [PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals Sricharan R
` (5 preceding siblings ...)
2018-03-20 3:58 ` [PATCH v3 06/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file Sricharan R
@ 2018-03-20 3:58 ` Sricharan R
2018-03-20 3:58 ` [PATCH v3 08/13] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data Sricharan R
` (5 subsequent siblings)
12 siblings, 0 replies; 35+ messages in thread
From: Sricharan R @ 2018-03-20 3:58 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
Cc: sricharan
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 8 ++++++++
2 files changed, 9 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4f209fb..b71487a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -748,6 +748,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 0000000..0843523
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH v3 08/13] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
2018-03-20 3:58 [PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals Sricharan R
` (6 preceding siblings ...)
2018-03-20 3:58 ` [PATCH v3 07/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 " Sricharan R
@ 2018-03-20 3:58 ` Sricharan R
2018-03-20 3:58 ` [PATCH v3 09/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file Sricharan R
` (4 subsequent siblings)
12 siblings, 0 replies; 35+ messages in thread
From: Sricharan R @ 2018-03-20 3:58 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
Cc: sricharan
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Add the common data for all dk07 based boards.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 83 +++++++++++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 0000000..37a2ea8
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+ compatible = "qcom,ipq4019";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512MB */
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd1@87000000 {
+ /* Reserved for other subsystem */
+ reg = <0x87000000 0x500000>;
+ no-map;
+ };
+
+ wifi_dump@87500000 {
+ reg = <0x87500000 0x600000>;
+ no-map;
+ };
+
+ rsvd2@87B00000 {
+ /* Reserved for other subsystem */
+ reg = <0x87B00000 0x500000>;
+ no-map;
+ };
+ };
+
+ soc {
+ pinctrl@1000000 {
+ serial_0_pins: serial0_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ i2c_0_pins: i2c_0_pinmux {
+ mux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+ };
+ };
+
+ serial@78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ blsp_dma: dma@7884000 {
+ status = "ok";
+ };
+
+ i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ qpic_bam: dma@7984000 {
+ status = "ok";
+ };
+
+ nand: qpic-nand@79b0000 {
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH v3 09/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
2018-03-20 3:58 [PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals Sricharan R
` (7 preceding siblings ...)
2018-03-20 3:58 ` [PATCH v3 08/13] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data Sricharan R
@ 2018-03-20 3:58 ` Sricharan R
2018-03-20 3:58 ` [PATCH v3 10/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 " Sricharan R
` (3 subsequent siblings)
12 siblings, 0 replies; 35+ messages in thread
From: Sricharan R @ 2018-03-20 3:58 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
Cc: sricharan
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +++++++++++++++++++++++++
2 files changed, 66 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b71487a..8c93fd0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -749,6 +749,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
+ qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 0000000..e4fddc1
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
+
+ soc {
+ pcie0: pci@40000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 38 0x1>;
+ };
+
+ spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+ status = "ok";
+ };
+
+ pinctrl@1000000 {
+ serial_1_pins: serial1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ serial@78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ spi_0: spi@78b5000 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 12 0>;
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "n25q128a11";
+ spi-max-frequency = <24000000>;
+ };
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH v3 10/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
2018-03-20 3:58 [PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals Sricharan R
` (8 preceding siblings ...)
2018-03-20 3:58 ` [PATCH v3 09/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file Sricharan R
@ 2018-03-20 3:58 ` Sricharan R
2018-03-20 3:58 ` [PATCH v3 11/13] ARM: dts: ipq8074: Add peripheral nodes Sricharan R
` (2 subsequent siblings)
12 siblings, 0 replies; 35+ messages in thread
From: Sricharan R @ 2018-03-20 3:58 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
Cc: sricharan
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26 +++++++++++++++++++++++++
2 files changed, 27 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8c93fd0..0844087 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -750,6 +750,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
+ qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
new file mode 100644
index 0000000..c1e909c
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
+
+ soc {
+ pinctrl@1000000 {
+ serial_1_pins: serial1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+ };
+
+ serial@78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH v3 11/13] ARM: dts: ipq8074: Add peripheral nodes
2018-03-20 3:58 [PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals Sricharan R
` (9 preceding siblings ...)
2018-03-20 3:58 ` [PATCH v3 10/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 " Sricharan R
@ 2018-03-20 3:58 ` Sricharan R
2018-03-20 3:58 ` [PATCH v3 12/13] ARM: dts: ipq8074: Add pcie nodes Sricharan R
2018-03-20 3:58 ` [PATCH v3 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board Sricharan R
12 siblings, 0 replies; 35+ messages in thread
From: Sricharan R @ 2018-03-20 3:58 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
Cc: sricharan
Add serial, i2c, bam, spi, qpic peripheral nodes.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 ++++++++++++++++++++++++++++++++++
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2bc5dec..a8dbbf0 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -124,6 +124,111 @@
clock-names = "core", "iface";
status = "disabled";
};
+
+ blsp_dma: dma@7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7884000 0x2b000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ serial_blsp0: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78af000 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ serial_blsp2: serial@78b1000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78b1000 0x200>;
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 4>,
+ <&blsp_dma 5>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi_0: spi@78b5000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b5000 0x600>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c_0: i2c@78b6000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b6000 0x600>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ dmas = <&blsp_dma 15>, <&blsp_dma 14>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c_1: i2c@78b7000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b7000 0x600>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <100000>;
+ dmas = <&blsp_dma 17>, <&blsp_dma 16>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ qpic_bam: dma@7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7984000 0x1a000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ qpic_nand: nand@79b0000 {
+ compatible = "qcom,ipq8074-nand";
+ reg = <0x79b0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ status = "disabled";
+ };
};
cpus {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH v3 12/13] ARM: dts: ipq8074: Add pcie nodes
2018-03-20 3:58 [PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals Sricharan R
` (10 preceding siblings ...)
2018-03-20 3:58 ` [PATCH v3 11/13] ARM: dts: ipq8074: Add peripheral nodes Sricharan R
@ 2018-03-20 3:58 ` Sricharan R
2018-03-20 3:58 ` [PATCH v3 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board Sricharan R
12 siblings, 0 replies; 35+ messages in thread
From: Sricharan R @ 2018-03-20 3:58 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
Cc: sricharan
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +++++++++++++++++++++++++++++++++-
1 file changed, 156 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index a8dbbf0..caf3485 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
- pinctrl@1000000 {
+ tlmm: pinctrl@1000000 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
@@ -229,6 +229,161 @@
dma-names = "tx", "rx", "cmd";
status = "disabled";
};
+
+ pcie_phy0: phy@86000 {
+ compatible = "qcom,ipq8074-qmp-pcie-phy";
+ reg = <0x86000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe_clk";
+ clock-output-names = "pcie20_phy0_pipe_clk";
+
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie0: pci@20000000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x20000000 0xf1d
+ 0x20000f20 0xa8
+ 0x80000 0x2000
+ 0x20100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie_phy0>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0 0x20200000 0x20200000
+ 0 0x100000 /* downstream I/O */
+ 0x82000000 0 0x20300000 0x20300000
+ 0 0xd00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 75
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_AUX_CLK>;
+
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_SLEEP_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+ status = "disabled";
+ };
+
+ pcie_phy1: phy@8e000 {
+ compatible = "qcom,ipq8074-qmp-pcie-phy";
+ reg = <0x8e000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+ clock-names = "pipe_clk";
+ clock-output-names = "pcie20_phy1_pipe_clk";
+
+ resets = <&gcc GCC_PCIE1_PHY_BCR>,
+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie1: pci@10000000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x10000000 0xf1d
+ 0x10000f20 0xa8
+ 0x88000 0x2000
+ 0x10100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie_phy1>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0 0x10200000 0x10200000
+ 0 0x100000 /* downstream I/O */
+ 0x82000000 0 0x10300000 0x10300000
+ 0 0xd00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
+ <&gcc GCC_PCIE1_AXI_M_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_AUX_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+ <&gcc GCC_PCIE1_SLEEP_ARES>,
+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE1_AHB_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+ status = "disabled";
+ };
};
cpus {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 35+ messages in thread* [PATCH v3 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board
2018-03-20 3:58 [PATCH v3 00/13] ARM: dts: ipq: updates to enable a few peripherals Sricharan R
` (11 preceding siblings ...)
2018-03-20 3:58 ` [PATCH v3 12/13] ARM: dts: ipq8074: Add pcie nodes Sricharan R
@ 2018-03-20 3:58 ` Sricharan R
2018-03-20 7:35 ` Stephen Boyd
12 siblings, 1 reply; 35+ messages in thread
From: Sricharan R @ 2018-03-20 3:58 UTC (permalink / raw)
To: robh+dt, robh, mark.rutland, linux, andy.gross, david.brown,
catalin.marinas, will.deacon, sboyd, bjorn.andersson, devicetree,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-soc, absahu,
marc.zyngier
Cc: sricharan
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++++++++++++++++++++++++++++++
1 file changed, 103 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..8efc8f9e 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -21,6 +21,7 @@
aliases {
serial0 = &blsp1_uart5;
+ serial1 = &serial_blsp2;
};
chosen {
@@ -41,6 +42,47 @@
bias-disable;
};
};
+
+ i2c_0_pins: i2c_0_pinmux {
+ mux {
+ pins = "gpio42", "gpio43";
+ function = "blsp1_i2c";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pins {
+ mux {
+ pins = "gpio38", "gpio39", "gpio40", "gpio41";
+ function = "blsp0_spi";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ hsuart_pins: hsuart_pins {
+ mux {
+ pins = "gpio46", "gpio47", "gpio48", "gpio49";
+ function = "blsp2_uart";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ qpic_pins: qpic_pins {
+ mux {
+ pins = "gpio1", "gpio3", "gpio4",
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17";
+ function = "qpic";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
};
serial@78b3000 {
@@ -48,5 +90,66 @@
pinctrl-names = "default";
status = "ok";
};
+
+ spi@78b5000 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a11", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+ };
+
+ serial@78b1000 {
+ pinctrl-0 = <&hsuart_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ i2c_0@78b6000 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma@7984000 {
+ status = "ok";
+ };
+
+ nand@79b0000 {
+ pinctrl-0 = <&qpic_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+ };
+
+ phy@86000 {
+ status = "ok";
+ };
+
+ phy@8e000 {
+ status = "ok";
+ };
+
+ pci@20000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 58 0x1>;
+ };
+
+ pci@10000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 61 0x1>;
+ };
};
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH v3 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board
2018-03-20 3:58 ` [PATCH v3 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board Sricharan R
@ 2018-03-20 7:35 ` Stephen Boyd
2018-03-20 12:10 ` sricharan
0 siblings, 1 reply; 35+ messages in thread
From: Stephen Boyd @ 2018-03-20 7:35 UTC (permalink / raw)
To: absahu, andy.gross, bjorn.andersson, catalin.marinas, david.brown,
devicetree, linux-arm-kernel, linux-arm-msm, linux-kernel,
linux-soc, linux, marc.zyngier, mark.rutland, robh+dt, robh,
sboyd, will.deacon
Cc: sricharan
Quoting Sricharan R (2018-03-19 20:58:56)
> + };
> + };
> +
> + serial@78b1000 {
> + pinctrl-0 = <&hsuart_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + };
> +
> + i2c_0@78b6000 {
Node should just be called i2c?
> + pinctrl-0 = <&i2c_0_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + };
> +
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH v3 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board
2018-03-20 7:35 ` Stephen Boyd
@ 2018-03-20 12:10 ` sricharan
0 siblings, 0 replies; 35+ messages in thread
From: sricharan @ 2018-03-20 12:10 UTC (permalink / raw)
To: Stephen Boyd
Cc: absahu, andy.gross, bjorn.andersson, catalin.marinas, david.brown,
devicetree, linux-arm-kernel, linux-arm-msm, linux-kernel,
linux-soc, linux, marc.zyngier, mark.rutland, robh+dt, robh,
sboyd, will.deacon, linux-arm-msm-owner
On 2018-03-20 13:05, Stephen Boyd wrote:
> Quoting Sricharan R (2018-03-19 20:58:56)
>> + };
>> + };
>> +
>> + serial@78b1000 {
>> + pinctrl-0 = <&hsuart_pins>;
>> + pinctrl-names = "default";
>> + status = "ok";
>> + };
>> +
>> + i2c_0@78b6000 {
>
> Node should just be called i2c?
>
ok, will fix
Regards,
Sricharan
^ permalink raw reply [flat|nested] 35+ messages in thread