* [PATCH v1 0/1] arm: npcm: enable L2 cache in NPCM7xx architecture
@ 2018-04-08 14:03 Tomer Maimon
2018-04-08 14:03 ` [PATCH v1 1/1] " Tomer Maimon
2018-04-10 14:41 ` [PATCH v1 0/1] " Arnd Bergmann
0 siblings, 2 replies; 3+ messages in thread
From: Tomer Maimon @ 2018-04-08 14:03 UTC (permalink / raw)
To: arm, linux, avifishman70, brendanhiggins, venture, yuenn, joel
Cc: arnd, devicetree, linux-kernel, openbmc, Tomer Maimon
This patch Enable ARM L2 cache module in Nuvoton NPCM7xx BMC
by adding L2 cache parameters into NPCM7xx DT machine start structure.
At patch V7 arm: npcm: add basic support for Nuvoton BMCs we got comments
regarding the flags use in L2 cache module.
- https://www.spinics.net/lists/arm-kernel/msg613212.html
After checking again the L2 cache use in the NPCM7xx,
the only L2 cache flag we need to set is L2C_AUX_CTRL_SHARED_OVERRIDE
and it is done in the device tree:
https://patchwork.kernel.org/patch/10063497/
L2 cache flag mask allowed all the flag option.
Tomer Maimon (1):
arm: npcm: enable L2 cache in NPCM7xx architecture
arch/arm/mach-npcm/npcm7xx.c | 2 ++
1 file changed, 2 insertions(+)
--
2.14.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v1 1/1] arm: npcm: enable L2 cache in NPCM7xx architecture
2018-04-08 14:03 [PATCH v1 0/1] arm: npcm: enable L2 cache in NPCM7xx architecture Tomer Maimon
@ 2018-04-08 14:03 ` Tomer Maimon
2018-04-10 14:41 ` [PATCH v1 0/1] " Arnd Bergmann
1 sibling, 0 replies; 3+ messages in thread
From: Tomer Maimon @ 2018-04-08 14:03 UTC (permalink / raw)
To: arm, linux, avifishman70, brendanhiggins, venture, yuenn, joel
Cc: arnd, devicetree, linux-kernel, openbmc, Tomer Maimon
Enable ARM L2 cache module in Nuvoton NPCM7xx BMC by adding
L2 cache parameters into NPCM7xx DT machine start structure.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
arch/arm/mach-npcm/npcm7xx.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
index 5f7cd88103ef..c5f77d854c4f 100644
--- a/arch/arm/mach-npcm/npcm7xx.c
+++ b/arch/arm/mach-npcm/npcm7xx.c
@@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
.atag_offset = 0x100,
.dt_compat = npcm7xx_dt_match,
+ .l2c_aux_val = 0x0,
+ .l2c_aux_mask = ~0x0,
MACHINE_END
--
2.14.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v1 0/1] arm: npcm: enable L2 cache in NPCM7xx architecture
2018-04-08 14:03 [PATCH v1 0/1] arm: npcm: enable L2 cache in NPCM7xx architecture Tomer Maimon
2018-04-08 14:03 ` [PATCH v1 1/1] " Tomer Maimon
@ 2018-04-10 14:41 ` Arnd Bergmann
1 sibling, 0 replies; 3+ messages in thread
From: Arnd Bergmann @ 2018-04-10 14:41 UTC (permalink / raw)
To: Tomer Maimon
Cc: arm-soc, Russell King - ARM Linux, Avi Fishman, Brendan Higgins,
Patrick Venture, Nancy Yuen, Joel Stanley, DTML,
Linux Kernel Mailing List, OpenBMC Maillist
On Sun, Apr 8, 2018 at 4:03 PM, Tomer Maimon <tmaimon77@gmail.com> wrote:
> This patch Enable ARM L2 cache module in Nuvoton NPCM7xx BMC
> by adding L2 cache parameters into NPCM7xx DT machine start structure.
>
> At patch V7 arm: npcm: add basic support for Nuvoton BMCs we got comments
> regarding the flags use in L2 cache module.
> - https://www.spinics.net/lists/arm-kernel/msg613212.html
>
> After checking again the L2 cache use in the NPCM7xx,
> the only L2 cache flag we need to set is L2C_AUX_CTRL_SHARED_OVERRIDE
> and it is done in the device tree:
> https://patchwork.kernel.org/patch/10063497/
>
> L2 cache flag mask allowed all the flag option.
I've applied the patch to my fixes branch now, but took your description above
instead of the two-line text that you had in the patch itself. I liked
the longer
text much better.
Arnd
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2018-04-08 14:03 [PATCH v1 0/1] arm: npcm: enable L2 cache in NPCM7xx architecture Tomer Maimon
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2018-04-10 14:41 ` [PATCH v1 0/1] " Arnd Bergmann
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