From: thor.thayer@linux.intel.com
To: bp@alien8.de, mchehab@kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, dinguyen@kernel.org,
catalin.marinas@arm.com, will.deacon@arm.com
Cc: devicetree@vger.kernel.org, thor.thayer@linux.intel.com,
linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org
Subject: [PATCHv2 0/3] Add SDRAM ECC support for Stratix10
Date: Fri, 27 Apr 2018 13:37:15 -0500 [thread overview]
Message-ID: <1524854238-19394-1-git-send-email-thor.thayer@linux.intel.com> (raw)
From: Thor Thayer <thor.thayer@linux.intel.com>
The Intel Stratix10 platform is an ARM64 but still has many register
definitions that are similar to the Arria10. One significant difference
is the Stratix10 Secure Monitor handles registers that may
be shared by guest OSes at a different exception level. Register access
is through an ARM SMC call. Currently, SMC handling is implemented
in Stratix10 U-Boot.
Thor Thayer (3):
Documentation: dt: socfpga: Add Stratix10 ECC Manager binding
edac: altera: Add support for Stratix10 SDRAM EDAC
arm64: dts: stratix10: add sdram ecc
.../bindings/arm/altera/socfpga-eccmgr.txt | 35 ++
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 +
drivers/edac/Kconfig | 2 +-
drivers/edac/altera_edac.c | 455 ++++++++++++++++++++-
drivers/edac/altera_edac.h | 126 +++++-
5 files changed, 602 insertions(+), 28 deletions(-)
--
2.7.4
next reply other threads:[~2018-04-27 18:37 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-27 18:37 thor.thayer [this message]
2018-04-27 18:37 ` [PATCHv2 1/3] Documentation: dt: socfpga: Add Stratix10 ECC Manager binding thor.thayer
2018-05-01 12:54 ` Rob Herring
2018-04-27 18:37 ` [PATCHv2 2/3] edac: altera: Add support for Stratix10 SDRAM EDAC thor.thayer
2018-04-27 18:37 ` [PATCHv2 3/3] arm64: dts: stratix10: add sdram ecc thor.thayer
2018-05-07 16:59 ` Borislav Petkov
2018-05-07 20:50 ` Dinh Nguyen
2018-05-07 21:10 ` Dinh Nguyen
2018-05-08 8:53 ` Borislav Petkov
2018-05-08 19:27 ` Dinh Nguyen
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