From: Amelie Delaunay <amelie.delaunay@st.com>
To: Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org,
Amelie Delaunay <amelie.delaunay@st.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] ARM: dts: stm32: update rtc st, syscfg property on stm32f746
Date: Wed, 9 May 2018 17:18:14 +0200 [thread overview]
Message-ID: <1525879094-19562-3-git-send-email-amelie.delaunay@st.com> (raw)
In-Reply-To: <1525879094-19562-1-git-send-email-amelie.delaunay@st.com>
To fit with latest rtc driver updates, rtc st,syscfg property must contain
the control register offset of pwrcfg and the mask corresponding to the
DBP (Disable Backup Protection) bit.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
---
arch/arm/boot/dts/stm32f746.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 1479e3e..f48d06a 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -297,7 +297,7 @@
interrupt-parent = <&exti>;
interrupts = <17 1>;
interrupt-names = "alarm";
- st,syscfg = <&pwrcfg>;
+ st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
--
2.7.4
next prev parent reply other threads:[~2018-05-09 15:18 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-09 15:18 [PATCH 0/2] ARM: dts: stm32: update rtc st,syscfg Amelie Delaunay
2018-05-09 15:18 ` [PATCH 1/2] ARM: dts: stm32: update rtc st,syscfg property on stm32f429 Amelie Delaunay
2018-05-09 15:18 ` Amelie Delaunay [this message]
2018-06-25 10:12 ` [PATCH 0/2] ARM: dts: stm32: update rtc st,syscfg Alexandre Torgue
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