From: Geert Uytterhoeven <geert+renesas@glider.be>
To: Simon Horman <horms@verge.net.au>, Magnus Damm <magnus.damm@gmail.com>
Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-arm-kernel@lists.infradead.org,
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Subject: [PATCH v2 2/2] arm64: dts: renesas: r8a77970: Add Cortex-A53 PMU node
Date: Wed, 9 May 2018 17:23:23 +0200 [thread overview]
Message-ID: <1525879403-12207-3-git-send-email-geert+renesas@glider.be> (raw)
In-Reply-To: <1525879403-12207-1-git-send-email-geert+renesas@glider.be>
Enable the performance monitor unit for the Cortex-A53 cores on the
R-Car V3M (r8a77970) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
- Move the pmu node from the soc subnode to the root node, as it
doesn't have registers.
---
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index ccc955e89cea4d32..71157ad893910a97 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -73,6 +73,13 @@
clock-frequency = <0>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>, <&a53_1>;
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
--
2.7.4
next prev parent reply other threads:[~2018-05-09 15:23 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-09 15:23 [PATCH v2 0/2] arm64: dts: renesas: r8a77970: Add SMP Support Geert Uytterhoeven
2018-05-09 15:23 ` [PATCH v2 1/2] arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core Geert Uytterhoeven
2018-05-09 15:23 ` Geert Uytterhoeven [this message]
2018-05-09 19:08 ` [PATCH v2 0/2] arm64: dts: renesas: r8a77970: Add SMP Support Simon Horman
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