From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lin Huang Subject: [PATCH v3 2/4] Documentation: bindings: add phy_config for Rockchip USB Type-C PHY Date: Mon, 14 May 2018 17:53:53 +0800 Message-ID: <1526291635-31122-2-git-send-email-hl@rock-chips.com> References: <1526291635-31122-1-git-send-email-hl@rock-chips.com> Return-path: In-Reply-To: <1526291635-31122-1-git-send-email-hl@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org To: seanpaul@chromium.org, airlied@linux.ie, zyw@rock-chips.com Cc: dianders@chromium.org, briannorris@chromium.org, linux-rockchip@lists.infradead.org, heiko@sntech.de, daniel.vetter@intel.com, jani.nikula@linux.intel.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, eballetbo@gmail.com, robh+dt@kernel.org, devicetree@vger.kernel.org, Lin Huang List-Id: devicetree@vger.kernel.org If want to do training outside DP Firmware, need phy voltage swing and pre_emphasis value. Signed-off-by: Lin Huang --- Changes in v2: - rebase Changes in v3: - modify property description and add this property to example .../devicetree/bindings/phy/phy-rockchip-typec.txt | 29 +++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt index 960da7f..af298f2 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt @@ -17,7 +17,8 @@ Required properties: Optional properties: - extcon : extcon specifier for the Power Delivery - + - rockchip,phy_config : A list of voltage swing(mv) and pre-emphasis + (dB) pairs. Required nodes : a sub-node is required for each port the phy provides. The sub-node name is used to identify dp or usb3 port, and shall be the following entries: @@ -50,6 +51,19 @@ Example: <&cru SRST_P_UPHY0_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,phy_config =<0x2a 0x00 + 0x1f 0x15 + 0x14 0x22 + 0x02 0x2b + 0x21 0x00 + 0x12 0x15 + 0x02 0x22 + 0 0 + 0x15 0x00 + 0x00 0x15 + 0 0 + 0 0>; + tcphy0_dp: dp-port { #phy-cells = <0>; }; @@ -74,6 +88,19 @@ Example: <&cru SRST_P_UPHY1_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,phy_config =<0x2a 0x00 + 0x1f 0x15 + 0x14 0x22 + 0x02 0x2b + 0x21 0x00 + 0x12 0x15 + 0x02 0x22 + 0 0 + 0x15 0x00 + 0x00 0x15 + 0 0 + 0 0>; + tcphy1_dp: dp-port { #phy-cells = <0>; }; -- 2.7.4