From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bhadram Varka Subject: [PATCH V2 3/3] arm64: tegra: Configure DWC EQOS TxPBL for multi-queue Date: Sat, 2 Jun 2018 14:50:51 +0530 Message-ID: <1527931251-4809-3-git-send-email-vbhadram@nvidia.com> References: <1527931251-4809-1-git-send-email-vbhadram@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1527931251-4809-1-git-send-email-vbhadram@nvidia.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, treding@nvidia.com, mperttunen@nvidia.com Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org PBL should be limited to half of the Queue size. For multi-queue: Total MTL queue size 4KB. PBL = 16, PBLx8 = 1 -> This setting would lead to an effective burst = 8*16 = 128, which would mean 128*16B = 2KB (half of queue size) Signed-off-by: Bhadram Varka --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 48c6caf..c4d70c5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -101,7 +101,7 @@ snps,write-requests = <1>; snps,read-requests = <3>; snps,burst-map = <0x7>; - snps,txpbl = <32>; + snps,txpbl = <16>; snps,rxpbl = <8>; snps,mtl-rx-config = <&mtl_rx_setup>; snps,mtl-tx-config = <&mtl_tx_setup>; -- 2.7.4