From: Stu Hsieh <stu.hsieh@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>, Philipp Zabel <p.zabel@pengutronix.de>
Cc: David Airlie <airlied@linux.ie>, Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, srv_heupstream@mediatek.com,
Stu Hsieh <stu.hsieh@mediatek.com>
Subject: [PATCH 02/28] drm/mediatek: support maximum 64 mutex mod
Date: Mon, 11 Jun 2018 11:25:54 +0800 [thread overview]
Message-ID: <1528687580-549-3-git-send-email-stu.hsieh@mediatek.com> (raw)
In-Reply-To: <1528687580-549-1-git-send-email-stu.hsieh@mediatek.com>
This patch support that if modules more than 32,
add index more than 31 when using DISP_REG_MUTEX_MOD2 bit
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +++++++++++++++++++++-------------
1 file changed, 47 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 8130f3dab661..47ffa240bd25 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -41,31 +41,32 @@
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
#define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
#define INT_MUTEX BIT(1)
-#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
-#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
-#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
-#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
-#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
-#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
-#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
-#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
-#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
-#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
-#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
-#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
-#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
-#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
-#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
-
-#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
-#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
-#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
-#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
-#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
-#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_OVL0 11
+#define MT8173_MUTEX_MOD_DISP_OVL1 12
+#define MT8173_MUTEX_MOD_DISP_RDMA0 13
+#define MT8173_MUTEX_MOD_DISP_RDMA1 14
+#define MT8173_MUTEX_MOD_DISP_RDMA2 15
+#define MT8173_MUTEX_MOD_DISP_WDMA0 16
+#define MT8173_MUTEX_MOD_DISP_WDMA1 17
+#define MT8173_MUTEX_MOD_DISP_COLOR0 18
+#define MT8173_MUTEX_MOD_DISP_COLOR1 19
+#define MT8173_MUTEX_MOD_DISP_AAL 20
+#define MT8173_MUTEX_MOD_DISP_GAMMA 21
+#define MT8173_MUTEX_MOD_DISP_UFOE 22
+#define MT8173_MUTEX_MOD_DISP_PWM0 23
+#define MT8173_MUTEX_MOD_DISP_PWM1 24
+#define MT8173_MUTEX_MOD_DISP_OD 25
+
+#define MT2701_MUTEX_MOD_DISP_OVL 3
+#define MT2701_MUTEX_MOD_DISP_WDMA 6
+#define MT2701_MUTEX_MOD_DISP_COLOR 7
+#define MT2701_MUTEX_MOD_DISP_BLS 9
+#define MT2701_MUTEX_MOD_DISP_RDMA0 10
+#define MT2701_MUTEX_MOD_DISP_RDMA1 12
#define MUTEX_SOF_SINGLE_MODE 0
#define MUTEX_SOF_DSI0 1
@@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]);
unsigned int reg;
+ unsigned int offset;
WARN_ON(&ddp->mutex[mutex->id] != mutex);
@@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
reg = MUTEX_SOF_DPI0;
break;
default:
- reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
- reg |= ddp->mutex_mod[id];
- writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
+ if (ddp->mutex_mod[id] < 32) {
+ offset = DISP_REG_MUTEX_MOD(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg |= 1 << ddp->mutex_mod[id];
+ writel_relaxed(reg, ddp->regs + offset);
+ } else {
+ offset = DISP_REG_MUTEX_MOD2(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg |= 1 << (ddp->mutex_mod[id] - 32);
+ writel_relaxed(reg, ddp->regs + offset);
+ }
return;
}
@@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]);
unsigned int reg;
+ unsigned int offset;
WARN_ON(&ddp->mutex[mutex->id] != mutex);
@@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
break;
default:
- reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
- reg &= ~(ddp->mutex_mod[id]);
- writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
+ if (ddp->mutex_mod[id] < 32) {
+ offset = DISP_REG_MUTEX_MOD(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg &= ~(1 << ddp->mutex_mod[id]);
+ writel_relaxed(reg, ddp->regs + offset);
+ } else {
+ offset = DISP_REG_MUTEX_MOD2(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg &= ~(1 << (ddp->mutex_mod[id] - 32));
+ writel_relaxed(reg, ddp->regs + offset);
+ }
break;
}
}
--
2.12.5
next prev parent reply other threads:[~2018-06-11 3:25 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-11 3:25 [PATCH v5 00/28] Add support for mediatek SOC MT2712 Stu Hsieh
2018-06-11 3:25 ` [PATCH 01/28] drm/mediatek: update dt-bindings for mt2712 Stu Hsieh
2018-06-11 3:25 ` Stu Hsieh [this message]
2018-06-11 3:25 ` [PATCH 03/28] drm/mediatek: add ddp component AAL1 Stu Hsieh
2018-06-11 3:25 ` [PATCH 04/28] drm/mediatek: add ddp component OD1 Stu Hsieh
2018-06-13 5:27 ` CK Hu
2018-06-11 3:25 ` [PATCH 05/28] drm/mediatek: add ddp component PWM1 Stu Hsieh
2018-06-11 3:25 ` [PATCH 06/28] drm/mediatek: add ddp component PWM2 Stu Hsieh
2018-06-11 3:25 ` [PATCH 07/28] drm/mediatek: add component DPI1 Stu Hsieh
2018-06-13 5:29 ` CK Hu
2018-06-11 3:26 ` [PATCH 08/28] drm/mediatek: add component DSI2 Stu Hsieh
2018-06-13 5:30 ` CK Hu
2018-06-11 3:26 ` [PATCH 09/28] drm/mediatek: add component DSI3 Stu Hsieh
2018-06-13 5:31 ` CK Hu
2018-06-11 3:26 ` [PATCH 10/28] drm/mediatek: add connection from OD1 to RDMA1 Stu Hsieh
2018-06-11 3:26 ` [PATCH 11/28] drm/mediatek: add connection from RDMA0 to DPI0 Stu Hsieh
2018-06-13 5:38 ` CK Hu
2018-06-11 3:26 ` [PATCH 12/28] drm/mediatek: add connection from RDMA0 to DSI2 Stu Hsieh
2018-06-13 5:39 ` CK Hu
2018-06-11 3:26 ` [PATCH 13/28] drm/mediatek: add connection from RDMA0 to DSI3 Stu Hsieh
2018-06-13 5:45 ` CK Hu
2018-06-13 7:46 ` Stu Hsieh
2018-06-13 8:05 ` CK Hu
2018-06-13 8:52 ` Stu Hsieh
2018-06-11 3:26 ` [PATCH 14/28] drm/mediatek: add connection from RDMA1 to DPI1 Stu Hsieh
2018-06-13 6:13 ` CK Hu
2018-06-13 7:56 ` Stu Hsieh
2018-06-13 8:27 ` CK Hu
2018-06-13 8:53 ` Stu Hsieh
2018-06-11 3:26 ` [PATCH 15/28] drm/mediatek: add connection from RDMA1 to DSI1 Stu Hsieh
2018-06-13 6:44 ` CK Hu
2018-06-13 6:59 ` CK Hu
2018-06-11 3:26 ` [PATCH 16/28] drm/mediatek: add connection from RDMA1 to DSI2 Stu Hsieh
2018-06-13 7:00 ` CK Hu
2018-06-11 3:26 ` [PATCH 17/28] drm/mediatek: add connection from RDMA1 to DSI3 Stu Hsieh
2018-06-13 7:04 ` CK Hu
2018-06-11 3:26 ` [PATCH 18/28] drm/mediatek: add connection from RDMA2 to DPI0 Stu Hsieh
2018-06-13 7:07 ` CK Hu
2018-06-11 3:26 ` [PATCH 19/28] drm/mediatek: add connection from RDMA2 to DPI1 Stu Hsieh
2018-06-13 7:13 ` CK Hu
2018-06-13 8:01 ` Stu Hsieh
2018-06-13 8:14 ` CK Hu
2018-06-13 8:58 ` Stu Hsieh
2018-06-13 9:01 ` CK Hu
2018-06-11 3:26 ` [PATCH 20/28] drm/mediatek: add connection from RDMA2 to DSI1 Stu Hsieh
2018-06-13 7:17 ` CK Hu
2018-06-11 3:26 ` [PATCH 21/28] drm/mediatek: add connection from RDMA2 to DSI2 Stu Hsieh
2018-06-13 7:18 ` CK Hu
2018-06-11 3:26 ` [PATCH 22/28] drm/mediatek: add connection from RDMA2 to DSI3 Stu Hsieh
2018-06-13 7:19 ` CK Hu
2018-06-11 3:26 ` [PATCH 23/28] drm/mediatek: add DPI1 support for mutex Stu Hsieh
2018-06-13 7:22 ` CK Hu
2018-06-11 3:26 ` [PATCH 24/28] drm/mediatek: add DSI2 " Stu Hsieh
2018-06-13 7:22 ` CK Hu
2018-06-11 3:26 ` [PATCH 25/28] drm/mediatek: add DSI3 " Stu Hsieh
2018-06-13 7:22 ` CK Hu
2018-06-11 3:26 ` [PATCH 26/28] drm/mediatek: add DPI1/DSI1/DSI2/DSI3 in comp_init Stu Hsieh
2018-06-13 7:35 ` CK Hu
2018-06-13 8:05 ` Stu Hsieh
2018-06-11 3:26 ` [PATCH 27/28] drm/mediatek: add third ddp path Stu Hsieh
2018-06-13 7:38 ` CK Hu
2018-06-11 3:26 ` [PATCH 28/28] drm/mediatek: Add support for mediatek SOC MT2712 Stu Hsieh
2018-06-13 7:48 ` CK Hu
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