From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michel Pollet Subject: [PATCH v9 2/5] dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation Date: Thu, 14 Jun 2018 11:56:31 +0100 Message-ID: <1528973829-25493-3-git-send-email-michel.pollet@bp.renesas.com> References: <1528973829-25493-1-git-send-email-michel.pollet@bp.renesas.com> Return-path: In-Reply-To: <1528973829-25493-1-git-send-email-michel.pollet@bp.renesas.com> Sender: linux-kernel-owner@vger.kernel.org To: linux-renesas-soc@vger.kernel.org, Simon Horman Cc: phil.edworthy@renesas.com, Michel Pollet , Michel Pollet , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Geert Uytterhoeven , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: devicetree@vger.kernel.org The Renesas R9A06G032 SYSCTRL node description. Signed-off-by: Michel Pollet --- .../bindings/clock/renesas,r9a06g032-sysctrl.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt new file mode 100644 index 0000000..f6cb5e3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt @@ -0,0 +1,44 @@ +* Renesas R9A06G032 SYSCTRL + +Required Properties: + + - compatible: Must be: + - "renesas,r9a06g032-sysctrl" + - reg: Base address and length of the SYSCTRL IO block. + - #clock-cells: Must be 1 + - clocks: References to the parent clocks: + - external 40mhz crystal. + - external (optional) 32.768khz + - external (optional) jtag input + - external (optional) RGMII_REFCLK + - clock-names: Must be: + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + +Examples +-------- + + - SYSCTRL node: + + sysctrl: system-controller@4000c000 { + compatible = "renesas,r9a06g032-sysctrl"; + reg = <0x4000c000 0x1000>; + status = "okay"; + #clock-cells = <1>; + + clocks = <&ext_mclk>, <&ext_rtc_clk>, + <&ext_jtag_clk>, <&ext_rgmii_ref>; + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + }; + + - Other nodes can use the clocks provided by SYSCTRL as in: + + #include + uart0: serial@40060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x40060000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART0>; + clock-names = "baudclk"; + }; -- 2.7.4