From mboxrd@z Thu Jan 1 00:00:00 1970 From: Elaine Zhang Subject: [PATCH v3 0/4] clk: rockchip: support clock controller for px30 SoC Date: Fri, 15 Jun 2018 10:16:47 +0800 Message-ID: <1529029011-15021-1-git-send-email-zhangqing@rock-chips.com> Return-path: Sender: linux-kernel-owner@vger.kernel.org To: heiko@sntech.de Cc: sboyd@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, mturquette@baylibre.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, cl@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com, Elaine Zhang List-Id: devicetree@vger.kernel.org Change in V3: [PATCH v3 1/4]: Correct description [PATCH v3 2/4]: Use an SPDX tag instead. [PATCH v3 3/4]: Use an SPDX tag instead, parent_rate might overflow and fix it. fix up the checkpatch warning. add more CMPOSITE_xxx_HALFdiv. Change in V2: [PATCH v2 2/4]: modify the Author name [PATCH v2 3/4]: provide a bit more explanation for commit message Elaine Zhang (4): dt-bindings: add bindings for px30 clock controller clk: rockchip: add dt-binding header for px30 clk: rockchip: add support for half divider clk: rockchip: add clock controller for px30 .../bindings/clock/rockchip,px30-cru.txt | 66 ++ drivers/clk/rockchip/Makefile | 2 + drivers/clk/rockchip/clk-half-divider.c | 231 +++++ drivers/clk/rockchip/clk-px30.c | 1080 ++++++++++++++++++++ drivers/clk/rockchip/clk.c | 10 + drivers/clk/rockchip/clk.h | 126 ++- include/dt-bindings/clock/px30-cru.h | 389 +++++++ 7 files changed, 1903 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt create mode 100644 drivers/clk/rockchip/clk-half-divider.c create mode 100644 drivers/clk/rockchip/clk-px30.c create mode 100644 include/dt-bindings/clock/px30-cru.h -- 1.9.1