From mboxrd@z Thu Jan 1 00:00:00 1970 From: Abel Vesa Subject: [PATCH v4 1/2] dt-bindings: add binding for i.MX8MQ IOMUXC Date: Wed, 20 Jun 2018 15:23:48 +0300 Message-ID: <1529497429-8576-2-git-send-email-abel.vesa@nxp.com> References: <1529497429-8576-1-git-send-email-abel.vesa@nxp.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1529497429-8576-1-git-send-email-abel.vesa@nxp.com> Sender: linux-kernel-owner@vger.kernel.org To: Lucas Stach , Dong Aisheng Cc: linux-gpio@vger.kernel.org, linux-imx@nxp.com, Shawn Guo , Pengutronix Kernel Team , Linus Walleij , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Abel Vesa List-Id: devicetree@vger.kernel.org This adds the binding for the i.MX8MQ pin controller, in the same fashion as earlier i.MX SoCs. Signed-off-by: Abel Vesa --- .../bindings/pinctrl/fsl,imx8mq-pinctrl.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt new file mode 100644 index 0000000..f11a3f0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt @@ -0,0 +1,29 @@ +* Freescale IMX8MQ IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory +for common binding part and usage. + +Required properties: +- compatible: "fsl,imx8mq-iomuxc" +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in + imx8mq-pinfunc.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX8M Quad + Reference Manual for detailed CONFIG settings. + +Examples: + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + >; + }; +}; -- 2.7.4