[PATCH 0/3] clk: meson: add a sub EMMC clock controller support

[PATCH 0/3] clk: meson: add a sub EMMC clock controller support

[Yixun Lan]

This driver will add a EMMC clock controller driver support.
The original idea about adding a clock controller is during the
discussion in the NAND driver mainline effort[1].

I've tested this in the S400 board (AXG platform) by using NAND driver.

[1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13

Yixun Lan (3):
  clk: meson: add DT documentation for emmc clock controller
  clk: meson: add sub EMMC clock dt-bindings IDs
  clk: meson: add sub EMMC clock controller driver

 .../bindings/clock/amlogic,emmc-clkc.txt      |  45 ++++++
 drivers/clk/meson/Kconfig                     |   9 ++
 drivers/clk/meson/Makefile                    |   1 +
 drivers/clk/meson/emmc-clkc.c                 | 136 ++++++++++++++++++
 include/dt-bindings/clock/emmc-clkc.h         |  14 ++
 5 files changed, 205 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt
 create mode 100644 drivers/clk/meson/emmc-clkc.c
 create mode 100644 include/dt-bindings/clock/emmc-clkc.h

-- 
2.18.0

Re: [PATCH 0/3] clk: meson: add a sub EMMC clock controller support

[Boris Brezillon]

On Tue, 3 Jul 2018 14:57:13 +0000
Yixun Lan <yixun.lan@amlogic.com> wrote:

> This driver will add a EMMC clock controller driver support.
> The original idea about adding a clock controller is during the
> discussion in the NAND driver mainline effort[1].
> 
> I've tested this in the S400 board (AXG platform) by using NAND driver.
> 
> [1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13

This is much better :-).

> 
> Yixun Lan (3):
>   clk: meson: add DT documentation for emmc clock controller
>   clk: meson: add sub EMMC clock dt-bindings IDs
>   clk: meson: add sub EMMC clock controller driver
> 
>  .../bindings/clock/amlogic,emmc-clkc.txt      |  45 ++++++
>  drivers/clk/meson/Kconfig                     |   9 ++
>  drivers/clk/meson/Makefile                    |   1 +
>  drivers/clk/meson/emmc-clkc.c                 | 136 ++++++++++++++++++
>  include/dt-bindings/clock/emmc-clkc.h         |  14 ++
>  5 files changed, 205 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt
>  create mode 100644 drivers/clk/meson/emmc-clkc.c
>  create mode 100644 include/dt-bindings/clock/emmc-clkc.h
> 

[PATCH 1/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

Document the EMMC sub clock controller driver, the potential consumer
of this driver is EMMC or NAND.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 .../bindings/clock/amlogic,emmc-clkc.txt      | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt

diff --git a/Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt
new file mode 100644
index 000000000000..5534bd446363
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt
@@ -0,0 +1,45 @@
+* Amlogic EMMC Sub Clock Controller Driver
+
+The Amlogic EMMC clock controller generates and supplies clock to support
+EMMC and NAND controller
+
+Required Properties:
+
+- compatible: should be:
+		"amlogic,emmc-clkc"
+
+- #clock-cells: should be 1.
+
+Two clocks are provided as the parent of this EMMC clock controller driver from
+upper layer clock controller - eg "amlogic,axg-clkc" in AXG platfrom.
+The main consumer of this driver is EMMC or NAND, to specify which the clock
+they may consume, the preprocessor macros in the dt-bindings/clock/emmc-clkc.h
+header and can be used in device tree sources.
+
+Parent node should have the following properties :
+- compatible: "syscon", "simple-mfd, and "amlogic,emmc-clkc"
+- reg: base address and size of the EMMC control register space.
+
+Example: Clock controller node:
+
+sd_emmc_c_clkc: clock-controller@7000 {
+	compatible = "amlogic,emmc-clkc", "syscon", "simple-mfd";
+	reg = <0x0 0x7000 0x0 0x4>;
+	#clock-cells = <1>;
+
+	clock-names = "clkin0", "clkin1";
+	clocks = <&clkc CLKID_SD_EMMC_C_CLK0>,
+			<&clkc CLKID_FCLK_DIV2>;
+};
+
+Example: NAND controller node that consumes the clock generated by the clock
+  controller:
+
+	nand: nfc@7800 {
+		compatible = "amlogic,meson-axg-nfc";
+		reg = <0x0 0x7800 0x0 0x100>;
+		interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
+		clocks = <&clkc CLKID_SD_EMMC_C>,
+				<&sd_emmc_c_clkc CLKID_EMMC_C_DIV>;
+		clock-names = "core", "device";
+	};
-- 
2.18.0

Re: [PATCH 1/3] clk: meson: add DT documentation for emmc clock controller

[Jerome Brunet]

On Tue, 2018-07-03 at 14:57 +0000, Yixun Lan wrote:
> Document the EMMC sub clock controller driver, the potential consumer
> of this driver is EMMC or NAND.
> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  .../bindings/clock/amlogic,emmc-clkc.txt      | 45 +++++++++++++++++++
>  1 file changed, 45 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt
> new file mode 100644
> index 000000000000..5534bd446363
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt
> @@ -0,0 +1,45 @@
> +* Amlogic EMMC Sub Clock Controller Driver
> +
> +The Amlogic EMMC clock controller generates and supplies clock to support
> +EMMC and NAND controller
> +
> +Required Properties:
> +
> +- compatible: should be:
> +		"amlogic,emmc-clkc"

missing clocks and clock-names here

> +
> +- #clock-cells: should be 1.
> +
> +Two clocks are provided as the parent of this EMMC clock controller driver from
> +upper layer clock controller - eg "amlogic,axg-clkc" in AXG platfrom.
> +The main consumer of this driver is EMMC or NAND, to specify which the clock
> +they may consume, the preprocessor macros in the dt-bindings/clock/emmc-clkc.h
> +header and can be used in device tree sources.

Not sure this explanation belongs in dt-binding documentation.
Maybe this should be in the driver itself.

> +
> +Parent node should have the following properties :
> +- compatible: "syscon", "simple-mfd, and "amlogic,emmc-clkc"
> +- reg: base address and size of the EMMC control register space.
> +
> +Example: Clock controller node:
> +
> +sd_emmc_c_clkc: clock-controller@7000 {
> +	compatible = "amlogic,emmc-clkc", "syscon", "simple-mfd";
> +	reg = <0x0 0x7000 0x0 0x4>;
> +	#clock-cells = <1>;
> +
> +	clock-names = "clkin0", "clkin1";
> +	clocks = <&clkc CLKID_SD_EMMC_C_CLK0>,
> +			<&clkc CLKID_FCLK_DIV2>;
> +};
> +

Not sure the following is necessary, you don't really to show how to use a clock
controller.

> +Example: NAND controller node that consumes the clock generated by the clock
> +  controller:
> +
> +	nand: nfc@7800 {
> +		compatible = "amlogic,meson-axg-nfc";
> +		reg = <0x0 0x7800 0x0 0x100>;
> +		interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
> +		clocks = <&clkc CLKID_SD_EMMC_C>,
> +				<&sd_emmc_c_clkc CLKID_EMMC_C_DIV>;
> +		clock-names = "core", "device";
> +	};

Re: [PATCH 1/3] clk: meson: add DT documentation for emmc clock controller

[Yixun Lan]

Hi jerome

On 07/03/18 16:16, Jerome Brunet wrote:
> On Tue, 2018-07-03 at 14:57 +0000, Yixun Lan wrote:
>> Document the EMMC sub clock controller driver, the potential consumer
>> of this driver is EMMC or NAND.
>>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>> ---
>>  .../bindings/clock/amlogic,emmc-clkc.txt      | 45 +++++++++++++++++++
>>  1 file changed, 45 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt
>> new file mode 100644
>> index 000000000000..5534bd446363
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,emmc-clkc.txt
>> @@ -0,0 +1,45 @@
>> +* Amlogic EMMC Sub Clock Controller Driver
>> +
>> +The Amlogic EMMC clock controller generates and supplies clock to support
>> +EMMC and NAND controller
>> +
>> +Required Properties:
>> +
>> +- compatible: should be:
>> +		"amlogic,emmc-clkc"
> 
> missing clocks and clock-names here
> 
ok, will update

>> +
>> +- #clock-cells: should be 1.
>> +
>> +Two clocks are provided as the parent of this EMMC clock controller driver from
>> +upper layer clock controller - eg "amlogic,axg-clkc" in AXG platfrom.
>> +The main consumer of this driver is EMMC or NAND, to specify which the clock
>> +they may consume, the preprocessor macros in the dt-bindings/clock/emmc-clkc.h
>> +header and can be used in device tree sources.
> 
> Not sure this explanation belongs in dt-binding documentation.
> Maybe this should be in the driver itself.
> 
ok, I probably will waiting for more comments coming in ;-)

>> +
>> +Parent node should have the following properties :
>> +- compatible: "syscon", "simple-mfd, and "amlogic,emmc-clkc"
>> +- reg: base address and size of the EMMC control register space.
>> +
>> +Example: Clock controller node:
>> +
>> +sd_emmc_c_clkc: clock-controller@7000 {
>> +	compatible = "amlogic,emmc-clkc", "syscon", "simple-mfd";
>> +	reg = <0x0 0x7000 0x0 0x4>;
>> +	#clock-cells = <1>;
>> +
>> +	clock-names = "clkin0", "clkin1";
>> +	clocks = <&clkc CLKID_SD_EMMC_C_CLK0>,
>> +			<&clkc CLKID_FCLK_DIV2>;
>> +};
>> +
> 
> Not sure the following is necessary, you don't really to show how to use a clock
> controller.
> 
ditto,

and I'm fine with either way, this was a copy & paste from gxbb-clkc.h


>> +Example: NAND controller node that consumes the clock generated by the clock
>> +  controller:
>> +
>> +	nand: nfc@7800 {
>> +		compatible = "amlogic,meson-axg-nfc";
>> +		reg = <0x0 0x7800 0x0 0x100>;
>> +		interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
>> +		clocks = <&clkc CLKID_SD_EMMC_C>,
>> +				<&sd_emmc_c_clkc CLKID_EMMC_C_DIV>;
>> +		clock-names = "core", "device";
>> +	};
> 
> .
> 

[PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs

[Yixun Lan]

Add two clock bindings IDs which provided by the EMMC clock controller,
These two clocks will be used by EMMC or NAND driver.

Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 include/dt-bindings/clock/emmc-clkc.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 include/dt-bindings/clock/emmc-clkc.h

diff --git a/include/dt-bindings/clock/emmc-clkc.h b/include/dt-bindings/clock/emmc-clkc.h
new file mode 100644
index 000000000000..d9972c400e58
--- /dev/null
+++ b/include/dt-bindings/clock/emmc-clkc.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson EMMC sub clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __EMMC_CLKC_H
+#define __EMMC_CLKC_H
+
+#define CLKID_EMMC_C_MUX				0
+#define CLKID_EMMC_C_DIV				1
+
+#endif
-- 
2.18.0

Re: [PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs

[Boris Brezillon]

On Tue, 3 Jul 2018 14:57:15 +0000
Yixun Lan <yixun.lan@amlogic.com> wrote:

> Add two clock bindings IDs which provided by the EMMC clock controller,
> These two clocks will be used by EMMC or NAND driver.
> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  include/dt-bindings/clock/emmc-clkc.h | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>  create mode 100644 include/dt-bindings/clock/emmc-clkc.h
> 
> diff --git a/include/dt-bindings/clock/emmc-clkc.h b/include/dt-bindings/clock/emmc-clkc.h
> new file mode 100644
> index 000000000000..d9972c400e58
> --- /dev/null
> +++ b/include/dt-bindings/clock/emmc-clkc.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Meson EMMC sub clock tree IDs
> + *
> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> + */
> +
> +#ifndef __EMMC_CLKC_H
> +#define __EMMC_CLKC_H
> +
> +#define CLKID_EMMC_C_MUX				0

Looks like the MUX clk is the parent of the DIV one, and I guess the clk
driver is able to select the best parent+div pair for a requested rate.
Do you really need to expose the MUX to users?

> +#define CLKID_EMMC_C_DIV				1
> +
> +#endif

Re: [PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs

[Yixun Lan]

Hi Broris

 thanks for your quick response, and see my comments below

On 07/03/18 15:21, Boris Brezillon wrote:
> On Tue, 3 Jul 2018 14:57:15 +0000
> Yixun Lan <yixun.lan@amlogic.com> wrote:
> 
>> Add two clock bindings IDs which provided by the EMMC clock controller,
>> These two clocks will be used by EMMC or NAND driver.
>>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>> ---
>>  include/dt-bindings/clock/emmc-clkc.h | 14 ++++++++++++++
>>  1 file changed, 14 insertions(+)
>>  create mode 100644 include/dt-bindings/clock/emmc-clkc.h
>>
>> diff --git a/include/dt-bindings/clock/emmc-clkc.h b/include/dt-bindings/clock/emmc-clkc.h
>> new file mode 100644
>> index 000000000000..d9972c400e58
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/emmc-clkc.h
>> @@ -0,0 +1,14 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Meson EMMC sub clock tree IDs
>> + *
>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +#ifndef __EMMC_CLKC_H
>> +#define __EMMC_CLKC_H
>> +
>> +#define CLKID_EMMC_C_MUX				0
> 
> Looks like the MUX clk is the parent of the DIV one, and I guess the clk
> driver is able to select the best parent+div pair for a requested rate.
> Do you really need to expose the MUX to users?
> 

Yes, It's true, the mux is parent of the div clock.

while testing for the NAND driver, I find it's kind of loose about the
parent of the clock, so selecting the div (and let CCF decide freely) is
actually works fine

but for the EMMC driver, especially when running at high clock, it's
kind of picky about the parent of the clock, so the driver may want to
manually choose the parent of the mux clock (example fclk_div2 here).
That's why I'm exporting this clock ID.


>> +#define CLKID_EMMC_C_DIV				1
>> +
>> +#endif
> 
> .
> 

Re: [PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs

[Jerome Brunet]

On Tue, 2018-07-03 at 15:36 +0800, Yixun Lan wrote:
> Hi Broris
> 
>  thanks for your quick response, and see my comments below
> 
> On 07/03/18 15:21, Boris Brezillon wrote:
> > On Tue, 3 Jul 2018 14:57:15 +0000
> > Yixun Lan <yixun.lan@amlogic.com> wrote:
> > 
> > > Add two clock bindings IDs which provided by the EMMC clock controller,
> > > These two clocks will be used by EMMC or NAND driver.
> > > 
> > > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> > > ---
> > >  include/dt-bindings/clock/emmc-clkc.h | 14 ++++++++++++++
> > >  1 file changed, 14 insertions(+)
> > >  create mode 100644 include/dt-bindings/clock/emmc-clkc.h
> > > 
> > > diff --git a/include/dt-bindings/clock/emmc-clkc.h b/include/dt-bindings/clock/emmc-clkc.h
> > > new file mode 100644
> > > index 000000000000..d9972c400e58
> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/emmc-clkc.h
> > > @@ -0,0 +1,14 @@
> > > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> > > +/*
> > > + * Meson EMMC sub clock tree IDs
> > > + *
> > > + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> > > + */
> > > +
> > > +#ifndef __EMMC_CLKC_H
> > > +#define __EMMC_CLKC_H
> > > +
> > > +#define CLKID_EMMC_C_MUX				0
> > 
> > Looks like the MUX clk is the parent of the DIV one, and I guess the clk
> > driver is able to select the best parent+div pair for a requested rate.
> > Do you really need to expose the MUX to users?
> > 
> 
> Yes, It's true, the mux is parent of the div clock.
> 
> while testing for the NAND driver, I find it's kind of loose about the
> parent of the clock, so selecting the div (and let CCF decide freely) is
> actually works fine
> 
> but for the EMMC driver, especially when running at high clock, it's
> kind of picky about the parent of the clock, 

It would be nice to get an explanation about this behavior.
it seems that even of the rate provided by CLKID_SD_EMMC_X_CLK0 (main clock
controller) is correct, the eMMC cannot reliably tune with it.

Could you elaborate on this ?

> so the driver may want to
> manually choose the parent of the mux clock (example fclk_div2 here).
> That's why I'm exporting this clock ID.

ATM the EMMC driver will not use this provider. If this is the only reason, it
could be done later.

Is the NAND driver "picky" as well ?

> 
> 
> > > +#define CLKID_EMMC_C_DIV				1
> > > +
> > > +#endif
> > 
> > .
> > 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs

[Yixun Lan]

Hi Jerome:


On 07/03/18 16:09, Jerome Brunet wrote:
> On Tue, 2018-07-03 at 15:36 +0800, Yixun Lan wrote:
>> Hi Broris
>>
>>  thanks for your quick response, and see my comments below
>>
>> On 07/03/18 15:21, Boris Brezillon wrote:
>>> On Tue, 3 Jul 2018 14:57:15 +0000
>>> Yixun Lan <yixun.lan@amlogic.com> wrote:
>>>
>>>> Add two clock bindings IDs which provided by the EMMC clock controller,
>>>> These two clocks will be used by EMMC or NAND driver.
>>>>
>>>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>>>> ---
>>>>  include/dt-bindings/clock/emmc-clkc.h | 14 ++++++++++++++
>>>>  1 file changed, 14 insertions(+)
>>>>  create mode 100644 include/dt-bindings/clock/emmc-clkc.h
>>>>
>>>> diff --git a/include/dt-bindings/clock/emmc-clkc.h b/include/dt-bindings/clock/emmc-clkc.h
>>>> new file mode 100644
>>>> index 000000000000..d9972c400e58
>>>> --- /dev/null
>>>> +++ b/include/dt-bindings/clock/emmc-clkc.h
>>>> @@ -0,0 +1,14 @@
>>>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>>>> +/*
>>>> + * Meson EMMC sub clock tree IDs
>>>> + *
>>>> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
>>>> + */
>>>> +
>>>> +#ifndef __EMMC_CLKC_H
>>>> +#define __EMMC_CLKC_H
>>>> +
>>>> +#define CLKID_EMMC_C_MUX				0
>>>
>>> Looks like the MUX clk is the parent of the DIV one, and I guess the clk
>>> driver is able to select the best parent+div pair for a requested rate.
>>> Do you really need to expose the MUX to users?
>>>
>>
>> Yes, It's true, the mux is parent of the div clock.
>>
>> while testing for the NAND driver, I find it's kind of loose about the
>> parent of the clock, so selecting the div (and let CCF decide freely) is
>> actually works fine
>>
>> but for the EMMC driver, especially when running at high clock, it's
>> kind of picky about the parent of the clock, 
> 
> It would be nice to get an explanation about this behavior.
> it seems that even of the rate provided by CLKID_SD_EMMC_X_CLK0 (main clock
> controller) is correct, the eMMC cannot reliably tune with it.
> 
> Could you elaborate on this ?
> 
It's during my own test in AXG platform, I found clock path
a) fclk_div2 -> sd_emmc_c_clk0_sel -> sd_emmc_c_clk0_div ->
sd_emmc_c_clk0 -> sd_emmc_c_mux -> sd_emmc_c_div

b) fclk_div2 -> sd_emmc_c_mux -> sd_emmc_c_div

path a) doesn't work in EMMC driver, even both clock parent of them from
the same fclk_div2 source.

 sd_emmc_c_mux -> sd_emmc_c_div is the clock from the EMMC register base.
I believe it's ASIC design issue

>> so the driver may want to
>> manually choose the parent of the mux clock (example fclk_div2 here).
>> That's why I'm exporting this clock ID.
> 
> ATM the EMMC driver will not use this provider. If this is the only reason, it
> could be done later.
> 
sure, I'm fine with this.. we could certainly adjust it later.

I will fix this in next patch version

> Is the NAND driver "picky" as well ?
> 
No, since the NAND is running at much low clock speed, and during my
tests, it works fine with various clock parent

>>
>>
>>>> +#define CLKID_EMMC_C_DIV				1
>>>> +
>>>> +#endif
>>>
>>> .
>>>
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> .
> 

Re: [PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs

[Jerome Brunet]

On Tue, 2018-07-03 at 17:56 +0800, Yixun Lan wrote:
> > > Yes, It's true, the mux is parent of the div clock.
> > > 
> > > while testing for the NAND driver, I find it's kind of loose about the
> > > parent of the clock, so selecting the div (and let CCF decide freely) is
> > > actually works fine
> > > 
> > > but for the EMMC driver, especially when running at high clock, it's
> > > kind of picky about the parent of the clock, 
> > 
> > It would be nice to get an explanation about this behavior.
> > it seems that even of the rate provided by CLKID_SD_EMMC_X_CLK0 (main clock
> > controller) is correct, the eMMC cannot reliably tune with it.
> > 
> > Could you elaborate on this ?
> > 
> 
> It's during my own test in AXG platform, I found clock path
> a) fclk_div2 -> sd_emmc_c_clk0_sel -> sd_emmc_c_clk0_div ->
> sd_emmc_c_clk0 -> sd_emmc_c_mux -> sd_emmc_c_div
> 
> b) fclk_div2 -> sd_emmc_c_mux -> sd_emmc_c_div
> 
> path a) doesn't work in EMMC driver, even both clock parent of them from
> the same fclk_div2 source.
> 
>  sd_emmc_c_mux -> sd_emmc_c_div is the clock from the EMMC register base.
> I believe it's ASIC design issue

yes Yixun, I did the same test. What I meant with this question is: could you
confirm there a problem with this clock, and what it is exactly so we can adjust
the clock as necessary.

If FDIV2 entry to this clock is broken, maybe it should be removed.