* Re: [PATCH 1/2] dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation
2018-07-05 21:46 [PATCH 1/2] dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation Girish Mahadevan
@ 2018-07-10 15:03 ` Stephen Boyd
2018-07-16 22:27 ` Rob Herring
2018-07-17 22:19 ` Doug Anderson
2 siblings, 0 replies; 4+ messages in thread
From: Stephen Boyd @ 2018-07-10 15:03 UTC (permalink / raw)
To: broonie, devicetree, linux-kernel, linux-spi, mark.rutland,
robh+dt
Cc: Girish Mahadevan, dianders, sdharia, kramasub, linux-arm-msm
Quoting Girish Mahadevan (2018-07-05 14:46:41)
> Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
> ---
> .../devicetree/bindings/spi/qcom,spi-qcom-qspi.txt | 36 ++++++++++++++++++++++
> err.txt | 27 ----------------
> 2 files changed, 36 insertions(+), 27 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
> delete mode 100644 err.txt
>
> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
> new file mode 100644
> index 0000000..3baa893
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
> @@ -0,0 +1,36 @@
> +QTI [Qualcomm Technologies Inc] Quad Serial Peripheral Interface (QSPI)
Just write out the TLA?
> +
> +QSPI [Quad Serial Peripheral Interface] allows single dual and quad read/write
> +access to slaves. QTI's QSPI controller implements the QSPI protocol to interface
This QSPI controller?
> +with slaves like NOR Flash devices.
> +
> +Required properties:
> +- compatible: Should contain:
> + "qcom,qspi-v1"
> +- reg: Contains the base register location and length
> +- interrupts: Interrupt number used by the controller.
> +- clocks: Contains the core and AHB clock names.
> +- clock-names: "core" for core clock and "iface" for AHB clock.
> +- spi-max-frequency: Maximum SPI core clock frequency in Hz.
> +
> +SPI slave nodes must be children of the SPI master node and can contain
> +properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
> +
> +Example:
> +
> + qspi: qspi@7418000 {
> + compatible = "qcom,qspi-v1";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x7418000 0x600>;
> + interrupts = <0 459 0>;
> + clock-names = "iface", "core";
> + clocks = <&clock_gcc clk_gcc_qspi_ahb_clk>,
> + <&clock_gcc clk_gcc_qspi_ser_clk>;
> +
> + device@0 {
> + compatible = "dummy_device";
> + reg = <x>; /* CS for the device */
> + spi-max-frequency = <f>; /* Max supported frequency of the slave (Hz) */
> + };
> + };
> diff --git a/err.txt b/err.txt
> deleted file mode 100644
> index 09000e4..0000000
This part of the patch shouldn't be here.
> --- a/err.txt
> +++ /dev/null
> @@ -1,27 +0,0 @@
> -Skipping hidl generation
> -arch/arm64/Makefile:23: ld does not support --fix-cortex-a53-843419; kernel may be susceptible to erratum
> -arch/arm64/Makefile:44: Detected assembler with broken .inst; disassembly will be unreliable
> - CHK include/config/kernel.release
> - CHK include/generated/uapi/linux/version.h
> - CHK include/generated/utsrelease.h
> - CHK include/generated/bounds.h
> - CHK include/generated/timeconst.h
> - CHK include/generated/asm-offsets.h
> - CALL scripts/checksyscalls.sh
> - CHK scripts/mod/devicetable-offsets.h
> - CHK include/generated/compile.h
> - CHK kernel/config_data.h
> - CC drivers/mtd/devices/m25p80.o
> - AR drivers/mtd/devices/built-in.o
> - AR drivers/mtd/built-in.o
> - CC drivers/spi/spi-mem.o
> -drivers/spi/spi-mem.c:12:23: fatal error: internals.h: No such file or directory
> - #include "internals.h"
> - ^
> -compilation terminated.
> -make[2]: *** [drivers/spi/spi-mem.o] Error 1
> -make[1]: *** [drivers/spi] Error 2
> -make: *** [drivers] Error 2
> -
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH 1/2] dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation
2018-07-05 21:46 [PATCH 1/2] dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation Girish Mahadevan
2018-07-10 15:03 ` Stephen Boyd
@ 2018-07-16 22:27 ` Rob Herring
2018-07-17 22:19 ` Doug Anderson
2 siblings, 0 replies; 4+ messages in thread
From: Rob Herring @ 2018-07-16 22:27 UTC (permalink / raw)
To: Girish Mahadevan
Cc: broonie, mark.rutland, linux-spi, devicetree, linux-kernel,
dianders, swboyd, sdharia, kramasub, linux-arm-msm
On Thu, Jul 05, 2018 at 03:46:41PM -0600, Girish Mahadevan wrote:
> Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
> ---
> .../devicetree/bindings/spi/qcom,spi-qcom-qspi.txt | 36 ++++++++++++++++++++++
> err.txt | 27 ----------------
> 2 files changed, 36 insertions(+), 27 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
> delete mode 100644 err.txt
>
> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
> new file mode 100644
> index 0000000..3baa893
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
> @@ -0,0 +1,36 @@
> +QTI [Qualcomm Technologies Inc] Quad Serial Peripheral Interface (QSPI)
> +
> +QSPI [Quad Serial Peripheral Interface] allows single dual and quad read/write
> +access to slaves. QTI's QSPI controller implements the QSPI protocol to interface
> +with slaves like NOR Flash devices.
> +
> +Required properties:
> +- compatible: Should contain:
> + "qcom,qspi-v1"
Needs an SoC specific compatible string.
> +- reg: Contains the base register location and length
> +- interrupts: Interrupt number used by the controller.
> +- clocks: Contains the core and AHB clock names.
> +- clock-names: "core" for core clock and "iface" for AHB clock.
> +- spi-max-frequency: Maximum SPI core clock frequency in Hz.
This goes in the slave device nodes.
> +
> +SPI slave nodes must be children of the SPI master node and can contain
> +properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
> +
> +Example:
> +
> + qspi: qspi@7418000 {
> + compatible = "qcom,qspi-v1";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x7418000 0x600>;
> + interrupts = <0 459 0>;
> + clock-names = "iface", "core";
> + clocks = <&clock_gcc clk_gcc_qspi_ahb_clk>,
> + <&clock_gcc clk_gcc_qspi_ser_clk>;
> +
> + device@0 {
> + compatible = "dummy_device";
Why don't you use an actual NOR flash chip here.
> + reg = <x>; /* CS for the device */
It's an example, show a CS#.
> + spi-max-frequency = <f>; /* Max supported frequency of the slave (Hz) */
> + };
> + };
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH 1/2] dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation
2018-07-05 21:46 [PATCH 1/2] dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation Girish Mahadevan
2018-07-10 15:03 ` Stephen Boyd
2018-07-16 22:27 ` Rob Herring
@ 2018-07-17 22:19 ` Doug Anderson
2 siblings, 0 replies; 4+ messages in thread
From: Doug Anderson @ 2018-07-17 22:19 UTC (permalink / raw)
To: Girish Mahadevan
Cc: Mark Brown, Rob Herring, Mark Rutland, linux-spi, devicetree,
LKML, Stephen Boyd, Sagar Dharia, Karthikeyan Ramasubramanian,
linux-arm-msm
Hi,
On Thu, Jul 5, 2018 at 2:46 PM, Girish Mahadevan <girishm@codeaurora.org> wrote:
> Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
> ---
> .../devicetree/bindings/spi/qcom,spi-qcom-qspi.txt | 36 ++++++++++++++++++++++
> err.txt | 27 ----------------
> 2 files changed, 36 insertions(+), 27 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
> delete mode 100644 err.txt
>
> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
> new file mode 100644
> index 0000000..3baa893
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
> @@ -0,0 +1,36 @@
> +QTI [Qualcomm Technologies Inc] Quad Serial Peripheral Interface (QSPI)
> +
> +QSPI [Quad Serial Peripheral Interface] allows single dual and quad read/write
> +access to slaves. QTI's QSPI controller implements the QSPI protocol to interface
> +with slaves like NOR Flash devices.
> +
> +Required properties:
> +- compatible: Should contain:
> + "qcom,qspi-v1"
> +- reg: Contains the base register location and length
> +- interrupts: Interrupt number used by the controller.
> +- clocks: Contains the core and AHB clock names.
> +- clock-names: "core" for core clock and "iface" for AHB clock.
> +- spi-max-frequency: Maximum SPI core clock frequency in Hz.
> +
> +SPI slave nodes must be children of the SPI master node and can contain
> +properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
> +
> +Example:
> +
> + qspi: qspi@7418000 {
> + compatible = "qcom,qspi-v1";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x7418000 0x600>;
> + interrupts = <0 459 0>;
Please use a more proper interrupts example, AKA:
interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "iface", "core";
> + clocks = <&clock_gcc clk_gcc_qspi_ahb_clk>,
> + <&clock_gcc clk_gcc_qspi_ser_clk>;
In upstream I believe that the clock #defines are usually in ALL CAPS.
Maybe good to use that in your example. In the clock patches I'm
hoping to send up for SDM845, for instance, this will be:
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<&gcc GCC_QSPI_CORE_CLK>;
> +
> + device@0 {
> + compatible = "dummy_device";
> + reg = <x>; /* CS for the device */
> + spi-max-frequency = <f>; /* Max supported frequency of the slave (Hz) */
Since you are a Quad SPI controller, maybe you'd want your example to
include how to enable that? AKA:
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
-Doug
^ permalink raw reply [flat|nested] 4+ messages in thread