From: Fabio Estevam <fabio.estevam@nxp.com>
To: shawnguo@kernel.org
Cc: devicetree@vger.kernel.org, Fabio Estevam <fabio.estevam@nxp.com>,
robh+dt@kernel.org, kernel@pengutronix.de,
sebastian.reichel@collabora.co.uk,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 5/6] ARM: dts: imx53: Add a label for the PMU node
Date: Tue, 10 Jul 2018 13:08:46 -0300 [thread overview]
Message-ID: <1531238927-19579-5-git-send-email-fabio.estevam@nxp.com> (raw)
In-Reply-To: <1531238927-19579-1-git-send-email-fabio.estevam@nxp.com>
Add a label for the PMU node so that the board dts may be able to
pass the 'secure-reg-access' property like this:
&pmu {
secure-reg-access;
};
This also makes it consistent with the PMU node in imx6qdl.dtsi
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Tested-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
Changes since v2:
- None
arch/arm/boot/dts/imx53.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 3fd553c..6386185 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -113,7 +113,7 @@
};
};
- pmu {
+ pmu: pmu {
compatible = "arm,cortex-a8-pmu";
interrupt-parent = <&tzic>;
interrupts = <77>;
--
2.7.4
next prev parent reply other threads:[~2018-07-10 16:08 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-10 16:08 [PATCH v3 1/6] dt-bindings: freescale: Add bindings for the tigerp module Fabio Estevam
2018-07-10 16:08 ` [PATCH v3 2/6] ARM: dts: imx51: Add PMU support Fabio Estevam
2018-07-10 16:08 ` [PATCH v3 3/6] ARM: dts: imx51: Add tigerp support Fabio Estevam
2018-07-10 16:08 ` [PATCH v3 4/6] ARM: dts: imx53: " Fabio Estevam
2018-07-10 16:08 ` Fabio Estevam [this message]
2018-07-10 16:08 ` [PATCH v3 6/6] ARM: mx5: Set the DBGEN bit in ARM_GPC register Fabio Estevam
2018-07-10 16:23 ` Sebastian Reichel
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