From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mars Cheng Subject: [PATCH v5 04/11] soc: mediatek: add MT6765 scpsys support Date: Tue, 17 Jul 2018 16:52:25 +0800 Message-ID: <1531817552-17221-5-git-send-email-mars.cheng@mediatek.com> References: <1531817552-17221-1-git-send-email-mars.cheng@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1531817552-17221-1-git-send-email-mars.cheng@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Matthias Brugger , Rob Herring , Marc Zyngier , Ryder Lee , Stephen Boyd , Sean Wang Cc: devicetree@vger.kernel.org, CC Hwang , wsd_upstream@mediatek.com, Loda Chou , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-serial@vger.kernel.org, Mars Cheng , Owen Chen , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org This adds scpsys support for MT6765 Signed-off-by: Mars Cheng Signed-off-by: Owen Chen --- drivers/soc/mediatek/mtk-scpsys.c | 88 ++++++++++++++++++++++++++++++ include/dt-bindings/power/mt6765-power.h | 14 +++++ 2 files changed, 102 insertions(+) create mode 100644 include/dt-bindings/power/mt6765-power.h diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 5b24bb4..4bb6c7a 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -23,6 +23,7 @@ #include #include +#include #include #include #include @@ -680,6 +681,79 @@ static void mtk_register_power_domains(struct platform_device *pdev, }; /* + * MT6765 power domain support + */ +#define SPM_PWR_STATUS_MT6765 0x0180 +#define SPM_PWR_STATUS_2ND_MT6765 0x0184 + +static const struct scp_domain_data scp_domain_data_mt6765[] = { + [MT6765_POWER_DOMAIN_VCODEC] = { + .name = "vcodec", + .sta_mask = BIT(26), + .ctl_offs = 0x300, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT6765_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = BIT(5), + .ctl_offs = 0x308, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT6765_POWER_DOMAIN_MM] = { + .name = "mm", + .sta_mask = BIT(3), + .ctl_offs = 0x30C, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT6765_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = BIT(1), + .ctl_offs = 0x32C, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + }, + [MT6765_POWER_DOMAIN_MFG_ASYNC] = { + .name = "mfg_async", + .sta_mask = BIT(23), + .ctl_offs = 0x334, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + }, + [MT6765_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = BIT(4), + .ctl_offs = 0x338, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT6765_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(25), + .ctl_offs = 0x344, + .sram_pdn_bits = GENMASK(8, 9), + .sram_pdn_ack_bits = GENMASK(12, 13), + }, + [MT6765_POWER_DOMAIN_MFG_CORE0] = { + .name = "mfg_core0", + .sta_mask = BIT(7), + .ctl_offs = 0x34C, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, +}; + +static const struct scp_subdomain scp_subdomain_mt6765[] = { + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM}, + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP}, + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC}, + {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG}, + {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0}, +}; + +/* * MT6797 power domain support */ @@ -962,6 +1036,17 @@ static void mtk_register_power_domains(struct platform_device *pdev, .bus_prot_reg_update = false, }; +static const struct scp_soc_data mt6765_data = { + .domains = scp_domain_data_mt6765, + .num_domains = ARRAY_SIZE(scp_domain_data_mt6765), + .subdomains = scp_subdomain_mt6765, + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765), + .regs = { + .pwr_sta_offs = SPM_PWR_STATUS_MT6765, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765, + }, +}; + static const struct scp_soc_data mt6797_data = { .domains = scp_domain_data_mt6797, .num_domains = ARRAY_SIZE(scp_domain_data_mt6797), @@ -1018,6 +1103,9 @@ static void mtk_register_power_domains(struct platform_device *pdev, .compatible = "mediatek,mt2712-scpsys", .data = &mt2712_data, }, { + .compatible = "mediatek,mt6765-scpsys", + .data = &mt6765_data, + }, { .compatible = "mediatek,mt6797-scpsys", .data = &mt6797_data, }, { diff --git a/include/dt-bindings/power/mt6765-power.h b/include/dt-bindings/power/mt6765-power.h new file mode 100644 index 0000000..d347b4e --- /dev/null +++ b/include/dt-bindings/power/mt6765-power.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_POWER_MT6765_POWER_H +#define _DT_BINDINGS_POWER_MT6765_POWER_H + +#define MT6765_POWER_DOMAIN_CONN 0 +#define MT6765_POWER_DOMAIN_MM 1 +#define MT6765_POWER_DOMAIN_MFG_ASYNC 2 +#define MT6765_POWER_DOMAIN_ISP 3 +#define MT6765_POWER_DOMAIN_MFG 4 +#define MT6765_POWER_DOMAIN_MFG_CORE0 5 +#define MT6765_POWER_DOMAIN_CAM 6 +#define MT6765_POWER_DOMAIN_VCODEC 7 + +#endif /* _DT_BINDINGS_POWER_MT6765_POWER_H */ -- 1.7.9.5