[PATCH v0 0/4] Add cache erp driver for Last Level Cache Controller (LLCC)

[PATCH v0 0/4] Add cache erp driver for Last Level Cache Controller (LLCC)

[Venkata Narendra Kumar Gutta]

This series implements cache erp driver for Last Level Cache Controller 
(LLCC). Cache erp driver is to detect and report single and double bit
errors on Last Level Cache Controller (LLCC) cache. This driver also takes
care of dumping registers and have config options to enable and disable
panic when these errors happen in LLCC.

The driver functionality is implemented in:
qcom_llcc_edac.c : This platform driver registers to edac framework and
handles the single and double bit errors in llcc cache by registering
interrupt handlers. 

llcc-slice.c: It invokes the llcc cache erp driver and passes platform
data to it. 

This patchset depends on the LLCC driver, which is yet to be merged.
Link: https://patchwork.kernel.org/patch/10422531/
Link: Link: http://lists-archives.com/linux-kernel/29157082-dt-bindings-documentation-for-qcom-llcc.html

Venkata Narendra Kumar Gutta (4):
  drivers: soc: Add broadcast base for Last Level Cache Controller
    (LLCC)
  drivers: soc: Support to add cache erp driver for Last Level Cache
    Controller (LLCC)
  drivers: edac: Add cache erp driver for Last Level Cache Controller
    (LLCC)
  dt-bindigs: Update documentation of qcom,llcc

 .../devicetree/bindings/arm/msm/qcom,llcc.txt      |  41 ++
 drivers/edac/Kconfig                               |  21 +
 drivers/edac/Makefile                              |   1 +
 drivers/edac/qcom_llcc_edac.c                      | 523 +++++++++++++++++++++
 drivers/soc/qcom/llcc-slice.c                      |  74 ++-
 include/linux/soc/qcom/llcc-qcom.h                 |   6 +-
 6 files changed, 640 insertions(+), 26 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
 create mode 100644 drivers/edac/qcom_llcc_edac.c

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v0 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC)

[Venkata Narendra Kumar Gutta]

Currently, boradcast base is set to end of the LLCC banks, which may
not be correct always. As the number of banks may vary for each chipset
and the broadcast base could be at a different address as well. This info
depends on the chipset, so get the broadcast base info from the device
tree (DT). Add broadcast base in LLCC driver and use this for broadcast
writes.

Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
 drivers/soc/qcom/llcc-slice.c      | 55 +++++++++++++++++++++++---------------
 include/linux/soc/qcom/llcc-qcom.h |  4 +--
 2 files changed, 35 insertions(+), 24 deletions(-)

diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c
index fcaad1a..a63640d 100644
--- a/drivers/soc/qcom/llcc-slice.c
+++ b/drivers/soc/qcom/llcc-slice.c
@@ -105,22 +105,24 @@ static int llcc_update_act_ctrl(u32 sid,
 	u32 slice_status;
 	int ret;
 
-	act_ctrl_reg = drv_data->bcast_off + LLCC_TRP_ACT_CTRLn(sid);
-	status_reg = drv_data->bcast_off + LLCC_TRP_STATUSn(sid);
+	act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid);
+	status_reg = LLCC_TRP_STATUSn(sid);
 
 	/* Set the ACTIVE trigger */
 	act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG;
-	ret = regmap_write(drv_data->regmap, act_ctrl_reg, act_ctrl_reg_val);
+	ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
+				act_ctrl_reg_val);
 	if (ret)
 		return ret;
 
 	/* Clear the ACTIVE trigger */
 	act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG;
-	ret = regmap_write(drv_data->regmap, act_ctrl_reg, act_ctrl_reg_val);
+	ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
+				act_ctrl_reg_val);
 	if (ret)
 		return ret;
 
-	ret = regmap_read_poll_timeout(drv_data->regmap, status_reg,
+	ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
 				      slice_status, !(slice_status & status),
 				      0, LLCC_STATUS_READ_DELAY);
 	return ret;
@@ -225,16 +227,13 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
 	int ret;
 	const struct llcc_slice_config *llcc_table;
 	struct llcc_slice_desc desc;
-	u32 bcast_off = drv_data->bcast_off;
 
 	sz = drv_data->cfg_size;
 	llcc_table = drv_data->cfg;
 
 	for (i = 0; i < sz; i++) {
-		attr1_cfg = bcast_off +
-				LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
-		attr0_cfg = bcast_off +
-				LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
+		attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
+		attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
 
 		attr1_val = llcc_table[i].cache_mode;
 		attr1_val |= llcc_table[i].probe_target_ways <<
@@ -259,10 +258,12 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
 		attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK;
 		attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
 
-		ret = regmap_write(drv_data->regmap, attr1_cfg, attr1_val);
+		ret = regmap_write(drv_data->bcast_regmap, attr1_cfg,
+					attr1_val);
 		if (ret)
 			return ret;
-		ret = regmap_write(drv_data->regmap, attr0_cfg, attr0_val);
+		ret = regmap_write(drv_data->bcast_regmap, attr0_cfg,
+					attr0_val);
 		if (ret)
 			return ret;
 		if (llcc_table[i].activate_on_init) {
@@ -278,24 +279,36 @@ int qcom_llcc_probe(struct platform_device *pdev,
 {
 	u32 num_banks;
 	struct device *dev = &pdev->dev;
-	struct resource *res;
-	void __iomem *base;
+	struct resource *llcc_banks_res, *llcc_bcast_res;
+	void __iomem *llcc_banks_base, *llcc_bcast_base;
 	int ret, i;
 
 	drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
 	if (!drv_data)
 		return -ENOMEM;
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	base = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
+	llcc_banks_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+							"llcc_base");
+	llcc_banks_base = devm_ioremap_resource(&pdev->dev, llcc_banks_res);
+	if (IS_ERR(llcc_banks_base))
+		return PTR_ERR(llcc_banks_base);
 
-	drv_data->regmap = devm_regmap_init_mmio(dev, base,
-					&llcc_regmap_config);
+	drv_data->regmap = devm_regmap_init_mmio(dev, llcc_banks_base,
+						&llcc_regmap_config);
 	if (IS_ERR(drv_data->regmap))
 		return PTR_ERR(drv_data->regmap);
 
+	llcc_bcast_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+							"llcc_broadcast_base");
+	llcc_bcast_base = devm_ioremap_resource(&pdev->dev, llcc_bcast_res);
+	if (IS_ERR(llcc_bcast_base))
+		return PTR_ERR(llcc_bcast_base);
+
+	drv_data->bcast_regmap = devm_regmap_init_mmio(dev, llcc_bcast_base,
+							&llcc_regmap_config);
+	if (IS_ERR(drv_data->bcast_regmap))
+		return PTR_ERR(drv_data->bcast_regmap);
+
 	ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
 						&num_banks);
 	if (ret)
@@ -317,8 +330,6 @@ int qcom_llcc_probe(struct platform_device *pdev,
 	for (i = 0; i < num_banks; i++)
 		drv_data->offsets[i] = i * BANK_OFFSET_STRIDE;
 
-	drv_data->bcast_off = num_banks * BANK_OFFSET_STRIDE;
-
 	drv_data->bitmap = devm_kcalloc(dev,
 	BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long),
 						GFP_KERNEL);
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 7e3b9c6..c681e79 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -70,22 +70,22 @@ struct llcc_slice_config {
 /**
  * llcc_drv_data - Data associated with the llcc driver
  * @regmap: regmap associated with the llcc device
+ * @bcast_regmap: regmap associated with llcc broadcast offset
  * @cfg: pointer to the data structure for slice configuration
  * @lock: mutex associated with each slice
  * @cfg_size: size of the config data table
  * @max_slices: max slices as read from device tree
- * @bcast_off: Offset of the broadcast bank
  * @num_banks: Number of llcc banks
  * @bitmap: Bit map to track the active slice ids
  * @offsets: Pointer to the bank offsets array
  */
 struct llcc_drv_data {
 	struct regmap *regmap;
+	struct regmap *bcast_regmap;
 	const struct llcc_slice_config *cfg;
 	struct mutex lock;
 	u32 cfg_size;
 	u32 max_slices;
-	u32 bcast_off;
 	u32 num_banks;
 	unsigned long *bitmap;
 	u32 *offsets;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v0 2/4] drivers: soc: Support to add cache erp driver for Last Level Cache Controller (LLCC)

[Venkata Narendra Kumar Gutta]

Cache error reporting controller is to detect and report single
and double bit errors on Last Level Cache Controller (LLCC) cache.
Add required support to register cache erp driver as platform driver,
from LLCC driver.

Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
 drivers/soc/qcom/llcc-slice.c      | 18 ++++++++++++++++--
 include/linux/soc/qcom/llcc-qcom.h |  2 ++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c
index a63640d..9860ef9 100644
--- a/drivers/soc/qcom/llcc-slice.c
+++ b/drivers/soc/qcom/llcc-slice.c
@@ -224,7 +224,7 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
 	u32 attr0_val;
 	u32 max_cap_cacheline;
 	u32 sz;
-	int ret;
+	int ret = 0;
 	const struct llcc_slice_config *llcc_table;
 	struct llcc_slice_desc desc;
 
@@ -282,6 +282,7 @@ int qcom_llcc_probe(struct platform_device *pdev,
 	struct resource *llcc_banks_res, *llcc_bcast_res;
 	void __iomem *llcc_banks_base, *llcc_bcast_base;
 	int ret, i;
+	struct platform_device *llcc_edac;
 
 	drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
 	if (!drv_data)
@@ -341,6 +342,19 @@ int qcom_llcc_probe(struct platform_device *pdev,
 	mutex_init(&drv_data->lock);
 	platform_set_drvdata(pdev, drv_data);
 
-	return qcom_llcc_cfg_program(pdev);
+	ret = qcom_llcc_cfg_program(pdev);
+	if (ret)
+		return ret;
+
+	drv_data->ecc_irq = platform_get_irq(pdev, 0);
+	if (drv_data->ecc_irq >= 0) {
+		llcc_edac = platform_device_register_data(&pdev->dev,
+						"qcom_llcc_erp", -1, drv_data,
+						sizeof(*drv_data));
+		if (IS_ERR(llcc_edac))
+			dev_err(dev, "Failed to register llcc edac driver\n");
+	}
+
+	return ret;
 }
 EXPORT_SYMBOL_GPL(qcom_llcc_probe);
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index c681e79..1a3bc25 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -78,6 +78,7 @@ struct llcc_slice_config {
  * @num_banks: Number of llcc banks
  * @bitmap: Bit map to track the active slice ids
  * @offsets: Pointer to the bank offsets array
+ * @ecc_irq: interrupt for llcc cache error detection and reporting
  */
 struct llcc_drv_data {
 	struct regmap *regmap;
@@ -89,6 +90,7 @@ struct llcc_drv_data {
 	u32 num_banks;
 	unsigned long *bitmap;
 	u32 *offsets;
+	u32 ecc_irq;
 };
 
 #if IS_ENABLED(CONFIG_QCOM_LLCC)
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v0 3/4] drivers: edac: Add cache erp driver for Last Level Cache Controller (LLCC)

[Venkata Narendra Kumar Gutta]

Add cache error reporting driver for single and double bit errors on
Last Level Cache Controller (LLCC) cache. This driver takes care of
dumping registers and add config options to enable and disable panic
when these errors happen.

Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
 drivers/edac/Kconfig          |  21 ++
 drivers/edac/Makefile         |   1 +
 drivers/edac/qcom_llcc_edac.c | 520 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 542 insertions(+)
 create mode 100644 drivers/edac/qcom_llcc_edac.c

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 57304b2..68518ad 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -460,4 +460,25 @@ config EDAC_TI
 	  Support for error detection and correction on the
           TI SoCs.
 
+config EDAC_QCOM_LLCC
+        depends on QCOM_LLCC
+        tristate "QCOM EDAC Controller for LLCC Cache"
+        help
+          Support for error detection and correction on the
+          QCOM LLCC cache. Report errors caught by LLCC ECC
+          mechanism.
+
+          For debugging issues having to do with stability and overall system
+          health, you should probably say 'Y' here.
+
+config EDAC_QCOM_LLCC_PANIC_ON_UE
+        depends on EDAC_QCOM_LLCC
+        bool "Panic on uncorrectable errors - qcom llcc"
+        help
+          Forcibly cause a kernel panic if an uncorrectable error (UE) is
+          detected. This can reduce debugging times on hardware which may be
+          operating at voltages or frequencies outside normal specification.
+
+          For production builds, you should probably say 'N' here.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 02b43a7..28aff28 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)		+= altera_edac.o
 obj-$(CONFIG_EDAC_SYNOPSYS)		+= synopsys_edac.o
 obj-$(CONFIG_EDAC_XGENE)		+= xgene_edac.o
 obj-$(CONFIG_EDAC_TI)			+= ti_edac.o
+obj-$(CONFIG_EDAC_QCOM_LLCC)		+= qcom_llcc_edac.o
diff --git a/drivers/edac/qcom_llcc_edac.c b/drivers/edac/qcom_llcc_edac.c
new file mode 100644
index 0000000..7a678b5
--- /dev/null
+++ b/drivers/edac/qcom_llcc_edac.c
@@ -0,0 +1,520 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/edac.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/smp.h>
+#include <linux/spinlock.h>
+#include <linux/regmap.h>
+#include <linux/interrupt.h>
+#include <linux/soc/qcom/llcc-qcom.h>
+#include "edac_mc.h"
+#include "edac_device.h"
+
+#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
+#define LLCC_ERP_PANIC_ON_UE 1
+#else
+#define LLCC_ERP_PANIC_ON_UE 0
+#endif
+
+#define EDAC_LLCC	"qcom_llcc"
+
+#define TRP_SYN_REG_CNT	6
+
+#define DRP_SYN_REG_CNT	8
+
+#define LLCC_COMMON_STATUS0		0x0003000C
+#define LLCC_LB_CNT_MASK		GENMASK(31, 28)
+#define LLCC_LB_CNT_SHIFT		28
+
+/* single & Double Bit syndrome register offsets */
+#define TRP_ECC_SB_ERR_SYN0		0x0002304C
+#define TRP_ECC_DB_ERR_SYN0		0x00020370
+#define DRP_ECC_SB_ERR_SYN0		0x0004204C
+#define DRP_ECC_DB_ERR_SYN0		0x00042070
+
+/* Error register offsets */
+#define TRP_ECC_ERROR_STATUS1		0x00020348
+#define TRP_ECC_ERROR_STATUS0		0x00020344
+#define DRP_ECC_ERROR_STATUS1		0x00042048
+#define DRP_ECC_ERROR_STATUS0		0x00042044
+
+/* TRP, DRP interrupt register offsets */
+#define DRP_INTERRUPT_STATUS		0x00041000
+#define TRP_INTERRUPT_0_STATUS		0x00020480
+#define DRP_INTERRUPT_CLEAR		0x00041008
+#define DRP_ECC_ERROR_CNTR_CLEAR	0x00040004
+#define TRP_INTERRUPT_0_CLEAR		0x00020484
+#define TRP_ECC_ERROR_CNTR_CLEAR	0x00020440
+
+/* Mask and shift macros */
+#define ECC_DB_ERR_COUNT_MASK	GENMASK(4, 0)
+#define ECC_DB_ERR_WAYS_MASK	GENMASK(31, 16)
+#define ECC_DB_ERR_WAYS_SHIFT	BIT(4)
+
+#define ECC_SB_ERR_COUNT_MASK	GENMASK(23, 16)
+#define ECC_SB_ERR_COUNT_SHIFT	BIT(4)
+#define ECC_SB_ERR_WAYS_MASK	GENMASK(15, 0)
+
+#define SB_ECC_ERROR		BIT(0)
+#define DB_ECC_ERROR		BIT(1)
+
+#define DRP_TRP_INT_CLEAR	GENMASK(1, 0)
+#define DRP_TRP_CNT_CLEAR	GENMASK(1, 0)
+
+/* Config registers offsets*/
+#define DRP_ECC_ERROR_CFG       0x00040000
+
+/* TRP, DRP interrupt register offsets */
+#define CMN_INTERRUPT_0_ENABLE          0x0003001C
+#define CMN_INTERRUPT_2_ENABLE          0x0003003C
+#define TRP_INTERRUPT_0_ENABLE          0x00020488
+#define DRP_INTERRUPT_ENABLE            0x0004100C
+
+#define SB_ERROR_THRESHOLD      0x1
+#define SB_ERROR_THRESHOLD_SHIFT        24
+#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
+#define TRP0_INTERRUPT_ENABLE   0x1
+#define DRP0_INTERRUPT_ENABLE   BIT(6)
+#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
+
+
+enum {
+	LLCC_DRAM_CE = 0,
+	LLCC_DRAM_UE,
+	LLCC_TRAM_CE,
+	LLCC_TRAM_UE,
+};
+
+struct errors_edac {
+	const char *msg;
+	void (*func)(struct edac_device_ctl_info *edev_ctl,
+				int inst_nr, int block_nr, const char *msg);
+};
+
+static const struct errors_edac errors[] = {
+	{"LLCC Data RAM correctable Error", edac_device_handle_ce},
+	{"LLCC Data RAM uncorrectable Error", edac_device_handle_ue},
+	{"LLCC Tag RAM correctable Error", edac_device_handle_ce},
+	{"LLCC Tag RAM uncorrectable Error", edac_device_handle_ue},
+};
+
+static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
+{
+	u32 sb_err_threshold;
+	int ret;
+
+	/* Enable TRP in instance 2 of common interrupt enable register */
+	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
+				TRP0_INTERRUPT_ENABLE,
+				TRP0_INTERRUPT_ENABLE);
+	if (ret)
+		return ret;
+
+	/* Enable ECC interrupts on Tag Ram */
+	ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
+				SB_DB_TRP_INTERRUPT_ENABLE,
+				SB_DB_TRP_INTERRUPT_ENABLE);
+	if (ret)
+		return ret;
+
+	/* Enable SB error for Data RAM */
+	sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
+	ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
+				sb_err_threshold);
+	if (ret)
+		return ret;
+
+	/* Enable DRP in instance 2 of common interrupt enable register */
+	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
+				DRP0_INTERRUPT_ENABLE, DRP0_INTERRUPT_ENABLE);
+	if (ret)
+		return ret;
+
+	/* Enable ECC interrupts on Data Ram */
+	ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
+				SB_DB_DRP_INTERRUPT_ENABLE);
+	return ret;
+}
+
+/* Clear the error interrupt and counter registers */
+static int qcom_llcc_clear_errors(int err_type, struct llcc_drv_data *drv)
+{
+	int ret = 0;
+
+	switch (err_type) {
+	case LLCC_DRAM_CE:
+	case LLCC_DRAM_UE:
+		/* Clear the interrupt */
+		ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
+					DRP_TRP_INT_CLEAR);
+		if (ret)
+			return ret;
+
+		/* Clear the counters */
+		ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
+					DRP_TRP_CNT_CLEAR);
+		if (ret)
+			return ret;
+		break;
+	case LLCC_TRAM_CE:
+	case LLCC_TRAM_UE:
+		ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
+					DRP_TRP_INT_CLEAR);
+		if (ret)
+			return ret;
+
+		ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
+					DRP_TRP_CNT_CLEAR);
+		if (ret)
+			return ret;
+		break;
+	}
+	return ret;
+}
+
+/* Dump syndrome registers for tag Ram Double bit errors */
+static int dump_trp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
+{
+	int i, ret;
+	int db_err_cnt;
+	int db_err_ways;
+	u32 synd_reg;
+	u32 synd_val;
+
+	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
+		synd_reg = TRP_ECC_DB_ERR_SYN0 + (i * 4);
+		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
+				&synd_val);
+		if (ret)
+			return ret;
+		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n",
+			i, synd_val);
+	}
+
+	ret = regmap_read(drv->regmap,
+				drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
+				&db_err_cnt);
+	if (ret)
+		return ret;
+	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
+		db_err_cnt);
+
+	ret = regmap_read(drv->regmap,
+		drv->offsets[bank] + TRP_ECC_ERROR_STATUS0, &db_err_ways);
+	if (ret)
+		return ret;
+	db_err_ways = (db_err_ways & ECC_DB_ERR_WAYS_MASK);
+	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
+
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
+		db_err_ways);
+
+	return ret;
+}
+
+/* Dump syndrome register for tag Ram Single Bit Errors */
+static int dump_trp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
+{
+	int i, ret;
+	int sb_err_cnt;
+	int sb_err_ways;
+	u32 synd_reg;
+	u32 synd_val;
+
+	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
+		synd_reg = TRP_ECC_SB_ERR_SYN0 + (i * 4);
+		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
+					&synd_val);
+		if (ret)
+			return ret;
+		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n",
+				i, synd_val);
+	}
+
+	ret = regmap_read(drv->regmap,
+				drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
+				&sb_err_cnt);
+	if (ret)
+		return ret;
+	sb_err_cnt = (sb_err_cnt & ECC_SB_ERR_COUNT_MASK);
+	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
+		sb_err_cnt);
+
+	ret = regmap_read(drv->regmap,
+				drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
+				&sb_err_ways);
+	if (ret)
+		return ret;
+
+	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
+
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
+			sb_err_ways);
+
+	return ret;
+}
+
+/* Dump syndrome registers for Data Ram Double bit errors */
+static int dump_drp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
+{
+	int i, ret;
+	int db_err_cnt;
+	int db_err_ways;
+	u32 synd_reg;
+	u32 synd_val;
+
+	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
+		synd_reg = DRP_ECC_DB_ERR_SYN0 + (i * 4);
+		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
+					&synd_val);
+		if (ret)
+			return ret;
+		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n",
+				i, synd_val);
+	}
+
+	ret = regmap_read(drv->regmap,
+				drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
+				&db_err_cnt);
+	if (ret)
+		return ret;
+	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
+		db_err_cnt);
+
+	ret = regmap_read(drv->regmap,
+				drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
+				&db_err_ways);
+	if (ret)
+		return ret;
+	db_err_ways &= ECC_DB_ERR_WAYS_MASK;
+	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
+		db_err_ways);
+
+	return ret;
+}
+
+/* Dump Syndrome registers for Data Ram Single bit errors*/
+static int dump_drp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
+{
+	int i, ret;
+	int sb_err_cnt;
+	int sb_err_ways;
+	u32 synd_reg;
+	u32 synd_val;
+
+	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
+		synd_reg = DRP_ECC_SB_ERR_SYN0 + (i * 4);
+		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
+					&synd_val);
+		if (ret)
+			return ret;
+		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n",
+				i, synd_val);
+	}
+
+	ret = regmap_read(drv->regmap,
+				drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
+				&sb_err_cnt);
+	if (ret)
+		return ret;
+	sb_err_cnt &= ECC_SB_ERR_COUNT_MASK;
+	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
+		sb_err_cnt);
+
+	ret = regmap_read(drv->regmap,
+				drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
+				&sb_err_ways);
+	if (ret)
+		return ret;
+	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
+
+	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
+		sb_err_ways);
+
+	return ret;
+}
+
+
+static int dump_syn_reg(struct edac_device_ctl_info *edev_ctl,
+			 int err_type, u32 bank)
+{
+	int ret = 0;
+	struct llcc_drv_data *drv = edev_ctl->pvt_info;
+
+	switch (err_type) {
+	case LLCC_DRAM_CE:
+		ret = dump_drp_sb_syn_reg(drv, bank);
+		break;
+	case LLCC_DRAM_UE:
+		ret = dump_drp_db_syn_reg(drv, bank);
+		break;
+	case LLCC_TRAM_CE:
+		ret = dump_trp_sb_syn_reg(drv, bank);
+		break;
+	case LLCC_TRAM_UE:
+		ret = dump_trp_db_syn_reg(drv, bank);
+		break;
+	}
+	if (ret)
+		return ret;
+
+	ret = qcom_llcc_clear_errors(err_type, drv);
+	if (ret)
+		return ret;
+
+	errors[err_type].func(edev_ctl, 0, bank, errors[err_type].msg);
+
+	return ret;
+}
+
+static irqreturn_t qcom_llcc_check_cache_errors
+		(struct edac_device_ctl_info *edev_ctl)
+{
+	int ret;
+	u32 drp_error;
+	u32 trp_error;
+	struct llcc_drv_data *drv = edev_ctl->pvt_info;
+	u32 i;
+	irqreturn_t irq_rc = IRQ_NONE;
+
+	for (i = 0; i < drv->num_banks; i++) {
+		/* Look for Data RAM errors */
+		ret = regmap_read(drv->regmap,
+				drv->offsets[i] + DRP_INTERRUPT_STATUS,
+				&drp_error);
+		if (ret)
+			return irq_rc;
+
+		if (drp_error & SB_ECC_ERROR) {
+			edac_printk(KERN_CRIT, EDAC_LLCC,
+				"Single Bit Error detected in Data Ram\n");
+			dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
+			irq_rc = IRQ_HANDLED;
+		} else if (drp_error & DB_ECC_ERROR) {
+			edac_printk(KERN_CRIT, EDAC_LLCC,
+				"Double Bit Error detected in Data Ram\n");
+			dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
+			irq_rc = IRQ_HANDLED;
+		}
+
+		/* Look for Tag RAM errors */
+		ret = regmap_read(drv->regmap,
+				drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
+				&trp_error);
+		if (ret)
+			return irq_rc;
+		if (trp_error & SB_ECC_ERROR) {
+			edac_printk(KERN_CRIT, EDAC_LLCC,
+				"Single Bit Error detected in Tag Ram\n");
+			dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
+			irq_rc = IRQ_HANDLED;
+		} else if (trp_error & DB_ECC_ERROR) {
+			edac_printk(KERN_CRIT, EDAC_LLCC,
+				"Double Bit Error detected in Tag Ram\n");
+			dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
+			irq_rc = IRQ_HANDLED;
+		}
+	}
+
+	return irq_rc;
+}
+
+static irqreturn_t llcc_ecc_irq_handler
+			(int irq, void *edev_ctl)
+{
+	return qcom_llcc_check_cache_errors(edev_ctl);
+}
+
+static int qcom_llcc_erp_probe(struct platform_device *pdev)
+{
+	int rc;
+	u32 ecc_irq;
+	struct edac_device_ctl_info *edev_ctl;
+	struct device *dev = &pdev->dev;
+	struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
+
+	rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
+	if (rc)
+		return rc;
+
+	/* Allocate edac control info */
+	edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1,
+				"bank", llcc_driv_data->num_banks, 1, NULL, 0,
+				edac_device_alloc_index());
+
+	if (!edev_ctl)
+		return -ENOMEM;
+
+	edev_ctl->dev = dev;
+	edev_ctl->mod_name = dev_name(dev);
+	edev_ctl->dev_name = dev_name(dev);
+	edev_ctl->ctl_name = "llcc";
+	edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
+
+	edev_ctl->pvt_info = (struct llcc_drv_data *) llcc_driv_data;
+
+	rc = edac_device_add_device(edev_ctl);
+	if (rc)
+		goto out_mem;
+
+	platform_set_drvdata(pdev, edev_ctl);
+
+	/* Request for ecc irq */
+	ecc_irq = llcc_driv_data->ecc_irq;
+	if (!ecc_irq) {
+		rc = -ENODEV;
+		goto out_dev;
+	}
+	rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
+				IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl);
+	if (rc)
+		goto out_dev;
+
+	return rc;
+
+out_dev:
+	edac_device_del_device(edev_ctl->dev);
+out_mem:
+	edac_device_free_ctl_info(edev_ctl);
+
+	return rc;
+}
+
+static int qcom_llcc_erp_remove(struct platform_device *pdev)
+{
+	struct edac_device_ctl_info *edev_ctl = dev_get_drvdata(&pdev->dev);
+
+	edac_device_del_device(edev_ctl->dev);
+	edac_device_free_ctl_info(edev_ctl);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static const struct of_device_id qcom_llcc_erp_match_table[] = {
+	{ .compatible = "qcom,llcc-erp" },
+	{ },
+};
+
+static struct platform_driver qcom_llcc_erp_driver = {
+	.probe = qcom_llcc_erp_probe,
+	.remove = qcom_llcc_erp_remove,
+	.driver = {
+		.name = "qcom_llcc_erp",
+		.of_match_table = qcom_llcc_erp_match_table,
+	},
+};
+module_platform_driver(qcom_llcc_erp_driver);
+
+MODULE_DESCRIPTION("QCOM LLCC Error Reporting");
+MODULE_LICENSE("GPL v2");
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v0 3/4] drivers: edac: Add cache erp driver for Last Level Cache Controller (LLCC)

[Borislav Petkov]

On Wed, Jul 25, 2018 at 10:44:56AM -0700, Venkata Narendra Kumar Gutta wrote:
> Add cache error reporting driver for single and double bit errors on
> Last Level Cache Controller (LLCC) cache. This driver takes care of
> dumping registers and add config options to enable and disable panic
> when these errors happen.
> 
> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>

This SOB chain doesn't make any sense - see
Documentation/process/submitting-patches.rst

> ---
>  drivers/edac/Kconfig          |  21 ++
>  drivers/edac/Makefile         |   1 +
>  drivers/edac/qcom_llcc_edac.c | 520 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 542 insertions(+)
>  create mode 100644 drivers/edac/qcom_llcc_edac.c

Needs MAINTAINERS entry so that you get all the bug reports.

> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 57304b2..68518ad 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -460,4 +460,25 @@ config EDAC_TI
>  	  Support for error detection and correction on the
>            TI SoCs.
>  
> +config EDAC_QCOM_LLCC
> +        depends on QCOM_LLCC
> +        tristate "QCOM EDAC Controller for LLCC Cache"

No edac driver per functional unit pls - see how altera_edac.c does it,
for example. IOW, this driver - if it cannot share/reuse any of the
existing edac drivers, it should be called qcom_edac and contain all the
Qualcomm-specific RAS features there.

> +        help
> +          Support for error detection and correction on the
> +          QCOM LLCC cache. Report errors caught by LLCC ECC
> +          mechanism.
> +
> +          For debugging issues having to do with stability and overall system
> +          health, you should probably say 'Y' here.
> +
> +config EDAC_QCOM_LLCC_PANIC_ON_UE
> +        depends on EDAC_QCOM_LLCC
> +        bool "Panic on uncorrectable errors - qcom llcc"
> +        help
> +          Forcibly cause a kernel panic if an uncorrectable error (UE) is
> +          detected. This can reduce debugging times on hardware which may be
> +          operating at voltages or frequencies outside normal specification.
> +
> +          For production builds, you should probably say 'N' here.
> +
>  endif # EDAC
> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
> index 02b43a7..28aff28 100644
> --- a/drivers/edac/Makefile
> +++ b/drivers/edac/Makefile
> @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)		+= altera_edac.o
>  obj-$(CONFIG_EDAC_SYNOPSYS)		+= synopsys_edac.o
>  obj-$(CONFIG_EDAC_XGENE)		+= xgene_edac.o
>  obj-$(CONFIG_EDAC_TI)			+= ti_edac.o
> +obj-$(CONFIG_EDAC_QCOM_LLCC)		+= qcom_llcc_edac.o
> diff --git a/drivers/edac/qcom_llcc_edac.c b/drivers/edac/qcom_llcc_edac.c
> new file mode 100644
> index 0000000..7a678b5
> --- /dev/null
> +++ b/drivers/edac/qcom_llcc_edac.c
> @@ -0,0 +1,520 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/edac.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/smp.h>
> +#include <linux/spinlock.h>
> +#include <linux/regmap.h>
> +#include <linux/interrupt.h>
> +#include <linux/soc/qcom/llcc-qcom.h>
> +#include "edac_mc.h"
> +#include "edac_device.h"
> +
> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
> +#define LLCC_ERP_PANIC_ON_UE 1
> +#else
> +#define LLCC_ERP_PANIC_ON_UE 0
> +#endif
> +
> +#define EDAC_LLCC	"qcom_llcc"
> +
> +#define TRP_SYN_REG_CNT	6
> +
> +#define DRP_SYN_REG_CNT	8
> +
> +#define LLCC_COMMON_STATUS0		0x0003000C
> +#define LLCC_LB_CNT_MASK		GENMASK(31, 28)
> +#define LLCC_LB_CNT_SHIFT		28
> +
> +/* single & Double Bit syndrome register offsets */
> +#define TRP_ECC_SB_ERR_SYN0		0x0002304C
> +#define TRP_ECC_DB_ERR_SYN0		0x00020370
> +#define DRP_ECC_SB_ERR_SYN0		0x0004204C
> +#define DRP_ECC_DB_ERR_SYN0		0x00042070
> +
> +/* Error register offsets */
> +#define TRP_ECC_ERROR_STATUS1		0x00020348
> +#define TRP_ECC_ERROR_STATUS0		0x00020344
> +#define DRP_ECC_ERROR_STATUS1		0x00042048
> +#define DRP_ECC_ERROR_STATUS0		0x00042044
> +
> +/* TRP, DRP interrupt register offsets */
> +#define DRP_INTERRUPT_STATUS		0x00041000
> +#define TRP_INTERRUPT_0_STATUS		0x00020480
> +#define DRP_INTERRUPT_CLEAR		0x00041008
> +#define DRP_ECC_ERROR_CNTR_CLEAR	0x00040004
> +#define TRP_INTERRUPT_0_CLEAR		0x00020484
> +#define TRP_ECC_ERROR_CNTR_CLEAR	0x00020440
> +
> +/* Mask and shift macros */
> +#define ECC_DB_ERR_COUNT_MASK	GENMASK(4, 0)

Align all those to the same vertical column.

> +#define ECC_DB_ERR_WAYS_MASK	GENMASK(31, 16)
> +#define ECC_DB_ERR_WAYS_SHIFT	BIT(4)
> +
> +#define ECC_SB_ERR_COUNT_MASK	GENMASK(23, 16)
> +#define ECC_SB_ERR_COUNT_SHIFT	BIT(4)
> +#define ECC_SB_ERR_WAYS_MASK	GENMASK(15, 0)
> +
> +#define SB_ECC_ERROR		BIT(0)
> +#define DB_ECC_ERROR		BIT(1)
> +
> +#define DRP_TRP_INT_CLEAR	GENMASK(1, 0)
> +#define DRP_TRP_CNT_CLEAR	GENMASK(1, 0)
> +
> +/* Config registers offsets*/
> +#define DRP_ECC_ERROR_CFG       0x00040000
> +
> +/* TRP, DRP interrupt register offsets */
> +#define CMN_INTERRUPT_0_ENABLE          0x0003001C
> +#define CMN_INTERRUPT_2_ENABLE          0x0003003C
> +#define TRP_INTERRUPT_0_ENABLE          0x00020488
> +#define DRP_INTERRUPT_ENABLE            0x0004100C
> +
> +#define SB_ERROR_THRESHOLD      0x1
> +#define SB_ERROR_THRESHOLD_SHIFT        24
> +#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
> +#define TRP0_INTERRUPT_ENABLE   0x1
> +#define DRP0_INTERRUPT_ENABLE   BIT(6)
> +#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
> +
> +
> +enum {
> +	LLCC_DRAM_CE = 0,
> +	LLCC_DRAM_UE,
> +	LLCC_TRAM_CE,
> +	LLCC_TRAM_UE,
> +};
> +
> +struct errors_edac {
> +	const char *msg;
> +	void (*func)(struct edac_device_ctl_info *edev_ctl,
> +				int inst_nr, int block_nr, const char *msg);
> +};
> +
> +static const struct errors_edac errors[] = {
> +	{"LLCC Data RAM correctable Error", edac_device_handle_ce},
> +	{"LLCC Data RAM uncorrectable Error", edac_device_handle_ue},
> +	{"LLCC Tag RAM correctable Error", edac_device_handle_ce},
> +	{"LLCC Tag RAM uncorrectable Error", edac_device_handle_ue},
> +};
> +
> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
> +{
> +	u32 sb_err_threshold;
> +	int ret;
> +
> +	/* Enable TRP in instance 2 of common interrupt enable register */
> +	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
> +				TRP0_INTERRUPT_ENABLE,
> +				TRP0_INTERRUPT_ENABLE);

Align arguments at the opening brace. Check the rest below too.

> +	if (ret)
> +		return ret;
> +
> +	/* Enable ECC interrupts on Tag Ram */
> +	ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
> +				SB_DB_TRP_INTERRUPT_ENABLE,
> +				SB_DB_TRP_INTERRUPT_ENABLE);
> +	if (ret)
> +		return ret;
> +
> +	/* Enable SB error for Data RAM */
> +	sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
> +	ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
> +				sb_err_threshold);
> +	if (ret)
> +		return ret;
> +
> +	/* Enable DRP in instance 2 of common interrupt enable register */
> +	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
> +				DRP0_INTERRUPT_ENABLE, DRP0_INTERRUPT_ENABLE);
> +	if (ret)
> +		return ret;
> +
> +	/* Enable ECC interrupts on Data Ram */
> +	ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
> +				SB_DB_DRP_INTERRUPT_ENABLE);
> +	return ret;
> +}
> +
> +/* Clear the error interrupt and counter registers */
> +static int qcom_llcc_clear_errors(int err_type, struct llcc_drv_data *drv)
> +{
> +	int ret = 0;
> +
> +	switch (err_type) {
> +	case LLCC_DRAM_CE:
> +	case LLCC_DRAM_UE:
> +		/* Clear the interrupt */
> +		ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
> +					DRP_TRP_INT_CLEAR);
> +		if (ret)
> +			return ret;
> +
> +		/* Clear the counters */
> +		ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
> +					DRP_TRP_CNT_CLEAR);
> +		if (ret)
> +			return ret;
> +		break;
> +	case LLCC_TRAM_CE:
> +	case LLCC_TRAM_UE:
> +		ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
> +					DRP_TRP_INT_CLEAR);
> +		if (ret)
> +			return ret;
> +
> +		ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
> +					DRP_TRP_CNT_CLEAR);
> +		if (ret)
> +			return ret;
> +		break;
> +	}
> +	return ret;
> +}
> +
> +/* Dump syndrome registers for tag Ram Double bit errors */
> +static int dump_trp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +	int i, ret;
> +	int db_err_cnt;
> +	int db_err_ways;
> +	u32 synd_reg;
> +	u32 synd_val;
> +
> +	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
> +		synd_reg = TRP_ECC_DB_ERR_SYN0 + (i * 4);
> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +				&synd_val);
> +		if (ret)
> +			return ret;
> +		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n",
> +			i, synd_val);
> +	}
> +
> +	ret = regmap_read(drv->regmap,
> +				drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
> +				&db_err_cnt);
> +	if (ret)
> +		return ret;
> +	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
> +		db_err_cnt);
> +
> +	ret = regmap_read(drv->regmap,
> +		drv->offsets[bank] + TRP_ECC_ERROR_STATUS0, &db_err_ways);
> +	if (ret)
> +		return ret;
> +	db_err_ways = (db_err_ways & ECC_DB_ERR_WAYS_MASK);
> +	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
> +
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
> +		db_err_ways);
> +
> +	return ret;
> +}
> +
> +/* Dump syndrome register for tag Ram Single Bit Errors */
> +static int dump_trp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +	int i, ret;
> +	int sb_err_cnt;
> +	int sb_err_ways;
> +	u32 synd_reg;
> +	u32 synd_val;
> +
> +	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
> +		synd_reg = TRP_ECC_SB_ERR_SYN0 + (i * 4);
> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +					&synd_val);
> +		if (ret)
> +			return ret;
> +		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n",
> +				i, synd_val);
> +	}
> +
> +	ret = regmap_read(drv->regmap,
> +				drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
> +				&sb_err_cnt);
> +	if (ret)
> +		return ret;
> +	sb_err_cnt = (sb_err_cnt & ECC_SB_ERR_COUNT_MASK);
> +	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
> +		sb_err_cnt);
> +
> +	ret = regmap_read(drv->regmap,
> +				drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
> +				&sb_err_ways);
> +	if (ret)
> +		return ret;
> +
> +	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
> +
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
> +			sb_err_ways);
> +
> +	return ret;
> +}
> +
> +/* Dump syndrome registers for Data Ram Double bit errors */
> +static int dump_drp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +	int i, ret;
> +	int db_err_cnt;
> +	int db_err_ways;
> +	u32 synd_reg;
> +	u32 synd_val;
> +
> +	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
> +		synd_reg = DRP_ECC_DB_ERR_SYN0 + (i * 4);
> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +					&synd_val);
> +		if (ret)
> +			return ret;
> +		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n",
> +				i, synd_val);
> +	}
> +
> +	ret = regmap_read(drv->regmap,
> +				drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
> +				&db_err_cnt);
> +	if (ret)
> +		return ret;
> +	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
> +		db_err_cnt);
> +
> +	ret = regmap_read(drv->regmap,
> +				drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
> +				&db_err_ways);
> +	if (ret)
> +		return ret;
> +	db_err_ways &= ECC_DB_ERR_WAYS_MASK;
> +	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
> +		db_err_ways);
> +
> +	return ret;
> +}
> +
> +/* Dump Syndrome registers for Data Ram Single bit errors*/
> +static int dump_drp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
> +{
> +	int i, ret;
> +	int sb_err_cnt;
> +	int sb_err_ways;
> +	u32 synd_reg;
> +	u32 synd_val;
> +
> +	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
> +		synd_reg = DRP_ECC_SB_ERR_SYN0 + (i * 4);
> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +					&synd_val);
> +		if (ret)
> +			return ret;
> +		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n",
> +				i, synd_val);
> +	}
> +
> +	ret = regmap_read(drv->regmap,
> +				drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
> +				&sb_err_cnt);
> +	if (ret)
> +		return ret;
> +	sb_err_cnt &= ECC_SB_ERR_COUNT_MASK;
> +	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
> +		sb_err_cnt);
> +
> +	ret = regmap_read(drv->regmap,
> +				drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
> +				&sb_err_ways);
> +	if (ret)
> +		return ret;
> +	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
> +
> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
> +		sb_err_ways);
> +
> +	return ret;
> +}
> +
> +

one newline is enough.

> +static int dump_syn_reg(struct edac_device_ctl_info *edev_ctl,
> +			 int err_type, u32 bank)
> +{
> +	int ret = 0;
> +	struct llcc_drv_data *drv = edev_ctl->pvt_info;
> +
> +	switch (err_type) {
> +	case LLCC_DRAM_CE:
> +		ret = dump_drp_sb_syn_reg(drv, bank);
> +		break;
> +	case LLCC_DRAM_UE:
> +		ret = dump_drp_db_syn_reg(drv, bank);
> +		break;
> +	case LLCC_TRAM_CE:
> +		ret = dump_trp_sb_syn_reg(drv, bank);
> +		break;
> +	case LLCC_TRAM_UE:
> +		ret = dump_trp_db_syn_reg(drv, bank);
> +		break;
> +	}
> +	if (ret)
> +		return ret;
> +
> +	ret = qcom_llcc_clear_errors(err_type, drv);
> +	if (ret)
> +		return ret;
> +
> +	errors[err_type].func(edev_ctl, 0, bank, errors[err_type].msg);
> +
> +	return ret;
> +}
> +
> +static irqreturn_t qcom_llcc_check_cache_errors
> +		(struct edac_device_ctl_info *edev_ctl)

Please don't split the function name from the args.

static irqreturn_t
qcom_llcc_check_cache_errors(struct edac_device_ctl_info *edev_ctl)

is a bit better, for example.

> +{
> +	int ret;
> +	u32 drp_error;
> +	u32 trp_error;
> +	struct llcc_drv_data *drv = edev_ctl->pvt_info;
> +	u32 i;
> +	irqreturn_t irq_rc = IRQ_NONE;
> +
> +	for (i = 0; i < drv->num_banks; i++) {
> +		/* Look for Data RAM errors */
> +		ret = regmap_read(drv->regmap,
> +				drv->offsets[i] + DRP_INTERRUPT_STATUS,
> +				&drp_error);
> +		if (ret)
> +			return irq_rc;
> +
> +		if (drp_error & SB_ECC_ERROR) {
> +			edac_printk(KERN_CRIT, EDAC_LLCC,
> +				"Single Bit Error detected in Data Ram\n");
> +			dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
> +			irq_rc = IRQ_HANDLED;
> +		} else if (drp_error & DB_ECC_ERROR) {
> +			edac_printk(KERN_CRIT, EDAC_LLCC,
> +				"Double Bit Error detected in Data Ram\n");
> +			dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
> +			irq_rc = IRQ_HANDLED;
> +		}
> +
> +		/* Look for Tag RAM errors */
> +		ret = regmap_read(drv->regmap,
> +				drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
> +				&trp_error);
> +		if (ret)
> +			return irq_rc;
> +		if (trp_error & SB_ECC_ERROR) {
> +			edac_printk(KERN_CRIT, EDAC_LLCC,
> +				"Single Bit Error detected in Tag Ram\n");
> +			dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
> +			irq_rc = IRQ_HANDLED;
> +		} else if (trp_error & DB_ECC_ERROR) {
> +			edac_printk(KERN_CRIT, EDAC_LLCC,
> +				"Double Bit Error detected in Tag Ram\n");
> +			dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
> +			irq_rc = IRQ_HANDLED;
> +		}
> +	}
> +
> +	return irq_rc;
> +}
> +
> +static irqreturn_t llcc_ecc_irq_handler
> +			(int irq, void *edev_ctl)

That looks like a useless wrapper, get rid of it.

> +{
> +	return qcom_llcc_check_cache_errors(edev_ctl);
> +}
> +
> +static int qcom_llcc_erp_probe(struct platform_device *pdev)
> +{
> +	int rc;
> +	u32 ecc_irq;
> +	struct edac_device_ctl_info *edev_ctl;
> +	struct device *dev = &pdev->dev;
> +	struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;

Please sort function local variables declaration in a reverse christmas
tree order:

	<type> longest_variable_name;
	<type> shorter_var_name;
	<type> even_shorter;
	<type> i;

Ditto for the other functions.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--

Re: [PATCH v0 3/4] drivers: edac: Add cache erp driver for Last Level Cache Controller (LLCC)

[vnkgutta]

On 2018-07-28 20:49, Borislav Petkov wrote:
> On Wed, Jul 25, 2018 at 10:44:56AM -0700, Venkata Narendra Kumar Gutta 
> wrote:
>> Add cache error reporting driver for single and double bit errors on
>> Last Level Cache Controller (LLCC) cache. This driver takes care of
>> dumping registers and add config options to enable and disable panic
>> when these errors happen.
>> 
>> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
>> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> 
> This SOB chain doesn't make any sense - see
> Documentation/process/submitting-patches.rst

Do you mean the Signed-off-by lines above? That's because
Channagoud is the one who is the original author of this driver,
and I'm the one who did the incremental changes (changes in llcc)
and uploading it upstream.
That's why the Signed-off is like that.
Which way do you think it should be?

> 
>> ---
>>  drivers/edac/Kconfig          |  21 ++
>>  drivers/edac/Makefile         |   1 +
>>  drivers/edac/qcom_llcc_edac.c | 520 
>> ++++++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 542 insertions(+)
>>  create mode 100644 drivers/edac/qcom_llcc_edac.c
> 
> Needs MAINTAINERS entry so that you get all the bug reports.
I'll update it.
> 
>> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
>> index 57304b2..68518ad 100644
>> --- a/drivers/edac/Kconfig
>> +++ b/drivers/edac/Kconfig
>> @@ -460,4 +460,25 @@ config EDAC_TI
>>  	  Support for error detection and correction on the
>>            TI SoCs.
>> 
>> +config EDAC_QCOM_LLCC
>> +        depends on QCOM_LLCC
>> +        tristate "QCOM EDAC Controller for LLCC Cache"
> 
> No edac driver per functional unit pls - see how altera_edac.c does it,
> for example. IOW, this driver - if it cannot share/reuse any of the
> existing edac drivers, it should be called qcom_edac and contain all 
> the
> Qualcomm-specific RAS features there.

Ok, I'll refactor it.


> 
>> +        help
>> +          Support for error detection and correction on the
>> +          QCOM LLCC cache. Report errors caught by LLCC ECC
>> +          mechanism.
>> +
>> +          For debugging issues having to do with stability and 
>> overall system
>> +          health, you should probably say 'Y' here.
>> +
>> +config EDAC_QCOM_LLCC_PANIC_ON_UE
>> +        depends on EDAC_QCOM_LLCC
>> +        bool "Panic on uncorrectable errors - qcom llcc"
>> +        help
>> +          Forcibly cause a kernel panic if an uncorrectable error 
>> (UE) is
>> +          detected. This can reduce debugging times on hardware which 
>> may be
>> +          operating at voltages or frequencies outside normal 
>> specification.
>> +
>> +          For production builds, you should probably say 'N' here.
>> +
>>  endif # EDAC
>> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
>> index 02b43a7..28aff28 100644
>> --- a/drivers/edac/Makefile
>> +++ b/drivers/edac/Makefile
>> @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)		+= altera_edac.o
>>  obj-$(CONFIG_EDAC_SYNOPSYS)		+= synopsys_edac.o
>>  obj-$(CONFIG_EDAC_XGENE)		+= xgene_edac.o
>>  obj-$(CONFIG_EDAC_TI)			+= ti_edac.o
>> +obj-$(CONFIG_EDAC_QCOM_LLCC)		+= qcom_llcc_edac.o
>> diff --git a/drivers/edac/qcom_llcc_edac.c 
>> b/drivers/edac/qcom_llcc_edac.c
>> new file mode 100644
>> index 0000000..7a678b5
>> --- /dev/null
>> +++ b/drivers/edac/qcom_llcc_edac.c
>> @@ -0,0 +1,520 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/edac.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/smp.h>
>> +#include <linux/spinlock.h>
>> +#include <linux/regmap.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/soc/qcom/llcc-qcom.h>
>> +#include "edac_mc.h"
>> +#include "edac_device.h"
>> +
>> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
>> +#define LLCC_ERP_PANIC_ON_UE 1
>> +#else
>> +#define LLCC_ERP_PANIC_ON_UE 0
>> +#endif
>> +
>> +#define EDAC_LLCC	"qcom_llcc"
>> +
>> +#define TRP_SYN_REG_CNT	6
>> +
>> +#define DRP_SYN_REG_CNT	8
>> +
>> +#define LLCC_COMMON_STATUS0		0x0003000C
>> +#define LLCC_LB_CNT_MASK		GENMASK(31, 28)
>> +#define LLCC_LB_CNT_SHIFT		28
>> +
>> +/* single & Double Bit syndrome register offsets */
>> +#define TRP_ECC_SB_ERR_SYN0		0x0002304C
>> +#define TRP_ECC_DB_ERR_SYN0		0x00020370
>> +#define DRP_ECC_SB_ERR_SYN0		0x0004204C
>> +#define DRP_ECC_DB_ERR_SYN0		0x00042070
>> +
>> +/* Error register offsets */
>> +#define TRP_ECC_ERROR_STATUS1		0x00020348
>> +#define TRP_ECC_ERROR_STATUS0		0x00020344
>> +#define DRP_ECC_ERROR_STATUS1		0x00042048
>> +#define DRP_ECC_ERROR_STATUS0		0x00042044
>> +
>> +/* TRP, DRP interrupt register offsets */
>> +#define DRP_INTERRUPT_STATUS		0x00041000
>> +#define TRP_INTERRUPT_0_STATUS		0x00020480
>> +#define DRP_INTERRUPT_CLEAR		0x00041008
>> +#define DRP_ECC_ERROR_CNTR_CLEAR	0x00040004
>> +#define TRP_INTERRUPT_0_CLEAR		0x00020484
>> +#define TRP_ECC_ERROR_CNTR_CLEAR	0x00020440
>> +
>> +/* Mask and shift macros */
>> +#define ECC_DB_ERR_COUNT_MASK	GENMASK(4, 0)
> 
> Align all those to the same vertical column.
Sure, I'll update it in the next patch set.
> 
>> +#define ECC_DB_ERR_WAYS_MASK	GENMASK(31, 16)
>> +#define ECC_DB_ERR_WAYS_SHIFT	BIT(4)
>> +
>> +#define ECC_SB_ERR_COUNT_MASK	GENMASK(23, 16)
>> +#define ECC_SB_ERR_COUNT_SHIFT	BIT(4)
>> +#define ECC_SB_ERR_WAYS_MASK	GENMASK(15, 0)
>> +
>> +#define SB_ECC_ERROR		BIT(0)
>> +#define DB_ECC_ERROR		BIT(1)
>> +
>> +#define DRP_TRP_INT_CLEAR	GENMASK(1, 0)
>> +#define DRP_TRP_CNT_CLEAR	GENMASK(1, 0)
>> +
>> +/* Config registers offsets*/
>> +#define DRP_ECC_ERROR_CFG       0x00040000
>> +
>> +/* TRP, DRP interrupt register offsets */
>> +#define CMN_INTERRUPT_0_ENABLE          0x0003001C
>> +#define CMN_INTERRUPT_2_ENABLE          0x0003003C
>> +#define TRP_INTERRUPT_0_ENABLE          0x00020488
>> +#define DRP_INTERRUPT_ENABLE            0x0004100C
>> +
>> +#define SB_ERROR_THRESHOLD      0x1
>> +#define SB_ERROR_THRESHOLD_SHIFT        24
>> +#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
>> +#define TRP0_INTERRUPT_ENABLE   0x1
>> +#define DRP0_INTERRUPT_ENABLE   BIT(6)
>> +#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
>> +
>> +
>> +enum {
>> +	LLCC_DRAM_CE = 0,
>> +	LLCC_DRAM_UE,
>> +	LLCC_TRAM_CE,
>> +	LLCC_TRAM_UE,
>> +};
>> +
>> +struct errors_edac {
>> +	const char *msg;
>> +	void (*func)(struct edac_device_ctl_info *edev_ctl,
>> +				int inst_nr, int block_nr, const char *msg);
>> +};
>> +
>> +static const struct errors_edac errors[] = {
>> +	{"LLCC Data RAM correctable Error", edac_device_handle_ce},
>> +	{"LLCC Data RAM uncorrectable Error", edac_device_handle_ue},
>> +	{"LLCC Tag RAM correctable Error", edac_device_handle_ce},
>> +	{"LLCC Tag RAM uncorrectable Error", edac_device_handle_ue},
>> +};
>> +
>> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
>> +{
>> +	u32 sb_err_threshold;
>> +	int ret;
>> +
>> +	/* Enable TRP in instance 2 of common interrupt enable register */
>> +	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
>> +				TRP0_INTERRUPT_ENABLE,
>> +				TRP0_INTERRUPT_ENABLE);
> 
> Align arguments at the opening brace. Check the rest below too.
Sure, I'll update them in next patch.
> 
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Enable ECC interrupts on Tag Ram */
>> +	ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
>> +				SB_DB_TRP_INTERRUPT_ENABLE,
>> +				SB_DB_TRP_INTERRUPT_ENABLE);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Enable SB error for Data RAM */
>> +	sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
>> +	ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
>> +				sb_err_threshold);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Enable DRP in instance 2 of common interrupt enable register */
>> +	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
>> +				DRP0_INTERRUPT_ENABLE, DRP0_INTERRUPT_ENABLE);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Enable ECC interrupts on Data Ram */
>> +	ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
>> +				SB_DB_DRP_INTERRUPT_ENABLE);
>> +	return ret;
>> +}
>> +
>> +/* Clear the error interrupt and counter registers */
>> +static int qcom_llcc_clear_errors(int err_type, struct llcc_drv_data 
>> *drv)
>> +{
>> +	int ret = 0;
>> +
>> +	switch (err_type) {
>> +	case LLCC_DRAM_CE:
>> +	case LLCC_DRAM_UE:
>> +		/* Clear the interrupt */
>> +		ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
>> +					DRP_TRP_INT_CLEAR);
>> +		if (ret)
>> +			return ret;
>> +
>> +		/* Clear the counters */
>> +		ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
>> +					DRP_TRP_CNT_CLEAR);
>> +		if (ret)
>> +			return ret;
>> +		break;
>> +	case LLCC_TRAM_CE:
>> +	case LLCC_TRAM_UE:
>> +		ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
>> +					DRP_TRP_INT_CLEAR);
>> +		if (ret)
>> +			return ret;
>> +
>> +		ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
>> +					DRP_TRP_CNT_CLEAR);
>> +		if (ret)
>> +			return ret;
>> +		break;
>> +	}
>> +	return ret;
>> +}
>> +
>> +/* Dump syndrome registers for tag Ram Double bit errors */
>> +static int dump_trp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
>> +{
>> +	int i, ret;
>> +	int db_err_cnt;
>> +	int db_err_ways;
>> +	u32 synd_reg;
>> +	u32 synd_val;
>> +
>> +	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
>> +		synd_reg = TRP_ECC_DB_ERR_SYN0 + (i * 4);
>> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
>> +				&synd_val);
>> +		if (ret)
>> +			return ret;
>> +		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n",
>> +			i, synd_val);
>> +	}
>> +
>> +	ret = regmap_read(drv->regmap,
>> +				drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
>> +				&db_err_cnt);
>> +	if (ret)
>> +		return ret;
>> +	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
>> +		db_err_cnt);
>> +
>> +	ret = regmap_read(drv->regmap,
>> +		drv->offsets[bank] + TRP_ECC_ERROR_STATUS0, &db_err_ways);
>> +	if (ret)
>> +		return ret;
>> +	db_err_ways = (db_err_ways & ECC_DB_ERR_WAYS_MASK);
>> +	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
>> +
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
>> +		db_err_ways);
>> +
>> +	return ret;
>> +}
>> +
>> +/* Dump syndrome register for tag Ram Single Bit Errors */
>> +static int dump_trp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
>> +{
>> +	int i, ret;
>> +	int sb_err_cnt;
>> +	int sb_err_ways;
>> +	u32 synd_reg;
>> +	u32 synd_val;
>> +
>> +	for (i = 0; i < TRP_SYN_REG_CNT; i++) {
>> +		synd_reg = TRP_ECC_SB_ERR_SYN0 + (i * 4);
>> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
>> +					&synd_val);
>> +		if (ret)
>> +			return ret;
>> +		edac_printk(KERN_CRIT, EDAC_LLCC, "TRP_ECC_SYN%d: 0x%8x\n",
>> +				i, synd_val);
>> +	}
>> +
>> +	ret = regmap_read(drv->regmap,
>> +				drv->offsets[bank] + TRP_ECC_ERROR_STATUS1,
>> +				&sb_err_cnt);
>> +	if (ret)
>> +		return ret;
>> +	sb_err_cnt = (sb_err_cnt & ECC_SB_ERR_COUNT_MASK);
>> +	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
>> +		sb_err_cnt);
>> +
>> +	ret = regmap_read(drv->regmap,
>> +				drv->offsets[bank] + TRP_ECC_ERROR_STATUS0,
>> +				&sb_err_ways);
>> +	if (ret)
>> +		return ret;
>> +
>> +	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
>> +
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
>> +			sb_err_ways);
>> +
>> +	return ret;
>> +}
>> +
>> +/* Dump syndrome registers for Data Ram Double bit errors */
>> +static int dump_drp_db_syn_reg(struct llcc_drv_data *drv, u32 bank)
>> +{
>> +	int i, ret;
>> +	int db_err_cnt;
>> +	int db_err_ways;
>> +	u32 synd_reg;
>> +	u32 synd_val;
>> +
>> +	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
>> +		synd_reg = DRP_ECC_DB_ERR_SYN0 + (i * 4);
>> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
>> +					&synd_val);
>> +		if (ret)
>> +			return ret;
>> +		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n",
>> +				i, synd_val);
>> +	}
>> +
>> +	ret = regmap_read(drv->regmap,
>> +				drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
>> +				&db_err_cnt);
>> +	if (ret)
>> +		return ret;
>> +	db_err_cnt = (db_err_cnt & ECC_DB_ERR_COUNT_MASK);
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error count: 0x%4x\n",
>> +		db_err_cnt);
>> +
>> +	ret = regmap_read(drv->regmap,
>> +				drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
>> +				&db_err_ways);
>> +	if (ret)
>> +		return ret;
>> +	db_err_ways &= ECC_DB_ERR_WAYS_MASK;
>> +	db_err_ways >>= ECC_DB_ERR_WAYS_SHIFT;
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Double-Bit error ways: 0x%4x\n",
>> +		db_err_ways);
>> +
>> +	return ret;
>> +}
>> +
>> +/* Dump Syndrome registers for Data Ram Single bit errors*/
>> +static int dump_drp_sb_syn_reg(struct llcc_drv_data *drv, u32 bank)
>> +{
>> +	int i, ret;
>> +	int sb_err_cnt;
>> +	int sb_err_ways;
>> +	u32 synd_reg;
>> +	u32 synd_val;
>> +
>> +	for (i = 0; i < DRP_SYN_REG_CNT; i++) {
>> +		synd_reg = DRP_ECC_SB_ERR_SYN0 + (i * 4);
>> +		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
>> +					&synd_val);
>> +		if (ret)
>> +			return ret;
>> +		edac_printk(KERN_CRIT, EDAC_LLCC, "DRP_ECC_SYN%d: 0x%8x\n",
>> +				i, synd_val);
>> +	}
>> +
>> +	ret = regmap_read(drv->regmap,
>> +				drv->offsets[bank] + DRP_ECC_ERROR_STATUS1,
>> +				&sb_err_cnt);
>> +	if (ret)
>> +		return ret;
>> +	sb_err_cnt &= ECC_SB_ERR_COUNT_MASK;
>> +	sb_err_cnt >>= ECC_SB_ERR_COUNT_SHIFT;
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error count: 0x%4x\n",
>> +		sb_err_cnt);
>> +
>> +	ret = regmap_read(drv->regmap,
>> +				drv->offsets[bank] + DRP_ECC_ERROR_STATUS0,
>> +				&sb_err_ways);
>> +	if (ret)
>> +		return ret;
>> +	sb_err_ways = sb_err_ways & ECC_SB_ERR_WAYS_MASK;
>> +
>> +	edac_printk(KERN_CRIT, EDAC_LLCC, "Single-Bit error ways: 0x%4x\n",
>> +		sb_err_ways);
>> +
>> +	return ret;
>> +}
>> +
>> +
> 
> one newline is enough.
Ok, I'll remove it.
> 
>> +static int dump_syn_reg(struct edac_device_ctl_info *edev_ctl,
>> +			 int err_type, u32 bank)
>> +{
>> +	int ret = 0;
>> +	struct llcc_drv_data *drv = edev_ctl->pvt_info;
>> +
>> +	switch (err_type) {
>> +	case LLCC_DRAM_CE:
>> +		ret = dump_drp_sb_syn_reg(drv, bank);
>> +		break;
>> +	case LLCC_DRAM_UE:
>> +		ret = dump_drp_db_syn_reg(drv, bank);
>> +		break;
>> +	case LLCC_TRAM_CE:
>> +		ret = dump_trp_sb_syn_reg(drv, bank);
>> +		break;
>> +	case LLCC_TRAM_UE:
>> +		ret = dump_trp_db_syn_reg(drv, bank);
>> +		break;
>> +	}
>> +	if (ret)
>> +		return ret;
>> +
>> +	ret = qcom_llcc_clear_errors(err_type, drv);
>> +	if (ret)
>> +		return ret;
>> +
>> +	errors[err_type].func(edev_ctl, 0, bank, errors[err_type].msg);
>> +
>> +	return ret;
>> +}
>> +
>> +static irqreturn_t qcom_llcc_check_cache_errors
>> +		(struct edac_device_ctl_info *edev_ctl)
> 
> Please don't split the function name from the args.
Ok, I'll update this one.
> 
> static irqreturn_t
> qcom_llcc_check_cache_errors(struct edac_device_ctl_info *edev_ctl)
> 
> is a bit better, for example.
> 
>> +{
>> +	int ret;
>> +	u32 drp_error;
>> +	u32 trp_error;
>> +	struct llcc_drv_data *drv = edev_ctl->pvt_info;
>> +	u32 i;
>> +	irqreturn_t irq_rc = IRQ_NONE;
>> +
>> +	for (i = 0; i < drv->num_banks; i++) {
>> +		/* Look for Data RAM errors */
>> +		ret = regmap_read(drv->regmap,
>> +				drv->offsets[i] + DRP_INTERRUPT_STATUS,
>> +				&drp_error);
>> +		if (ret)
>> +			return irq_rc;
>> +
>> +		if (drp_error & SB_ECC_ERROR) {
>> +			edac_printk(KERN_CRIT, EDAC_LLCC,
>> +				"Single Bit Error detected in Data Ram\n");
>> +			dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
>> +			irq_rc = IRQ_HANDLED;
>> +		} else if (drp_error & DB_ECC_ERROR) {
>> +			edac_printk(KERN_CRIT, EDAC_LLCC,
>> +				"Double Bit Error detected in Data Ram\n");
>> +			dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
>> +			irq_rc = IRQ_HANDLED;
>> +		}
>> +
>> +		/* Look for Tag RAM errors */
>> +		ret = regmap_read(drv->regmap,
>> +				drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
>> +				&trp_error);
>> +		if (ret)
>> +			return irq_rc;
>> +		if (trp_error & SB_ECC_ERROR) {
>> +			edac_printk(KERN_CRIT, EDAC_LLCC,
>> +				"Single Bit Error detected in Tag Ram\n");
>> +			dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
>> +			irq_rc = IRQ_HANDLED;
>> +		} else if (trp_error & DB_ECC_ERROR) {
>> +			edac_printk(KERN_CRIT, EDAC_LLCC,
>> +				"Double Bit Error detected in Tag Ram\n");
>> +			dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
>> +			irq_rc = IRQ_HANDLED;
>> +		}
>> +	}
>> +
>> +	return irq_rc;
>> +}
>> +
>> +static irqreturn_t llcc_ecc_irq_handler
>> +			(int irq, void *edev_ctl)
> 
> That looks like a useless wrapper, get rid of it.
Ok, Done.
> 
>> +{
>> +	return qcom_llcc_check_cache_errors(edev_ctl);
>> +}
>> +
>> +static int qcom_llcc_erp_probe(struct platform_device *pdev)
>> +{
>> +	int rc;
>> +	u32 ecc_irq;
>> +	struct edac_device_ctl_info *edev_ctl;
>> +	struct device *dev = &pdev->dev;
>> +	struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
> 
> Please sort function local variables declaration in a reverse christmas
> tree order:
> 
> 	<type> longest_variable_name;
> 	<type> shorter_var_name;
> 	<type> even_shorter;
> 	<type> i;
> 
> Ditto for the other functions.
Ok, I'll update it for all other functions too.

Re: [PATCH v0 3/4] drivers: edac: Add cache erp driver for Last Level Cache Controller (LLCC)

[Borislav Petkov]

On Mon, Jul 30, 2018 at 02:38:01PM -0700, vnkgutta@codeaurora.org wrote:
> Do you mean the Signed-off-by lines above? That's because
> Channagoud is the one who is the original author of this driver,
> and I'm the one who did the incremental changes (changes in llcc)
> and uploading it upstream.
> That's why the Signed-off is like that.
> Which way do you think it should be?

Then you need to figure out between you two who the author should be
because we have single authorship. When you do, commit it in git with

git commit --amend --author=...

so that that is reflected properly.

For expressing stuff like co-authorship we have

Co-Developed-by:

All explained in submitting-patches.rst.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--

[PATCH v0 4/4] dt-bindigs: Update documentation of qcom,llcc

[Venkata Narendra Kumar Gutta]

Add reg-names and interrupts for LLCC documentation and the usage
examples. llcc broadcast base is added in addition to llcc base,
which is used for llcc broadcast writes.

Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
index 5e85749..b4b1c86 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -18,9 +18,22 @@ Properties:
 	Value Type: <prop-encoded-array>
 	Definition: Start address and the the size of the register region.
 
+- reg-names:
+        Usage: required
+        Value Type: <stringlist>
+        Definition: Register region names. Must be "llcc_base", "llcc_bcast_base".
+
+- interrupts:
+	Usage: required
+	Definition: The interrupt is associated with the llcc edac device.
+			It's used for llcc cache single and double bit error detection
+			and reporting.
+
 Example:
 
 	cache-controller@1100000 {
 		compatible = "qcom,sdm845-llcc";
-		reg = <0x1100000 0x250000>;
+		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
+		reg-names = "llcc_base", "llcc_bcast_base";
+		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 	};
-- 
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