From: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
To: evgreen@chromium.org, robh@kernel.org, bp@alien8.de,
mchehab@kernel.org, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org, andy.gross@linaro.org,
david.brown@linaro.org, linux-arm-msm@vger.kernel.org,
linux-soc@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, devicetree@vger.kernel.org,
tsoni@codeaurora.org, ckadabi@codeaurora.org,
rishabhb@codeaurora.org
Cc: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Subject: [PATCH v0 4/4] dt-bindigs: Update documentation of qcom,llcc
Date: Wed, 25 Jul 2018 10:44:57 -0700 [thread overview]
Message-ID: <1532540697-26630-5-git-send-email-vnkgutta@codeaurora.org> (raw)
In-Reply-To: <1532540697-26630-1-git-send-email-vnkgutta@codeaurora.org>
Add reg-names and interrupts for LLCC documentation and the usage
examples. llcc broadcast base is added in addition to llcc base,
which is used for llcc broadcast writes.
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
index 5e85749..b4b1c86 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -18,9 +18,22 @@ Properties:
Value Type: <prop-encoded-array>
Definition: Start address and the the size of the register region.
+- reg-names:
+ Usage: required
+ Value Type: <stringlist>
+ Definition: Register region names. Must be "llcc_base", "llcc_bcast_base".
+
+- interrupts:
+ Usage: required
+ Definition: The interrupt is associated with the llcc edac device.
+ It's used for llcc cache single and double bit error detection
+ and reporting.
+
Example:
cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
- reg = <0x1100000 0x250000>;
+ reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
+ reg-names = "llcc_base", "llcc_bcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2018-07-25 17:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-25 17:44 [PATCH v0 0/4] Add cache erp driver for Last Level Cache Controller (LLCC) Venkata Narendra Kumar Gutta
2018-07-25 17:44 ` [PATCH v0 1/4] drivers: soc: Add broadcast base " Venkata Narendra Kumar Gutta
2018-07-25 17:44 ` [PATCH v0 2/4] drivers: soc: Support to add cache erp driver " Venkata Narendra Kumar Gutta
2018-07-25 17:44 ` [PATCH v0 3/4] drivers: edac: Add " Venkata Narendra Kumar Gutta
2018-07-29 3:49 ` Borislav Petkov
2018-07-30 21:38 ` vnkgutta
2018-07-31 4:22 ` Borislav Petkov
2018-07-25 17:44 ` Venkata Narendra Kumar Gutta [this message]
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