From mboxrd@z Thu Jan 1 00:00:00 1970 From: Erin Lo Subject: [PATCH v4 10/10] dts: arm64: mt8183: add uart node Date: Tue, 31 Jul 2018 13:38:07 +0800 Message-ID: <1533015487-60189-11-git-send-email-erin.lo@mediatek.com> References: <1533015487-60189-1-git-send-email-erin.lo@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1533015487-60189-1-git-send-email-erin.lo@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org To: Matthias Brugger , Rob Herring , Mark Rutland , Thomas Gleixner , Jason Cooper , Marc Zyngier , Greg Kroah-Hartman , Stephen Boyd Cc: devicetree@vger.kernel.org, srv_heupstream , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, yingjoe.chen@mediatek.com, erin.lo@mediatek.com, mars.cheng@mediatek.com, eddie.huang@mediatek.com, linux-clk@vger.kernel.org, Weiyi Lu List-Id: devicetree@vger.kernel.org From: Weiyi Lu Add uart node with correct uart clocks. Signed-off-by: Erin Lo Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 8 ++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 30 +++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 2a3dd5a..9b52559 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -12,6 +12,10 @@ model = "MediaTek MT8183 evaluation board"; compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; + aliases { + serial0 = &uart0; + }; + memory@40000000 { device_type = "memory"; reg = <0 0x40000000 0 0x80000000>; @@ -21,3 +25,7 @@ stdout-path = "serial0:921600n8"; }; }; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 6b87a24..c22a2dc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -170,6 +170,36 @@ #clock-cells = <1>; }; + uart0: serial@11002000 { + compatible = "mediatek,mt8183-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8183-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt8183-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + audiosys: syscon@11220000 { compatible = "mediatek,mt8183-audiosys", "syscon"; reg = <0 0x11220000 0 0x1000>; -- 1.9.1