From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aapo Vienamo Subject: [PATCH v2 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI Date: Fri, 10 Aug 2018 21:13:58 +0300 Message-ID: <1533924845-1466-2-git-send-email-avienamo@nvidia.com> References: <1533924845-1466-1-git-send-email-avienamo@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1533924845-1466-1-git-send-email-avienamo@nvidia.com> Sender: linux-kernel-owner@vger.kernel.org To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Adrian Hunter , Mikko Perttunen Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Aapo Vienamo List-Id: devicetree@vger.kernel.org Document HS400 DQS trim value device tree property. Signed-off-by: Aapo Vienamo --- Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index edecf97..32b4b4e 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -71,6 +71,7 @@ Optional properties for Tegra210 and Tegra186: trimmer value for non-tunable modes. - nvidia,default-trim : Specify the default outbound clock trimmer value. +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing Notes on the pad calibration pull up and pulldown offset values: - The property values are drive codes which are programmed into the @@ -87,6 +88,9 @@ Optional properties for Tegra210 and Tegra186: - The values are programmed to the Vendor Clock Control Register. Please refer to the reference manual of the SoC for correct values. + - The DQS trim values are only used on controllers which support + HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports + HS400. Example: sdhci@700b0000 { -- 2.7.4